Selection circuit and electronic device

Abstract

A selection circuit includes at least three control terminals; wherein: a first group of the at least three control terminals is configured to provide a first signal for controlling a first function; and a second group of the at least three control terminals is also configured to provide a second signal for controlling the first function.

Claims

1. A selection circuit, comprising: N control terminals; N selection modules; and N enable terminals configured to enable respectively the N selection modules; wherein: N is an integer greater than or equal to 3; a first group of the at least three control terminals is configured to control one or more of the N selection modules to provide a first signal for controlling a first function; a second group of the at least three control terminals is configured to control one or more of the N selection modules to provide a second signal for controlling the first function; the first group comprises only one of the N control terminals; the second group comprises at least two other control terminals of the N control terminals; each of the N selection modules has, among the N control terminals, only one control terminal as a first control terminal, and at least two other control terminals as second terminals; different selection modules correspond to different first control terminals; different selection modules correspond to different combinations of second control terminals; each selection module is configured to enable a corresponding enable terminal if only one following condition is satisfied: its first control terminal receives an on signal, or each of its second control terminals receives an on signal; each of the N selection module has a same number of N1 second control terminals; each of the N selection modules comprises: a NOT gate, an OR gate, a first AND gate, and a second AND gate; the first AND gate and the second AND gate each has N input terminals; for an n-th selection module with n being an integer between 1 and N: its first control terminal is respectively coupled with the input terminal of the NAND gate of the n-th selection module, the n-th input terminal of the first AND gate of the n-th selection module, and the n-th input terminal of the second AND gate of the selection modules other than the n-th selection module; the output terminal of the NAND gate of the n-th selection module is respectively coupled with the n-th input terminal of the second AND gate of the n-th selection module, and the n-th input terminal of the first AND gate of selection modules other than the n-th selection module; the output terminal of the first AND gate of n-th selection module is coupled with the first input terminal of the OR gate of the n-th selection module, the output terminal of the second AND gate of n-th selection module is coupled with the second input terminal of the OR gate of the n-th selection module, the output terminal of the OR gate is coupled with the enable terminal corresponding to the n-th selection module.

2. The selection circuit of claim 1, wherein N=3.

3. A selection circuit, comprising: three control terminals; three selection modules; and three enable terminals configured to enable respectively the three selection modules; wherein: a first group of the three control terminals is configured to control one or more of the three selection modules to provide a first signal for controlling a first function; a second group of the at least three control terminals is configured to control one or more of the three selection modules to provide a second signal for controlling the first function; the first group comprises only one of the three control terminals; the second group comprises two other control terminals of the three control terminals; each of the three selection modules has, among the three control terminals, only one control terminal as its first control terminal, and two other control terminals as its second terminals; different selection modules correspond to different first control terminals; different selection modules correspond to different combinations of second control terminals; each selection module is configured to enable a corresponding enable terminal if only one following condition is satisfied: its first control terminal receives an on signal, or each of its second control terminals receives an on signal; each enable terminal is configured to be enabled through at least two methods including: engaging corresponding first control terminal and disengaging all the second control terminals; or disengaging corresponding first control terminal and engaging all corresponding second control terminals.

4. The selection circuit of claim 3, wherein: an n-th selection terminal is the first control terminal of the n-th selection module; a state of enable terminal Out_1 is a; a state of enable terminal Out_2 is b; a state of enable terminal Out_3 is c; a state of control terminal In_1 is a; a state of control terminal In_2 is b; a state of control terminal In_1 is c; state logic function expressions of the enable terminals and the control terminals include: a=abc+bc, b=bc+abc, c=bc+abc.

5. An electronic device, comprising: at least N function keys; a selection circuit comprising: at least three control terminals; and at least three selection modules; wherein: a first group of the at least three control terminals is configured to control one or more of the at least three selection modules to provide a first signal for controlling a first function; and a second group of the at least three control terminals is also configured to control one or more of the at least three selection modules provide a second signal for controlling the first function; wherein each of the control terminals of the selection circuit corresponds to one of the function keys.

6. The electronic device of claim 5, wherein the electronic device comprises at least one of a mobile phone, a laptop computer, or a tablet computer.

7. The electronic device of claim 6, wherein the electronic device is a mobile phone.

8. The electronic device of claim 5, wherein for N=3, the three control terminals of the selection circuit correspond respectively to a volume up function key, a volume down function key, and a power on/off function key.

9. The electronic device of claim 8, wherein the volume up function key, the volume down function key, and the power on/off function key are physical keys.

10. The electronic device of claim 8, wherein the volume up function key, the volume down function key, and the power on/off function key are soft keys on a touch screen of the electronic device.

11. A method of controlling an electronic apparatus, wherein the electronic apparatus has at least three function keys, the method comprising: selecting at least two function keys of the at least three function keys to realize a first function of a first function key; wherein the first function corresponds to the first function key; and wherein the electronic apparatus further comprises a selection circuit, including: at least three control terminals; and at least three selection modules; wherein: a first group of the at least three control terminals is configured to control one or more of the at least three selection modules to provide a first signal for controlling the first function; and a second group of the at least three control terminals is also configured to control one or more of the at least three selection modules to provide a second signal for controlling the first function.

12. The method of claim 11, wherein each of the at least three function keys corresponds to different functions.

13. The method of claim 12, wherein the at least three function keys correspond respectively to a volume up function, a volume down function, and a power on/off function.

14. The method of claim 13, further comprising selecting both the volume up function key and the volume down function key to realize the power on/off function.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) To more clearly illustrate some of the embodiments, the following is a brief description of the drawings. The drawings in the following descriptions are only illustrative of some embodiments. For those of ordinary skill in the art, other drawings of other embodiments can become apparent based on these drawings.

(2) FIG. 1 is a schematic view of a selection circuit according to some embodiments.

(3) FIG. 2 is a schematic view of some details of a selection circuit according to some embodiments.

(4) FIG. 3 is a schematic view of an electronic device according to some embodiments.

DETAILED DESCRIPTION

(5) In the following, with reference to the drawings of various embodiments disclosed herein, the technical solutions of the embodiments of the disclosure will be described in a clear and fully understandable way. It is obvious that the described embodiments are merely a portion but not all of the embodiments of the disclosure. Based on the described embodiments of the disclosure, those ordinarily skilled in the art can obtain other embodiment(s), without any inventive work, which come(s) within the scope sought for protection by the disclosure.

(6) As illustrated in FIG. 1, a selection circuit provided by embodiments of the present disclosure comprises: N selection modules: 1_1, 1_2, . . . 1_n, . . . , 1_N; N control terminals: In_1, In_2, . . . , In_n, . . . , In N1, In_N, and a plurality of enable terminals Out_1, Out_2, . . . , Out_n, . . . , Out_N, respectively corresponding to the N selection modules; wherein, N is an integer greater than and equal to 3.

(7) For each of the selection modules 1_n, among the N control terminals (In_1, In_2, . . . , In_n, . . . , In_N), only one control terminal In_n is the corresponding first control terminal, at least two other control terminals are the corresponding second control terminals. Moreover, different selection modules 1_n correspond to different first control terminals, and different selection modules 1_n correspond to different combinations of second control terminals.

(8) Each of the selection modules 1_n enables the enable terminal corresponding to the selection module 1_n only if the corresponding first control terminal receives an on signal, or only if each of the corresponding second control terminals receives an on signal.

(9) It should be noted that, in FIG. 1 a control terminal with a circular dot representing a connection is a first control terminal, and a control terminal with a square dot representing a connection is a second control terminal.

(10) The selection circuit according to some embodiments comprises: N selection modules, N control terminals, and a plurality of enable terminals corresponding respectively to the N selection modules; wherein, N is an integer greater than or equal to 3.

(11) For each selection module, N control terminals have one and only one control terminal as the corresponding first control terminal, and among the rest of the control terminals, at least two control terminals are the corresponding second control terminal. Different selection modules correspond to different first control terminals, and different selection modules correspond to different combinations of second control terminals.

(12) Each selection module enables the enable terminal corresponding to the selection module not only when the first control terminal receives an on signal, but also when all the corresponding second control terminals receive a start terminal in the case that the first control terminal corresponding to the selection module is broken. As such, the same function can be achieved even if the first control terminal corresponding to the selection module is broken.

(13) It should be noted that, in the selection circuit according to some embodiments, different combinations of second control terminals corresponding to different selection modules refers to that for any two second control modules, their respectively corresponding selection modules are not possible to be exactly the same.

(14) In some embodiments of the selection circuit, the number of the second control terminals corresponding to each selection module is the same. This allows the number of wires for each selection module to be the same, and the structures of each selection module can be the same. As such, the selection modules can be more conveniently produced.

(15) In the selection circuit according to some embodiments, each selection module corresponds to N1 second control terminals. That is, for each selection module, among the N control terminals, only one control terminal is the corresponding first control terminal, and all the other control terminals are the corresponding second terminals.

(16) As such, each enable terminal can be enabled through two methods. In the first method, the corresponding first control terminal receives an on signal, and all the second control terminals receive an off signal. In the second method, the corresponding first control terminal receives an off signal, and all of the corresponding second control terminals receive an on signal.

(17) For example, in the case that the n-th selection terminal is the corresponding first control terminal of the n-th selection module and N=3, assuming the state of the enable terminal Out_1 is a, the state of the enable terminal Out_2 is b, the state of the enable terminal Out_3 is c, the state of the control terminal In_1 is a, the state of control terminal In_2 is b, the state of the control terminal In_1 is c, the state logic function expressions of the enable terminals and the control terminals are: a=abc+bc, b=bc+abc, c=bc+abc.

(18) In some embodiments of the selection circuit, as illustrated in FIG. 2, taking N=3 as an example, each of the selection modules 1_1, 1_2, and 1_3 comprises: a NOT gate, an OR gate, a first AND gate, and a second AND gate; wherein, the first AND gate and the second AND gate each has N input terminals; for the n-th selection module 1_n, n is an integer between 1N. In the example illustrated in FIG. 2 with N=3, n can be 1, 2, or 3.

(19) The corresponding first control terminal, which in the example illustrated in FIG. 2 is the n-th control terminal In_n corresponding to the n-th selection module 1_n, is respectively coupled with the input terminal of NOT gate A of the n-th selection module 1_n, the n-th input terminal of the first AND gate C of the n-th selection module, and the n-th input terminal of the second AND gate D of selection modules other than the n-th selection module 1_n.

(20) The output terminal of the NOT gate A of the n-th selection module 1_n is respectively coupled with the n-th input of the second AND gate D of the n-th selection module 1_n, and the n-th input terminal of the first AND gate C of selection modules other than the n-th selection module 1_n.

(21) The output terminal of the first AND gate C of the n-th selection module 1_n is coupled with the first input terminal of the OR gate B of the n-th selection module 1_n, the output terminal of the second AND gate D of the n-th selection module 1_n is coupled with the second input terminal of the OR gate B of the n-th selection module 1_n, the output terminal of the OR gate B is coupled with the enable terminal Out_n corresponding to the n-th selection module 1_n:

(22) It is noted that the above-described structures of the selection module are for illustration purpose only, and the selection modules according to embodiments disclosed herein are not limited to the illustrative structures.

(23) Because the larger the value of N is, the more complex the structure of the whole selection circuit becomes, in some embodiments, N is predetermined to be 3. Such a relatively simple selection circuit can be set only for frequently-used function keys in electronic devices.

(24) In some embodiments, the selection circuit has two second control terminals corresponding to each of the selection modules. Because when the selection circuit is employed by an electronic device, each control terminal corresponds to one function key, therefore, the more the second control terminals corresponding to each selection module, the more number of function keys need to be pressed at the same time to engage corresponding enable terminals, and it becomes cumbersome to operate

(25) In the following, using the selection circuit as shown in FIG. 2 as an example, the working principles of the selection circuit according to some embodiments are described, wherein 1 denotes the on signal and 0 denotes the off

(26) In the first case, when In_1=1, In_2=0, In_3=0:

(27) For the first selection module 1_1, the signal of each of the three input terminals of its first AND gate is 1. Therefore, the signal of the output terminal of the first AND gate C, i.e., the input terminal of the OR gate B is 1; the signal of each of the three input terminals of the AND gate is 0, therefore the signal of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 0. Because the signals of the two input terminals of the OR gate B are respectively 1, and 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is 1, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is enabled.

(28) For the second selection module 1_2, the signal of each of the three input terminals of its first AND gate C is respectively 0, 0, and 1. Therefore, the signal of the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0; the signals of three input terminals of the second AND gate D are respectively 1, 1, and 0. Therefore, the signal of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 0. Because the signals of the two input terminal of the OR gate B are both 0, the signal of the output terminal of the OR gate B, i.e., the signal of the enable terminal Out_2 corresponding to the second selection module 1_2 is 0, i.e., the enable terminal Out_2 corresponding to the second selection module 1_2 is not enabled.

(29) For the third selection module 1_3, the signals of the three input terminals of the first AND gate C are respectively 0, 1, and 0. Therefore, the signal of the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are respectively 1, 0, and 1. Therefore, the signal of the output terminal of the second AND gate D, i.e., the signal of the second input terminal of the OR gate B is 0; because the signals of the two input terminals of the OR gate B are both 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is 0, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is not enabled.

(30) Specifically, the signal of each of the gates of each of the modules is shown in the following table 1.

(31) TABLE-US-00001 TABLE 1 In_1 = 1 In_2 = 0 In_3 = 0 1_1 1_2 1_3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 1 1 1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 b1 b2 b1 b2 b1 b2 1 0 0 0 0 0 Out_1 Out_2 Out_3 1 0 0

(32) In the second case: when In_1=0, In_2=1, In_3=1:

(33) For the first selection module 1_1, signals of the three input terminals of its first AND gate C are all 0, therefore the signal of the output terminal of the first AND gate C, i.e. the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are all 1. Therefore, the signal of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 1; because the signals of the two input terminals of the OR gate B are respectively 0 and 1, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is 1, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is enabled.

(34) For the second selection module 1_2, the signals of the three input terminals of its first AND gate C are respectively 1, 1, and 0, therefore the signal of the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0, the signals of the three input terminals of the second AND gate D are respectively 0, 0, and 1, therefore the output terminals of the second AND gate D, i.e., the second input terminal of the OR gate B is 0. Because the signals of the two input terminals of the OR gate B are all 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_2 corresponding to the second selection module 1_2 is 0, i.e., the enable terminal Out_2 corresponding to the second selection module 1_2 is not enabled.

(35) For the third selection module 1_3, the signals of the three input terminals of its first AND gate C are respectively 1, 0 and 1, therefore the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are respectively 0, 1, 0, therefore the signals of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 0; because the signals of the two input terminals of the OR gate B are all 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is 0, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is not enabled.

(36) Specifically, the signal of the input terminals of each gate of each of the selection module is shown in table 2 below.

(37) TABLE-US-00002 TABLE 2 In_1 = 0 In_2 = 1 In_3 = 1 1_1 1_2 1_3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 0 b1 b2 b1 b2 b1 b2 0 1 0 0 0 0 Out_1 Out_2 Out_3 1 0 0

(38) In the third case: when In_1=0, In_2=1, In_3=0:

(39) For the first selection module 1_1, signals of the three input terminals of its first AND gate C are respectively 0, 0, and 1, therefore the signal of the output terminal of the first AND gate C, i.e. the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are respectively 1, 1, and 0. Therefore, the signal of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 0; because the signals of the two input terminals of the OR gate B are all 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is 0, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is not enabled.

(40) For the second selection module 1_2, the signals of the three input terminals of its first AND gate C are respectively all 1, therefore the signal of the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 1; the signals of the three input terminals of the second AND gate D are all 0, therefore the output terminals of the second AND gate D, i.e., the second input terminal of the OR gate B is 0; because the signals of the two input terminals of the OR gate B are respectively 1 and 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_2 corresponding to the second selection module 1_2 is 1, i.e., the enable terminal Out_2 corresponding to the second selection module 1_2 is enabled.

(41) For the third selection module 1_3, the signals of the three input terminals of its first AND gate C are respectively 1, 0 and 0, therefore the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are respectively 0, 1, 1, therefore the signals of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 0; because the signals of the two input terminals of the OR gate B are all 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is 0, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is not enabled.

(42) Specifically, the input signal of each gate of each of the selection modules is shown in table 3 below.

(43) TABLE-US-00003 TABLE 3 In_1 = 0 In_2 = 1 In_3 = 0 1_1 1_2 1_3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 0 0 1 1 1 0 1 1 1 0 0 0 1 0 0 0 1 1 b1 b2 b1 b2 b1 b2 0 0 1 0 0 0 Out_1 Out_2 Out_3 0 1 0

(44) In the fourth case: when In_1=1, In_2=0, In_3=1:

(45) For the first selection module 1_1, signals of the three input terminals of its first AND gate C are respectively 1, 1 and 0, therefore the signal of the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are respectively 0, 0, and 1, therefore, the signal of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 0; since the signals of the two input terminals of the OR gate B are all 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is 0, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is not enabled.

(46) For the second selection module 1_2, the signals of the three input terminals of its first AND gate C are respectively all 0, therefore the signal of the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are all 1, therefore the output terminals of the second AND gate D, i.e., the second input terminal of the OR gate B is 1; since the signals of the two input terminals of the OR gate B are respectively 0 and 1, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_2 corresponding to the second selection module 1_2 is 1, i.e., the enable terminal Out_2 corresponding to the second selection module 1_2 is enabled.

(47) For the third selection module 1_3, the signals of the three input terminals of its first AND gate C are respectively 0, 1, and 1, therefore the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are respectively 1, 0, and 0, therefore the signals of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 0; since the signals of the two input terminals of the OR gate B are all 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is 0, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is not enabled.

(48) Specifically, the input signal of each gate of each of the selection modules is shown in table 4 below.

(49) TABLE-US-00004 TABLE 4 In_1 = 1 In_2 = 0 In_3 = 1 1_1 1_2 1_3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 1 1 0 0 0 1 0 0 0 1 1 1 0 1 1 1 0 0 b1 b2 b1 b2 b1 b2 0 0 0 1 0 0 Out_1 Out_2 Out_3 0 1 0

(50) In the fifth case: when In_1=0, In_2=0, In_3=1:

(51) For the first selection module 1_1, signals of the three input terminals of its first AND gate C are respectively 0, 1, and 0, therefore the signal of the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are respectively 1, 0, and 1, therefore, the signal of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 0; since the signals of the two input terminals of the OR gate B are all 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is 0, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is not enabled.

(52) For the second selection module 1_2, the signals of the three input terminals of its first AND gate C are respectively 1, 0 and 0, therefore the signal of the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are respectively 0, 1, and 1, therefore the output terminals of the second AND gate D, i.e., the second input terminal of the OR gate B is 0; since the signals of the two input terminals of the OR gate B are all 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_2 corresponding to the second selection module 1_2 is 0, i.e., the enable terminal Out_2 corresponding to the second selection module 1_2 is not enabled.

(53) For the third selection module 1_3, the signals of the three input terminals of its first AND gate C are all 1, therefore the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 1; the signals of the three input terminals of the second AND gate D are all 0, therefore the signals of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 0; because the signals of the two input terminals of the OR gate B are respectively 1 and 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is 1, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is enabled.

(54) Specifically, the input signal of each gate of each of the selection modules is shown in Table 5 below.

(55) TABLE-US-00005 TABLE 5 In_1 = 0 In_2 = 0 In_3 = 1 1_1 1_2 1_3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 0 1 0 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 b1 b2 b1 b2 b1 b2 0 0 0 0 1 0 Out_1 Out_2 Out_3 0 0 1

(56) In the sixth case, when In_1=1, In_2=1, In_3=0:

(57) For the first selection module 1_1, signals of the three input terminals of its first AND gate C are respectively 1, 0, and 1, therefore the signal of the output terminal of the first AND gate C, i.e. the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are respectively 0, 1, and 0, therefore, the signal of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 0; since the signals of the two input terminals of the OR gate B are all 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is 0, i.e., the enable terminal Out_1 corresponding to the first selection module 1_1 is not enabled.

(58) For the second selection module 1_2, the signals of the three input terminals of its first AND gate C are respectively 0, 1, and 1, therefore the signal of the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are respectively 1, 0, and 0, therefore the output terminals of the second AND gate D, i.e., the second input terminal of the OR gate B is 0; since the signals of the two input terminals of the OR gate B are all 0, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_2 corresponding to the second selection module 1_2 is 0, i.e., the enable terminal Out_2 corresponding to the second selection module 1_2 is not enabled.

(59) For the third selection module 1_3, the signals of the three input terminals of its first AND gate C are all 0, therefore the output terminal of the first AND gate C, i.e., the first input terminal of the OR gate B is 0; the signals of the three input terminals of the second AND gate D are all 1, therefore the signals of the output terminal of the second AND gate D, i.e., the second input terminal of the OR gate B is 1; since the signals of the two input terminals of the OR gate B are respectively 0 and 1, the signal of the output terminal of the OR gate B, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is 1, i.e., the enable terminal Out_3 corresponding to the third selection module 1_3 is enabled.

(60) Specifically, the input signal of each gate of each of the selection modules is shown in Table 6 below.

(61) TABLE-US-00006 TABLE 6 In_1 = 1 In_2 = 1 In_3 = 0 1_1 1_2 1_3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 c1 c2 c3 d1 d2 d3 1 0 1 0 1 0 0 1 1 1 0 0 0 0 0 1 1 1 b1 b2 b1 b2 b1 b2 0 0 0 0 0 1 Out_1 Out_2 Out_3 0 0 1

(62) It should be noted that, in Table 1-Table 6, c1, c2 and c3 respectively represent the first input terminal, the second input terminal, and the third input terminal of the first AND gate C, d1, d2 and d3 respectively represent the first input terminal, the second input terminal, and the third input terminal of the second AND gate D, and b1 and b2 respectively represent the first input terminal and the second input terminal of the OR gate B.

(63) Based on the same inventive conception, embodiments of the present disclosure also provide an electronic device. As illustrated in FIG. 3, the electronic device comprises at least N function keys: X1, X2, . . . , Xn, . . . , XN (in the example shown in FIG. 3, N=3), and further comprises the selection modules described above according to some embodiments of the present disclosure. Each control terminal In_n corresponds to a function key Xn.

(64) For the electronic device according to some embodiments, when the function key corresponding to the control terminal of the selection module is turned on, the on signal is output to the corresponding control terminal.

(65) In some embodiments, the electronic device can be a mobile phone, a laptop computer, a tablet computer, etc.

(66) Taking a mobile phone as an example, because the volume up function key, the volume down function key, and power-on function key are used frequently, these three function keys can correspond to the selection module. That is, in the selection module, N=3, each of the three control terminals in the selection module respectively corresponds to the volume-up function key, the volume-down function key, and the power-on function key of the mobile phone.

(67) Embodiments of the present disclosure provide a selection circuit and an electronic device, comprising: N selection modules, N control terminals, and enable terminals corresponding respectively to each selection module respectively; wherein, N is an integer greater than and equal to 3; for each selection module, among the N control terminals one and only one is the corresponding first control terminal; among the remaining of the control terminals, at least two control terminals are the corresponding second control terminal. Different selection modules correspond to different first control terminals, different selection modules correspond to different combinations of second control terminals. Because each selection module enables the enable terminal corresponding to the selection module not only if the first control terminal receives an on signal, but also if all the corresponding second control terminals receive an on signal in the case the first control terminal corresponding to the selection module is broken.

(68) Although specific embodiments have been described above in detail, the description is merely for purposes of illustration. It should be appreciated, therefore, that many aspects described above are not intended as required or essential elements unless explicitly stated otherwise. Various modifications of, and equivalent acts corresponding to, the disclosed aspects of the exemplary embodiments, in addition to those described above, can be made by a person of ordinary skill in the art, having the benefit of the present disclosure, without departing from the spirit and scope of the disclosure defined in the following claims, the scope of which is to be accorded the broadest interpretation so as to encompass such modifications and equivalent structures.