Method for improving spurious free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) of capacitor-resistor combined successive approximation register (SAR) analog-to-digital converter (ADC) by capacitor re-configuration

Abstract

A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C.sub.1-C.sub.128; and 4) selecting 64 groups of capacitors from C.sub.33 to C.sub.96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.

Claims

1. A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter, the method comprising: arranging 128 unit capacitors in each of a positive array and a negative array of a capacitor-resistor combined successive approximation register analog-to-digital converter, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; connecting one capacitor of a first group in the positive array to a positive reference voltage input (VREFP) and connecting the other capacitor of the first group in the negative array to a negative reference voltage input (VREFN), while connecting capacitors of remaining groups in the positive array to the VREFN and connecting capacitors of remaining groups in the negative array connect to the VREFP, and allowing the analog-to-digital converter successive approximation register to work at a 15-bit mode for conventional bit cycling to obtain a digital code corresponding to capacitors of the first group; and repeating the above process on capacitors of subsequent groups until 128 digital codes corresponding to the 128 groups of capacitors are obtained; sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained, and recording the 128 groups of capacitors after sorting as C.sub.1-C.sub.128; and selecting 64 groups of capacitors from C.sub.33 to C.sub.96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter according to an order as follows: C.sub.33, C.sub.96, C.sub.35, C.sub.94, C.sub.37, C.sub.92, C.sub.39, C.sub.90, C.sub.41, C.sub.88, C.sub.43, C.sub.86, C.sub.45, C.sub.84, C.sub.47, C.sub.82, C.sub.49, C.sub.80, C.sub.51, C.sub.78, C.sub.53, C.sub.76, C.sub.55, C.sub.74, C.sub.57, C.sub.72, C.sub.59, C.sub.70, C.sub.61, C.sub.68, C.sub.63, C.sub.66, C.sub.65, C.sub.64, C.sub.67, C.sub.62, C.sub.69, C.sub.60, C.sub.71, C.sub.58, C.sub.73, C.sub.56, C.sub.75, C.sub.54, C.sub.77, C.sub.52, C.sub.79, C.sub.50, C.sub.81, C.sub.48, C.sub.83, C.sub.46, C.sub.85, C.sub.44, C.sub.87, C.sub.42, C.sub.89, C.sub.40, C.sub.91, C.sub.38, C.sub.93, C.sub.36, C.sub.95, and C.sub.34.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention is described hereinbelow with reference to the accompanying drawings, in which:

(2) FIG. 1 is a circuit diagram of a conventional 14-bit capacitor-resistor architecture SAR ADC, in which, a 6-bit main capacitive DAC and an 8-bit sub-resistive DAC for a total of 14-bit conversion are configured, and the 6-bit main capacitive DAC comprises 64 unit capacitors;

(3) FIGS. 2A-2F illustrate a capacitor re-configuring method in accordance with one embodiment of the invention;

(4) FIG. 3 is a circuit diagram of a 14-bit capacitor-resistor architecture SAR ADC in accordance with one embodiment of the invention;

(5) FIG. 4 is a circuit diagram adopted by a capacitor measurement method in accordance with one embodiment of the invention;

(6) FIG. 5 is a chart of 500 Monte Carlo SI-DR simulation results for conventional 14-bit SAR ADC (.sub.u=0.3%);

(7) FIG. 6 is a chart of 500 Monte Carlo SFDR simulation results for 14-bit SAR ADC with capacitor re-configuring (.sub.u=0.3%) in accordance with one embodiment of the invention;

(8) FIG. 7 is a chart of 500 Monte Carlo SNDR simulation results for conventional 14-bit SAR ADC (.sub.u=0.3%); and

(9) FIG. 8 is a chart of 500 Monte Carlo SNDR simulation results for 14-bit SAR ADC with capacitor re-configuring (.sub.u=0.3%) in accordance with one embodiment of the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(10) For further illustrating the invention, experiments detailing a method for improving a SI-DR and a SNDR of a capacitor-resistor combined SAR analog-to-digital converter by capacitor re-configuration are described below. It should be noted that the following examples are intended to describe and not to limit the invention.

(11) Capacitor re-configuring method is proposed to enhance the linearity of capacitor-resistor combined SAR ADC by splitting the conventional binary capacitors into unary capacitors and adding some extra unit capacitors. The more unit capacitors added, the better the performance related to SFDR and SNDR, but more power is consumed. Here, only 64 groups of unit capacitors are added for compromises. The details of capacitor-reconfiguring technique proposed are shown in FIG. 2A.

(12) As well known, the conventional 6-bit binary capacitive DAC contains 64 unit capacitors in the positive array, and the negative capacitor array is symmetrical with the positive capacitor array, so only positive array is described here for simplicity. Unary architecture is applied to achieve optimum static linearity (FIG. 2B), also, it is convenient to implement the capacitor re-configuring scheme with unary capacitive architecture. At first, extra 64 unit capacitors are added, shown in FIG. 2C. Then, values of all the 128 capacitors are measured. Measurement of each capacitor is shown in FIG. 3, first, the first capacitor in the positive array is connected to positive reference voltage input (VREFP) while the remaining capacitors are kept to negative reference voltage input (VREFN), and the first capacitor in the negative array is connected to VREFN while the remaining capacitors are kept to VREFP, and a difference between top plates of positive and negative array corresponds to a proportion of the first capacitor. The conventional bit-cycling are proceeded, during the bit-cycling, the SAR ADC works at 15-bit mode to measure the value of the first capacitor, which means all the 128 capacitors work as a 7-bit capacitive main DAC prior to 8-bit resistor-string sub DAC, after measuring the first capacitor. The value of the second capacitor is measured with the same procedure, which repeats till values of all the 128 capacitors have been measured. After measuring the values of all 128 capacitors, the 128 capacitors are sorted from biggest to smallest, as shown in FIG. 2D), C.sub.1 is the biggest and the C.sub.128 is the smallest one. 32 capacitors in front and in the rear are respectively removed, and only the 64 capacitors in the middle (from C.sub.33 to C.sub.96 as shown in FIG. 2E) are reserved. C.sub.33 to C.sub.96 are used for the 6-bit capacitive DAC in FIG. 1, then the most important point is: the 64 capacitors (from C33 to C96) are re-ordered by one head and one tail with the capacitors of the odd-number position keep unchanged as follows: C.sub.33, C.sub.96, C.sub.35, C.sub.94, C.sub.37, C.sub.92, C.sub.39, C.sub.90, C.sub.41, C.sub.88, C.sub.43, C.sub.86, C.sub.45, C.sub.84, C.sub.47, C.sub.82, C.sub.49, C.sub.80, C.sub.51, C.sub.78, C.sub.\53, C.sub.76, C.sub.55, C.sub.74, C.sub.57, C.sub.72, C.sub.59, C.sub.70, C.sub.61, C.sub.68, C.sub.63, C.sub.66, C.sub.65, C.sub.64, C.sub.67, C.sub.62, C.sub.69, C.sub.60, C.sub.71, C.sub.58, C.sub.73, C.sub.56, C.sub.75, C.sub.54, C.sub.77, C.sub.52, C.sub.79, C.sub.50, C.sub.81, C.sub.48, C.sub.83, C.sub.46, C.sub.85, C.sub.44, C.sub.87, C.sub.42, C.sub.89, C.sub.40, C.sub.91, C.sub.38, C.sub.93, C.sub.36, C.sub.95, C.sub.34, shown in FIG. 2F. Finally, the re-ordered 64 unit capacitors proceed with the normal binary search conversion.

(13) Simulation Results:

(14) To evaluate the improvement on the SFDR and SNDR of 14-bit capacitor-resistor combined ADC, the ADC is simulated in MATLAB instead of Cadence to avoid other circuit non-idealities, because the effectiveness of the calibration method is more concerned. In addition, MATLAB allows us to run extensive Monte Carlo simulations, which otherwise will be extremely time consuming to run in Cadence. In the simulation, only the capacitor mismatch is considered. The capacitor mismatch for every capacitor is randomly generated and the values of the unit capacitors are taken to be Gaussian random variables with standard deviations of 0.3%.

(15) FIG. 5 and FIG. 6 show 500 Monte Carlo SFDR simulation results for 14-bit SAR ADC with respectively conventional and capacitor re-configuring with .sub.u=0.3%. In FIG. 5, without capacitor re-configuring technique, the worst-case and the averaged SFDR are 65.8 dB and 75.9 dB respectively with .sub.u=0.3%. After using the capacitor re-configuring technique, as shown in FIG. 6, the averaged SFDR are improved from 75.9 dB to 95.4 dB. On the other hand, the improvement of SNDR is obvious by comparing FIG. 7 and FIG. 8, the averaged SNDR are improved from 70.4 dB to 82.7 dB

(16) Table 1 and Table 2 conclude 500 Monte Carlo SFDR and SNDR simulation results. In table 1, by using the capacitor re-configuring technique, the improvements of the averaged SFDR is 19.5 dB, also, 12.3 dB improvement of averaged SNDR is achieved in Table 2.

(17) TABLE-US-00001 TABLE 1 Comparison of SFDR between conventional and proposed 14-bit ADC SFDR_min (dB) SFDR_mean (dB) Conventional 14-bit SAR ADC 65.8 75.9 14-bit SAR ADC with capacitor 84.6 95.4 re-configuring

(18) TABLE-US-00002 TABLE 2 Comparison of SNDR between conventional and proposed 14-bit ADC SNDR_min (dB) SNDR_mean (dB) Conventional 14-bit SAR ADC 61.9 70.4 14-bit SAR ADC with capacitor 78.9 82.7 re-configuring

(19) Capacitor re-configuring proposed in the invention is adaptable to any kind of capacitive SAR ADC. The Simulation results demonstrate excellent SFDR and SNDR improvements by using the capacitor re-configuring method of the invention.

(20) Unless otherwise indicated, the numerical ranges involved in the invention include the end values. While particular embodiments of the invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects, and therefore, the aim in the appended claims is to cover all such changes and modifications as fall within the true spirit and scope of the invention.