Computing device processing expanded data

Abstract

The present invention relates to a computing device for executing a first cryptographic operation of a cryptographic process on useful input data, said computing device comprising a first processor, a second processor and a selection circuit wherein: —said selection circuit is configured: —for receiving, from an input bus, expanded input data obtained by interleaving dummy input data with said useful input data, —for determining positions of the dummy input data in said expanded input data, —and for extracting said dummy input data and said useful input data from the expanded input data based on said determined positions, —said first processor is configured for executing said first cryptographic operation of said cryptographic process on said extracted useful input data to obtain useful output data, —said second processor is configured for executing a second operation on said extracted dummy input data to obtain dummy output data, said computing device being configured for having said operations executed such that leakage generated by said first cryptographic operation is jammed by leakage generated by the second operation.

Claims

1. An apparatus for performing cryptographic operations, comprising: a computing device for executing a first cryptographic operation of a cryptographic process on a first input data; said computing device having a first processor, a second processor and a selection circuit, wherein: said selection circuit of said computing device is configured: for receiving, from an input bus, expanded input data obtained by interleaving dummy input data with said first input data, for determining positions of said dummy input data in said expanded input data; and for extracting said dummy input data and said first input data from said expanded input data based on said determined positions; said first processor is configured for executing said first cryptographic operation of said cryptographic process on said extracted first input data to obtain first output data; said second processor is configured for executing a second operation, in parallel with said first processor executing said first cryptographic operation, on said extracted dummy input data to obtain dummy output data; and an expansion circuit configured for interleaving said dummy output data with said first output data to obtain expanded output data, whereby the computing device jams leakage from operations executed by said first cryptographic operation by leakage generated by said second operation; an external expansion circuit, connected to said selection circuit of the computing device via an input bus; and an external selection circuit connected via an output bus to said expansion circuit of the computing device; wherein: said external expansion circuit is configured for interleaving said dummy input data with said first input data to obtain said expanded input data received by the selection circuit from said input bus, said dummy input data being uncorrelated with said first input data; said external selection circuit being configured: for accessing, through said output bus, said expanded output data; for determining positions of said dummy output data in said expanded output data; and for extracting said first output data from said expanded output data based on said determined positions; and wherein said computing device is configured for using said first output data in a subsequent operation of the cryptographic process or is configured for storing said first output data in an external memory as a result of the cryptographic process.

2. The apparatus of claim 1 wherein said first cryptographic operation is a block cipher operation.

3. The apparatus of claim 1 where said computing device is among a computer, a smart card, a hardware security module and a system on chip.

4. The apparatus of claim 1, wherein determining positions of said dummy data in said expanded data comprises receiving said positions from said bus.

5. The apparatus of claim 4, wherein said positions are randomly generated positions.

6. The apparatus of claim 1, wherein said positions of said dummy data in said expanded data are predetermined and stored in said computing device or by said external selection circuit.

7. The apparatus of claim 1, wherein said first input data, said dummy input data, said expanded input data are sequences of bits and wherein said dummy input data are bit values randomly generated by the expansion circuit of the computing device or the external expansion circuit.

8. The apparatus of claim 1, wherein said first input data, said dummy input data, said expanded input data are sequences of bits and wherein said expansion circuit of the computing device and said external expansion circuit are configured for interleaving said dummy input data with said first input data to obtain said expanded input data using an insertion sequence and a positions random number such that for each bit in said positions random number with a first value, a bit of said expanded data is selected from said insertion sequence and for each bit in said positions random number with a second value, a bit of said expanded data is selected from said first input data.

9. The apparatus of claim 8, wherein said expansion circuit of the computing device and said external expansion circuit are configured for generating said insertion sequence randomly or for using a predetermined insertion sequence.

10. The apparatus of claim 1, wherein determining positions of said dummy data in said expanded data comprises receiving said positions from said bus.

11. The apparatus of claim 10, wherein said positions are randomly generated positions.

12. The apparatus of claim 1, wherein said positions of said dummy data in said expanded data are predetermined and stored in said computing device or by said external selection circuit.

13. The apparatus of claim 1, wherein said first input data, said dummy input data, said expanded input data are sequences of bits and wherein said dummy data are bit values randomly generated by said expansion circuit of said computing device or said external expansion circuit.

14. The apparatus of claim 1, wherein said first input data, said dummy input data, said expanded input data are sequences of bits and wherein said expansion circuit and said external expansion circuits are configured for interleaving said dummy input data with said first input data to obtain said expanded input data using an insertion sequence and a positions random number such that for each bit in said positions random number with a first value, a bit of said expanded data is selected from said insertion sequence and for each bit in said positions random number with a second value, a bit of said expanded input data is selected from said first input data.

15. The apparatus of claim 14, wherein said expansion circuits are configured for generating said insertion sequence randomly or for using a predetermined insertion sequence.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The following description and the annexed drawings set forth in detail certain illustrative aspects and are indicative of but a few of the various ways in which the principles of the embodiments may be employed. Other advantages and novel features will become apparent from the following detailed description when considered in conjunction with the drawings and the disclosed embodiments are intended to include all such aspects and their equivalents.

(2) FIG. 1 is a schematic illustration of a system according to the present invention;

(3) FIG. 2 is a schematic illustration of a computing device according to an embodiment of the present invention;

(4) FIG. 3 is a schematic detailed illustration of a computing device according to an embodiment of the present invention;

(5) FIG. 4 is a schematic illustration of the processing of sensitive and non-sensitive operations according to the invention;

(6) FIG. 5 is a schematic illustration of a circuit arrangement according to an embodiment of the present invention;

(7) FIG. 6 is a schematic illustration of an option to manage the positions of the dummy data and/or the useful data in the expanded data according to the invention;

(8) FIG. 7 illustrates a method according to an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

(9) In the description detailed below, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The description detailed below is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled.

(10) The invention aims at providing a new hardware architecture for a computing device performing cryptographic operations such as block cipher operations, and an associated method, such that these operations are protected against side-channel attacks.

(11) As depicted on FIG. 1, such a computing device 101, according to a first aspect of the invention, may be a stand-alone device connected to a personal computer or server 102 operated by a user and sending commands to the computing device for cryptographic operations such as data encryption or decryption using a block cipher algorithm such as the Advanced Encryption Standard (AES) algorithm, the Data Encryption Standard (DES), Blowfish, Serpent or Gost algorithms. Alternatively, the computing device 101 may be embedded in the computer 102.

(12) The computing device 101 may be a tamper resistant device secured against any unauthorized access. The computing device 101 may for example be a smart card, a hardware security module or a system on a chip.

(13) FIG. 2 is a schematic illustration of the computing device 101. The computing device 101 may include a processing system 201, connected via a bus 202 to a computer readable memory circuit including a random access memory (RAM) 203, a read-only memory (ROM) 204, and/or a non-volatile memory (NVM) 205. The computing device 101 may further include an interface 206 used to connect the computing device 101 to the computer 102. Such an interface may be either a wired interface such as a USB, Ethernet or Thunderbolt interface, or a wireless interface, such as a Bluetooth interface. The interface 206 may also be used to connect the computing device 101 to a wireless network, e.g., wide-area networks, WiFi networks, or mobile telephony networks through which communication may be performed with the computer 102.

(14) In order to avoid leaking information about operations computed by the computing device when such operations are executed by the processing system 201, the processing system 201 includes a first processor 2011 and a second processor 2012, as depicted on FIG. 3. The first processor may be used for executing the cryptographic operations to be performed by the computing device, whereas the second processor may be used for executing other operations such that any leakage generated by the first processor is jammed by the leakage generated by the second processor. By doing so an attacker performing a side channel analysis attack would capture a global leakage from both processors and would not be able from that global leakage to isolate the leakage from the first processor only which bears information on sensitive operations performed by the computing device.

(15) In order to achieve such a jamming, the second processor may perform operations on dummy data while the first processor performs operations on useful data.

(16) In order to achieve a full protection of the computing device against side channel analysis, the architecture of the computing device shall also prevent leakage about the useful data used as input to the operations performed by the first processor. Such a leakage may for example occur during a transfer of these data on the bus 202 or when loading it from the computer readable memory circuit of the computing device.

(17) In order to do so, the useful data to be used as input to the first processor may be stored in the memories and transferred on the buses of the computing device under an expanded format in which these useful data are interleaved with the dummy data used as input to the second processor. By doing so an attacker performing a side channel analysis on the computing device can only capture from the memories and buses leakages related to such expanded data. He would be incapable from such a leakage to isolate information on the sensitive useful data used as input to the first processor of the computing device.

(18) In order to recover from such expanded data the useful data to be provided to the first processor, the computing device also includes a selection circuit 207 which receives from an input bus 208 such expanded input data, determines the respective positions of useful and dummy data in the expanded data, extracts the dummy input data and useful input data from the expanded input data based on said determined positions and transmits them to the first and second processors.

(19) More precisely, as depicted on FIG. 3, the selection circuit 207 of the computing device executing a first cryptographic operation, such as block cipher operation, of a cryptographic process on useful input data d.sub.1 may be configured: for receiving, from the input bus 208, expanded input data d.sub.1′ obtained by interleaving dummy input data r.sub.1 with said useful input data d.sub.1, for determining positions of the dummy input data r.sub.1 in said expanded input data, for extracting said dummy input data r.sub.1 and said useful input data d.sub.1 from the expanded input data d.sub.1′ based on said determined positions.

(20) The first processor performs an access to the extracted useful input data d.sub.1 and the second processor performs an access to the dummy input data r.sub.1. A transmission of these two data could be performed simultaneously in order to prevent an attacker from obtaining the extracted useful input data d.sub.1.

(21) The first processor is configured for executing said first cryptographic operation of said cryptographic process on said extracted useful input data d.sub.1 to obtain useful output data d.sub.2.

(22) The second processor is configured for executing a second operation on said extracted dummy input data r.sub.1 to obtain dummy output data r.sub.2 and the computing device is configured for having said operations executed such that leakage generated by said first operation is jammed by leakage generated by the second operation.

(23) The dummy input data shall be uncorrelated with said useful input data. The leakage produced by the execution of the second operation may then be seen as noise added to the leakage from the first processor which is the signal of interest to the attacker. Performing the second operation lowers the Signal to Noise Ratio SNR of the global leakage, making it impossible for an attacker to retrieve from the global leakage information on the useful input data d.sub.1 only. In other words, the computing device is configured for having a global leakage depending more on the power signature or electromagnetic emission generated by the dummy input data than one generated by the useful input data. Thus the useful input data cannot be retrieved from the global leakage. The computing device may be configured for having said first cryptographic operation and said second operation executed in parallel in order to have both leakages emitted almost at the same time. Alternatively the second operation may be executed only during one or more parts of the execution of the first cryptographic operation.

(24) Before being stored in memory or provided to the selection circuit of the computing device, expanded input data shall be generated from useful data and dummy data. As shown on FIG. 4, operations that are not sensitive such as F1 on FIG. 4 may be performed on unprotected data d.sub.0. In order to prevent any leakage to an attacker, resulting useful data d.sub.1 shall then be protected by using an expansion operation E generating expanded data d.sub.1′ before performing any sensitive operation such as F2. After such sensitive operations have been performed and data d.sub.2 outputted by such operations may be revealed without risk to an attacker, useful data d.sub.2 may be extracted from expanded data d.sub.2′ by applying an inverse operation E.sup.−1 in order to perform subsequent not-sensitive operations.

(25) In a first embodiment, according to a second aspect of the invention, the computing device is included in a circuit arrangement 500 shown on FIG. 5 also including: an external expansion circuit 501, said input bus 208 configured for connecting said external expansion circuit 501 and the selection circuit 207 of said computing device 101,

(26) The external expansion circuit is configured for interleaving dummy input data r.sub.1 with useful input data d.sub.1 to obtain said expanded input data d.sub.1′ received by the selection circuit from said input bus 208, such that said dummy input data is uncorrelated with said useful input data.

(27) As shown on FIG. 5, the external expansion circuit may be external to the computing device. Alternatively, it may be included in the computing device.

(28) The useful output data d.sub.2 generated by the first processor may not be sensitive data and may be outputted to other components of the circuit arrangement. Alternatively, they may be sensitive data, and shall then also be protected against side channel analysis. The computing device may then include an expansion circuit 209 configured for interleaving said dummy output data r.sub.2 with said useful output data d.sub.2 to obtain expanded output data d′.sub.2 which may be stored in the memories of the computing device, further provided to the selection circuit for performing another operation, or outputted to other components of the circuit arrangement.

(29) In order to remove dummy data from the expanded output data produced by the computing device, the circuit arrangement may also comprise an external selection circuit 502, and an output bus 210 configured for connecting said computing device 101 and said external selection circuit 502, and said external selection circuit may be configured: for accessing, through said output bus, said expanded output data d′.sub.2, for determining positions of the dummy output data r.sub.2 in said expanded output data d′.sub.2, and for extracting said useful output data d.sub.2 from the expanded output data d′.sub.2 based on said determined positions.

(30) The circuit arrangement may then be configured for using said useful output data d.sub.2 in a subsequent operation of the cryptographic process. Alternatively the circuit arrangement may comprise an external memory and may be configured for storing the useful output data d.sub.2 in this external memory as result of the cryptographic process.

(31) Such an external memory may also be used for storing the input data d.sub.1 or the expanded input data d.sub.1′ when generated outside of the computing device, or the useful output data d.sub.2 when outputted directly by the computing device, or the expanded output data d.sub.2′.

(32) In an alternative embodiment, the external selection circuit 502 may be included in the computing device itself.

(33) The computing device may be configured for performing only sensitive operations on expanded data. For example, when the computing device is embedded in a computer 102, the elements of the circuit arrangement not included in the computing device may be part of said computer which may perform all non-sensitive operations.

(34) Alternatively, the computing device may be configured for performing both sensitive and non-sensitive operations. It may then expand data before performing a sensitive operation and then unexpand it when output data are not sensitive data anymore.

(35) Different options may be used in order to manage the position of the dummy data and/or the useful data in the expanded data.

(36) In a first embodiment, the positions of the dummy data in said expanded data are predetermined and are memorized by said computing device for being accessible by said selection circuit of said computing device or by said external selection circuit.

(37) Alternatively, such positions may be transmitted together with the expanded data. In that case, the selection circuit of the computing device and the external selection circuit are configured for receiving said positions from the input bus or the output bus in order to determine the positions of the dummy data in the expanded data. In such a case, said positions may be randomly generated positions.

(38) The useful data, the dummy data, the expanded data may be sequences of bits and in both cases the dummy data may be bit values randomly generated by the expansion circuit of the computing device or the external expansion circuit.

(39) In order to randomly generate positions of dummy data in an expanded data, as depicted on FIG. 6, the expansion circuit of the computing device or the external expansion circuit may use an insertion sequence r and a positions random number R such that for each bit in the positions random number R with a first value, for example 1 on the example of FIG. 6, a bit of said expanded data d′ is selected from the insertion sequence r and for each bit in the positions random number R with a second value, for example 0 on the example of FIG. 6, a bit of said expanded data d′ is selected from the useful data d.

(40) The expansion circuit of the computing device or the external expansion circuit may be configured for generating said insertion sequence r randomly or for using a predetermined insertion sequence r.

(41) The following paragraphs describe the steps of a method for secure execution of a first cryptographic operation of a cryptographic process on useful input data according to a third aspect of the invention as depicted on FIG. 7. These steps are performed by said computing device according to the first aspect of the invention comprising a first processor, a second processor, a selection circuit as descripted above.

(42) In a first step S1, said selection circuit receives, from an input bus, expanded input data d.sub.1′ obtained by interleaving dummy input r.sub.1 data with said useful input data d.sub.1.

(43) In a second step S2, said selection circuit determines the positions of the dummy input data r.sub.1 in said expanded input data d.sub.1′.

(44) In a third step S3, said selection circuit extracts said dummy input data r.sub.1 and said useful input data d.sub.1 from the expanded input data d.sub.1′ based on the determined positions.

(45) In a fourth step S4, said first processor executes said first cryptographic operation of said cryptographic process on said extracted useful input data d.sub.1 to obtain useful output data d.sub.2.

(46) In a fifth step S5, said second processor executes a second operation on said extracted dummy input data r.sub.1 to obtain dummy output data r.sub.2.

(47) Said operations are executed such that leakage generated by said first operation is jammed by leakage generated by the second operation.

(48) In addition to these steps, the method according to the third aspect of the invention may comprise any other step corresponding to the operations, described here before, for which the circuit arrangement or its subcomponents are configured.

(49) Finally, according to a fourth aspect of the invention, the invention relates to a computer program product directly loadable into the memory of at least one computer, comprising software code instructions for performing by a computer's processor the steps of the method according to the third aspect when said product is run on the computer.

(50) As a result, using such a jamming of leakage during sensitive computations and using expanded data, such a computing device enables to protect any sensitive operation against side channel analysis attacks.