Aluminum nitride (AlN) devices with infrared absorption structural layer

Abstract

A micro-electro-mechanical system device is disclosed. The micro-mechanical system device comprises a first silicon substrate comprising: a handle layer comprising a first surface and a second surface, the second surface comprises a cavity; an insulating layer deposited over the second surface of the handle layer; a device layer having a third surface bonded to the insulating layer and a fourth surface; a piezoelectric layer deposited over the fourth surface of the device layer; a metal conductivity layer disposed over the piezoelectric layer; a bond layer disposed over a portion of the metal conductivity layer; and a stand-off formed on the first silicon substrate; wherein the first silicon substrate is bonded to a second silicon substrate, comprising: a metal electrode configured to form an electrical connection between the metal conductivity layer formed on the first silicon substrate and the second silicon substrate.

Claims

1. A method, comprising: depositing an insulation layer over a silicon handle substrate that comprises a first surface and a second surface, wherein the second surface comprises a cavity and the insulation layer is formed on the second surface of the silicon handle substrate; bonding a first surface of a semiconductor layer to the insulation layer; depositing a piezoelectric layer directly on a second surface of the semiconductor layer; depositing a metal conductivity layer over the piezoelectric layer; partially depositing a bond layer over the metal conductivity layer; forming a stand-off on the second surface of the semiconductor layer; and establishing an electrical connection between the metal conductivity layer and a second silicon substrate.

2. The method of claim 1, further comprising depositing a silicon layer or a silicon dioxide layer to form the stand-off.

3. The method of claim 1, further comprising depositing a silicon dioxide layer to form a stand-off positioned on the piezoelectric layer.

4. The method of claim 1, further comprising performing patterning and etching of the piezoelectric layer to form a sidewall.

5. The method of claim 4, further comprising interposing a first dielectric layer between the piezoelectric layer and the metal conductive layer.

6. The method of claim 5, further comprising disposing a second dielectric layer on the sidewall of the piezoelectric layer.

7. The method of claim 6, further comprising exposing the semiconductor layer via a first opening in the silicon handle substrate.

8. The method of claim 7, further comprising exposing the piezoelectric layer through the first opening and a second opening in the semiconductor layer.

9. The method of claim 1, further comprising selectively removing a portion of the semiconductor layer.

10. The method of claim 1, further comprising depositing an infra-red (IR) absorption layer on a selected portion of the semiconductor layer.

11. The method of claim 1, further comprising depositing an infra-red (IR) absorption layer on a selected portion of the piezoelectric layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The numerous aspects, embodiments, objects and advantages of the present disclosure will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

(2) FIG. 1A illustrates a cross-section view of a MEMS structure in accordance with a first embodiment.

(3) FIG. 1B illustrates a cross-section view of a MEMS structure in accordance with a second embodiment.

(4) FIG. 2 illustrates a cross-section view of a MEMS structure in accordance with a third embodiment.

(5) FIG. 3 illustrates a cross-section view of a MEMS structure in accordance with a fourth embodiment.

(6) FIG. 4 illustrates a cross-section view of a MEMS structure in accordance with a fifth embodiment.

(7) FIG. 5 is a flowchart of a process for adding a piezoelectric layer to a MEMS structure.

(8) FIG. 6 illustrates a cross-section view of a MEMS structure in accordance with a sixth embodiment.

(9) FIG. 7 illustrates a cross-section view of a MEMS structure in accordance with a seventh embodiment.

(10) FIG. 8 illustrates a cross-section view of a MEMS structure in accordance with an eighth embodiment.

(11) FIGS. 9A-9K illustrate cross-section views of a MEMS structure in accordance with a ninth embodiment.

(12) FIG. 10 illustrates a cross-section view of a MEMS structure in accordance with a tenth embodiment.

(13) FIG. 11 illustrates a cross-section view of a MEMS structure in accordance with a eleventh embodiment.

(14) FIGS. 12(a)(i), 12(a)(ii), 12(b)(i), and 12(b)(ii) illustrate cross-section views of a MEMS structure in accordance with a twelfth embodiment.

(15) FIGS. 13A-13H illustrate cross-section views of a MEMS structure in accordance with a thirteenth embodiment.

(16) FIGS. 14A-14C illustrate cross-section views of a MEMS structure in accordance with a fourteenth embodiment

DETAILED DESCRIPTION

(17) One or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It may be evident, however, that the various embodiments can be practiced without these specific details, e.g., without applying to any particular networked environment or standard. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the embodiments in additional detail.

(18) The subject disclosure relates to Microelectromechanical System (MEMS) devices, and more particularly, to MEMS devices for Radio Frequency (RF) and low parasitics applications. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the described embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.

(19) In the described embodiments Micro-Electro-Mechanical Systems (MEMS) refers to a class of structures or devices fabricated using semiconductor-like processes and exhibiting mechanical characteristics such as the ability to move or deform. MEMS often, but not always interact with electrical signals. MEMS devices include but are not limited to gyroscopes, accelerometers, magnetometers, pressure sensors, and radio-frequency components. Silicon wafers containing MEMS structures are referred to as MEMS wafers.

(20) In the described embodiments, MEMS device may refer to a semiconductor device implemented as a micro-electro-mechanical system. MEMS structure may refer to any feature that may be part of a larger MEMS device. An engineered silicon-on-insulator (ESOI) wafer may refer to a SOI wafer with cavities beneath the silicon device layer or substrate. Handle wafer typically refers to a thicker substrate used as a carrier for the thinner silicon device substrate in a silicon-on-insulator wafer. Handle substrate and handle wafer can be interchanged.

(21) In the described embodiments, a cavity may refer to an opening or recession in a substrate wafer and enclosure may refer to a fully enclosed space. Bond chamber may be an enclosure in a piece of bonding equipment where the wafer bonding process takes place. The atmosphere in the bond chamber determines the atmosphere sealed in the bonded wafers.

(22) Additionally, a system and method in accordance with the present invention describes a class of RF MEMS devices, sensors, and actuators including but not limited to switches, resonators and tunable capacitors that are hermetically sealed and bonded to integrated circuits that may use capacitive sensing and electrostatic, magnetic, or piezoelectric actuation.

(23) FIG. 1A illustrates a cross-section view of a MEMS structure 100 in accordance with a first embodiment. FIG. 1A shows a MEMS structure with addition of metal on the silicon structural layer. The structure includes a CMOS wafer 102 bonded to a MEMS wafer 104. The MEMS wafer 104 comprises a silicon device layer 106 fusion bonded to a handle wafer 108 through an oxide layer 109. A MEMS aluminum 110 metal layer is added to the silicon device layer 106. Adding a metal layer lowers the resistivity of the MEMS structure over that of just the silicon device layer 106 making it more attractive for applications requiring low parasitics (ex. RF MEMS, Lorentz force sensors, etc.). In this embodiment, the connection between CMOS wafer 102 and MEMS wafer 104 is created through the silicon stand-offs 112 using an aluminum-germanium eutectic bond formed by germanium 111 and aluminum 113. Apart from the stand-offs 112 the bulk of the current is carried by the metal layers 117. In an embodiment, spacers 114 composed of an insulating material such as Silicon Oxide or Silicon Nitride may be placed on bottom metal layer 117 to reduce stiction and control the gap between the top metal layer 110 and the bottom metal layer 117.

(24) FIG. 1B illustrates a cross-section view of a MEMS structure 100 in accordance with a second embodiment. FIG. 1B shows a MEMS structure with additional insulating layer 112a deposited onto the MEMS aluminum 110 and insulating layer 112b deposited onto the bottom electrode 117 to prevent shorting and create a well-defined capacitive gap when the movable MEMS structure consisting of the silicon device layer 106, MEMS aluminum 110, and insulating layer 112a are brought into contact with the electrodes on the CMOS wafer 102.

(25) FIG. 2 illustrates a cross-section view of a MEMS structure 200 in accordance with a third embodiment. FIG. 2 shows a MEMS structure similar to FIG. 1A. However, in this embodiment the electrical connection between the CMOS wafer 102 and the MEMS wafer 104 occurs through physical contact between the CMOS aluminum 204 on the CMOS wafer 102 and the MEMS aluminum 110 on the MEMS wafer 104 connected by an Aluminum-Germanium layer created by the eutectic reaction between germanium 206 and CMOS aluminum 113 on the CMOS wafer 102 and the MEMS aluminum 110 on the MEMS wafer 104. One possible risk of this embodiment is a preferential reaction of the germanium 206 with the MEMS aluminum 110 (since that is the layer it is directly deposited on) with a possibly insufficient reaction with the CMOS aluminum 113. The insufficient reaction may lead to poor bonds and marginal electrical connections.

(26) FIG. 3 illustrates a cross-section view of a MEMS structure 300 in accordance with a fourth embodiment. FIG. 3 shows a MEMS structure identical to FIG. 2 with the exception of a barrier layer 302 deposited between the MEMS aluminum 110 and germanium 206. The barrier layer 302 is electrically conductive and makes an electrical contact with aluminum upon physical contact. The objective of the barrier layer 302 is to prevent a eutectic reaction between the MEMS aluminum 110 and germanium 206, leaving germanium 206 to eutectically react with the CMOS aluminum 113. One such barrier layer may be Titanium Nitride. During the eutectic reaction, the CMOS aluminum 113 will mix with germanium 206 creating an electrical contact and physical bond to the barrier layer 302 on the MEMS aluminum 110, thereby creating an electrical contact between the CMOS wafer 102 and MEMS wafer 104.

(27) FIG. 4 illustrates a cross-section view of a MEMS structure 400 in accordance with a fifth embodiment. FIG. 4 shows a MEMS structure identical to FIG. 3, but with an insulating layer 402 deposited between the MEMS aluminum 110 and silicon device layer 106 thereby electrically insulating the silicon from the metal. The insulating layer 402 is needed in cases where it is not desirable to carry any electrical signal in the silicon layer (for example in RF applications where signal transmission in the silicon would produce a power loss). In this embodiment, at RF frequencies the MEMS aluminum 110 is still capacitively coupled to the silicon device layer 106 through the insulating layer 402. To achieve sufficient isolation the insulating layer must be sufficiently thick to minimize capacitance or the silicon must be sufficiently resistive so as to minimize electrical signal coupling into it.

(28) FIG. 5 is a flowchart of a process for adding metal and piezoelectric layers to a MEMS structure. The process starts with an Engineered SOI 502. A first metal layer (metal 1) is deposited onto the device silicon surface via step 504 followed by the piezoelectric layer deposition (Ex. Aluminum Nitride or PZT) pattern and etch via step 506. Next a second metal layer (Metal 2) deposited onto the wafer to serve as a top electrode for the piezoelectric layer as well as to provide electrical contact between Metal 1 and the CMOS substrate via step 508. A germanium layer is deposited onto Metal 1 and patterned to define germanium pads in regions where bonding to CMOS will take place via step 510. Next, the MEMS wafer is bonded to a CMOS wafer such that germanium pads eutectically react with aluminum pads on the CMOS creating electrical and physical contact between the CMOS aluminum and MEMS Metal 2 via step 512.

(29) FIG. 6 illustrates a cross-section view of a MEMS structure 600 in accordance with a sixth embodiment that utilizes a piezoelectric layer. Adding a piezoelectric layer 602 enables a range of applications including acoustic resonators and filters and piezo-actuated devices. To operate, the piezoelectric layer 602 typically requires a bottom electrode 604 and top electrodes 606. The bottom electrode 604 may comprise a first metal layer (metal 1) (Ex. Aluminium, Ruthenium, Tungsten, Molybdenum or Platinum). In another embodiment, a silicon device layer can be used as a bottom electrode 604. The top electrode 606 and interconnect 610 are composed of a second metal layer (metal 2) (Ex. Aluminum). The top electrode 606 and interconnect 610 make physical and electrical contact to the CMOS aluminum pads 608 using an Aluminum Germanium bond. The bottom electrode 604 may make physical and electrical contact to the interconnect 610 thereby connecting to the CMOS wafer. Electrical potentials may be applied between top electrodes 606 and the bottom electrode 604 or between individual top electrodes 606. These potentials create electric fields to induce strains within the piezoelectric material.

(30) FIG. 7 illustrates a cross-section view of a MEMS structure 700 in accordance with a seventh embodiment. FIG. 7 shows the same structure as in FIG. 6 with an addition of a silicon dioxide layer 702 between the device layer silicon 106 and metal layer, 604. The silicon dioxide layer, 702 serves as a temperature stabilization layer that improves frequency stability of the resonator or filter over temperature by offsetting the positive Young's modulus temperature coefficient of silicon with the negative Young's modulus temperature coefficient of silicon oxide.

(31) FIG. 8 illustrates a cross-section view of a MEMS structure 800 in accordance with a eighth embodiment. FIG. 8 shows the same structure as in FIG. 7 with an addition of a patterned bottom electrode 604. By patterning the bottom electrode 604, multiple potentials may be applied to different sections of the bottom surface of the piezoelectric material 602, leading to more design flexibility and potentially more efficient devices. For resonator applications, for example, the ability to input electrical signals on both the bottom and top of the piezoelectric structure can lead to higher coupling efficiency. In further embodiments, the subject application provides disclosure of a micro-electro-mechanical system (MEMS) integration flow to incorporate aluminum nitride (AlN) on an engineering substrate and a top electrode layer combined with aluminum germanium (AlGe) with complementary metal-oxide-semiconductor (CMOS) wafers/layers/substrates.

(32) In addition to the foregoing, the subject application further describes a MEMS integration flow that comprises starting wafers/layers/substrates (e.g., complementary metal-oxide-semiconductor (CMOS) wafers/layers/substrates, MEMS handle wafers/layers/substrates, and/or MEMS device wafers/layers/substrates) and a plurality of masking layers, for example, ten masking layers, though, as will be appreciated by those of ordinary skill, a fewer or a greater number of masking layers can be utilized without unduly departing from the generality and scope of the subject disclosure.

(33) Typically, the MEMS handle wafers/layers/substrates can be patterned with back-side alignment mark layers used for front-to-back alignment after fusion bonding. Cavities that define suspended MEMS structures can also be etched in a front-side of the MEMS handle wafers/layers/substrates. The MEMS handle layers/wafers/substrates can then be oxidized and fusion-bonded to MEMS device layers/wafers/substrates.

(34) The MEMS device layers/wafers/substrates can, for example, comprise silicon (Si) structural layers that can be ground and polished to target thicknesses, at which point aluminum nitride seed layers can be disposed over a surface of the silicon structural layers, molybdenum layers can be deposited over the aluminum nitride seed layers, aluminum nitride stacking layers can be deposited over the molybdenum layers, and/or silicon dioxide standoff layers can be disposed on the aluminum nitride stacking layers.

(35) The silicon dioxide standoff layers can be etched on the MEMS device layers/wafers/substrates to provide separations between the MEMS structures and the complementary metal-oxide-semiconductor wafers/layers/substrates. The aluminum nitride (AlN) stacking layers can then be patterned through a silicon dioxide hard mask with structures, bottom contacts, and/or aluminum nitride top contact masks. Additionally, aluminum, titanium, and germanium can then be deposited in sequence from bottom to top and patterned with germanium pads and electrodes. The silicon device layer can then be patterned and etched using, for instance an anisotropic etch process used to create deep penetration, steep-sided holes and trenches in layers/wafers/substrates, typically with high aspect ratios, such as deep reactive-ion etching (DRIE), to define release structures. Generally, the combination of the structures and release layers that define the fully released structure are formed on the upper cavity.

(36) A bottom cavity can be etched in the complementary metal-oxide-semiconductor layer/wafer to allow clearance for out-of-plane moving of the MEMS structures (e.g., combinations of silicon and aluminum nitride stacking layers) or damping control. The MEMS and complementary metal-oxide-semiconductor wafers/layers/substrates can then be bonded using aluminum-germanium (AlGe) eutectic bonding to create hermetic seals around the MEMS structures as well as electrical interconnects between the MEMS structures and complementary metal-oxide-semiconductor circuits. Thereafter, the bonded wafer/layer can be thinned on the MEMS side to a desired thickness and a port can be formed on the polished side of the MEMS wafer/layer to create access to the surrounding environment. Silicon tabs on the MEMS wafer/layer can thereafter be removed using, for example, a dicing process to expose the complementary metal-oxide-semiconductor wire-bond pads.

(37) In accordance with the foregoing and with reference to FIG. 9A, a cross-section of a MEMS device 900 is illustrated. The MEMS 900 can comprise a silicon handle substrate 904 that can have been patterned with back-side alignment mark layers to be employed for front-to-back alignment after fusion bonding. Further, a front side of silicon handle substrate 904 can be etched to form cavities 902. As depicted silicon handle substrate 904 can be formed of a silicon substrate into which cavities 902 can have been etched. To the silicon handle substrate 904 inclusive of cavities 902 a silicon dioxide layer 906 can be deposited on the silicon handle substrate 904 thereby overlaying the silicon handle substrate 904 and cavities 902 formed therein. Disposed and/or deposited over silicon dioxide layer 906 and fusion bonded to the silicon dioxide layer 906 can be a layer formed of silicon 908. In accordance with an embodiment, the silicon handle substrate 904 inclusive of formed cavities 902 and silicon dioxide layer 906 can be referred to as an engineered substrate, and for purposes of this disclosure can be referred to as the MEMS handle layer.

(38) With reference to FIG. 9B that depicts a further cross-sectional view of MEMS device 900, in addition to the above noted silicon handle substrate 904 inclusive of etched cavities 902, silicon dioxide layer 906 (silicon substrate 904 inclusive of etched cavities 902 and silicon dioxide layer 906 can be referred to as the MEMS handle layer), and a layer 908 formed of silicon, silicon dioxide standoffs 916 can be formed on the MEMS handle layer by, for example, successively depositing aluminum nitride seed layers 910, molybdenum layers 912, and aluminum nitride stacking layers 914 over silicon layer 908, prior to etching and/or forming silicon dioxide standoffs 916. The additional deposited or disposed layers comprising the aluminum nitride seed layers 910, molybdenum layers 912, aluminum nitride stacking layers 914, and silicon dioxide standoffs 916 over silicon substrate/layer 908 can be referred to as the MEMS device layer or piezoelectric layer.

(39) Silicon layer 908 can be the silicon structural layer of the MEMS device to which the MEMS handle layer (e.g., silicon handle substrate 904 inclusive of etched cavities 902 and silicon dioxide layer 906) can have been fusion bonded to the MEMS device layer (e.g., silicon structural substrate 908, aluminum nitride seed layers 910, molybdenum layers 912, aluminum nitride stacking layers 914, and standoffs 916). It should be noted that the MEMS handle layer, prior to fusion bonding of the MEMS handle layer to the MEMS device layer, can typically have been oxidized and the silicon layer 908 of the MEMS device layer can have been ground and polished to a target or defined thickness prior to deposition of the aluminum nitride seed layers 910, molybdenum layers 912, aluminum nitride stacking layers 914, and standoffs 916 formed of silicon dioxide. Standoffs 916 are typically formed on the MEMS device layer to provide separation between the MEMS structure and a CMOS wafer/layer/substrate.

(40) FIGS. 9C-9E provide illustration of a further cross-sectional view of MEMS device 900 including the layers described above in connection with FIGS. 9A-9B. In FIG. 9C, structure can be defined and separate bottom electrodes 920 can be carved out by first disposing or depositing a silicon dioxide hard mask 918 over the aluminum nitride stacking layers 914 and standoffs 916 and thereafter etching through silicon dioxide hard mask 918 to define the structure and carve out separate bottom electrodes 920. As will be observed, the etching process etches through layers/substrates respectively formed of silicon dioxide hard mask 918, aluminum nitride 914, molybdenum 912, and aluminum nitride seed layer 910, to the silicon layer 908. In FIG. 9D, a bottom electrodes contact 922 can be created. In FIG. 9E a opening etch on silicon dioxide layer 918 can be performed to define aluminum nitride top contacts 924 and avoids unnecessary HBAR resonance from the pad. Defining the structure and carving out the bottom electrodes 920, creating bottom electrode contacts 922, and defining aluminum nitride top contacts 924, as depicted in FIGS. 9C-9E, can be undertaken by patterning the aluminum nitride stacking layers through silicon dioxide hard mark 918.

(41) As illustrated in FIG. 9F aluminum and titanium layers 926 are deposited for the purposes of top electrode material deposition and then germanium layers 928 are deposited over the aluminum and titanium layers 926 so that germanium pads 928 and electrodes 930 can be patterned as depicted in FIGS. 9G-H. The device layer can be overlaid with a layer of photo-resist 932 and patterned and etched using deep reactive-ion etching (DRIE) to define release structures, as depicted in FIG. 91. Only the combination of the structure and release layer can define the fully released structure 934 (See FIG. 9J) in the cavity 902.

(42) As depicted in FIG. 9J, a cavity 938 is etched into a CMOS wafer 936 to allow clearance for out-of-plane moving MEMS structures 934 and/or damping control, and thereafter the CMOS wafer 936 and MEMS device wafer 940 are bonded using an Aluminum-Germanium eutectic bond to create a hermetic seal around MEMS structure 934 and CMOS circuits and form a bonded wafer 942. The eutectically bonded wafer 942 can then be thinned, for instance, on the MEMS wafer side, to a defined or desired thickness and a port 944 can be formed on a polished side of the MEMS wafer 942 to create access to the surrounding environment, as illustrated in FIG. 9K. Additionally, silicon tabs on the MEMS wafer 942 can be removed using a dicing process to expose CMOS wire bond pads.

(43) In accordance with the foregoing and in an additional embodiment as illustrated in FIG. 10, subsequent to defining structure and carving out separate bottom electrodes 920, as illustrated in FIG. 9C, but prior to creating bottom electrode contacts 922, as depicted in FIG. 9D, a partial silicon etch can be performed wherein silicon layer 908 (e.g., the structural silicon layer of the MEMS device wafer) can partially be further etched 1002. The partial etch 1002 can be performed to partially thin down the silicon device layer (e.g., silicon layer 908). The partial etch 1002 can be accomplished with a structure layer mask through silicon etch or silicon deep reactive-ion etching. It should be noted that the partial etch 1002 can be an additional etch to that previously performed to define structure and carve out separate bottom electrodes 920 as elucidated above in connection with FIG. 9C. Additionally and/or alternatively, partial etch 1002 and the etch performed to define structure and carve out separate bottom electrodes 920, as depicted in FIG. 9C, can be accomplished in a single act without unduly and/or unnecessarily departing from the intent and generality of the subject disclosure.

(44) In a further additional aspect or embodiment, as illustrated in FIG. 11, an additional act of can be performed subsequent to etching port 944 on a polished side of the MEMS wafer 942 (see e.g., FIG. 9K). In accordance with this aspect, an infra-red (IR) absorption layer 1102 can be deposited on the back of the MEMS handle wafer 940. The infra-red (IR) absorption layer 1102, as illustrated, can be disposed not only on the back of the MEMS handle wafer 940 but also in the previously etched port 944.

(45) In accordance with a further disclosed aspect or embodiment, as illustrated in FIG. 12 additional and/or alternative standoff 916 formations techniques can be employed. As illustrated in FIG. 12(a)(i) a layer of silicon 908 can be deposited over the MEMS handle layer (e.g., silicon handle substrate 904 inclusive of cavities 902 and silicon dioxide layer 906) and thereafter the deposited layer of silicon 908 can be partially etched to form standoffs 916, thus, referring back to FIG. 9A and as illustrated in FIG. 12(a)(i), standoffs 916 can have been formed from the structural silicon layer 908 of the MEMS device. Alternatively, as depicted in FIG. 12(a)(ii) rather than partially etching into structural silicon layer 908, structural silicon layer 908 can be overlaid with a silicon dioxide layer and thereafter the deposited silicon dioxide layer can be patterned to create or form standoffs 916, as illustrated in FIG. 12(a)(ii).

(46) Thereafter, and still with reference to FIG. 12, deposition of piezoelectric stacking layers 1202, as described and illustrated in connection with FIGS. 9C-9K, can be carried out as respectively depicted in FIGS. 12(b)(i) and 12(b)(ii). In the context of FIG. 12(b)(i) it will be observed that the subsequent piezoelectric stacking layers 1202, as described in relation to FIGS. 9C-9K, overlay silicon standoffs 916, whereas, in connection with FIG. 12(b)(ii), the successive layers that comprise the piezoelectric stacking layers 1202, as disclosed with respect to FIGS. 9C-9K, are deposited over silicon dioxide standoffs 916.

(47) FIG. 13 illustrates an additional and/or alternative process flow than that described and disclosed in connection with FIGS. 9A-9K. In this instance, and as depicted in FIG. 13(a), and as has been described above in relation to FIG. 12(a)(i), silicon standoffs 916 can have been formed by patterning and/or partially etching structural silicon layer 908. Thereafter, the piezoelectric layer stacking (e.g., aluminum nitride seed layers 910, molybdenum layer 912, and aluminum nitride stacking layer 914) described earlier with respect to FIG. 9B can be reduced to only an aluminum nitride layer 1302, wherein an aluminum nitride layer 1302 is overlaid and patterned 1304 on top of the structural silicon layer 908 inclusive of the formed silicon standoffs 916. As illustrated in FIGS. 13B-13H, the structural silicon layer 908 inclusive of the silicon standoffs 916 can be used as bottom electrodes. In FIG. 13C the aluminum nitride layer 1302 can be overlaid with aluminum and titanium layers 1306. As will be noted in relation to FIG. 13C, patterning in aluminum nitride layer 1302 at 1304 will be filled by the aluminum and titanium layers 1306.

(48) In FIG. 13D germanium pads 1308 can be defined, wherein a germanium layer can be overlaid aluminum and titanium layers 1306 to form the germanium pads 1308. Further, in FIG. 13E the previously deposited aluminum and titanium layers 1306 can be selectively patterned to define aluminum and titanium pads 1310 and to expose the underlying aluminum nitride layer 1302. In FIG. 13F a silicon dioxide hard mask 1312 can be deposited over defined germanium pads 1308, aluminum and titanium pads 1310, and exposed aluminum nitride layer 1302 and an etch or patterning performed to define the structure 1314.

(49) Once structure 1314 has been defined, a CMOS wafer 936 can be eutectically bonded to the MEMS device wafer 1316, in a manner similar to that described in the context of FIG. 9J and illustrated in FIG. 13G. Further, on completion of the eutectic bonding of the CMOS wafer 936 to the MEMS device wafer 1316, a port 1318 can be formed on a polished side or surface of the MEMS device wafer 1316, as illustrated in FIG. 13H.

(50) With reference now to FIGS. 14A-14C, and initially in reference to FIG. 14A, in order to provide protection to sidewalls 1402 during the various etching and/or patterning phases that can be employed to construct the described micro-electrical-mechanical device, in accordance with an embodiment, and as illustrated in FIG. 14B a silicon dioxide layer 1404 can be deposited to overlay the layers previously described in the context of FIG. 9E. It will be observed on examination of FIG. 14B that the silicon dioxide layer 1404 has been disposed to cover the sidewalls 1402 as well as bottom electrodes 920 and the bottom electrodes contact 922. Additionally, as will also have been observed on inspection of FIG. 14B, the deposited silicon dioxide layer 1404 will also have covered the aluminum nitride top contact 924. The deposition and patterning of silicon dioxide layer 1404 provides isolation Once the silicon dioxide layer 1404 has been deposited as illustrated in FIG. 14B, the silicon dioxide layer 1404 can undergo a blank reactive-ion etch to create sidewall protection 1406.

(51) In accordance with the foregoing, the subject application discloses in one or more various embodiments and aspects a MEMS device, comprising: a first silicon substrate comprising: a handle layer comprising a first surface and a second surface, the second surface comprises a cavity; an insulating layer deposited over the second surface of the handle layer; a device layer having a third surface bonded to the insulating layer and a fourth surface; a piezoelectric layer deposited over the fourth surface of the device layer; a metal conductivity layer disposed over the piezoelectric layer; a bond layer disposed over a portion of the metal conductivity layer; and a stand-off formed on the first silicon substrate; wherein the first silicon substrate is bonded to a second silicon substrate, comprising: a metal electrode configured to form an electrical connection between the metal conductivity layer formed on the first silicon substrate and the second silicon substrate.

(52) In accordance with the foregoing, the stand-off can be formed on the piezoelectric layer and can be formed as a silicon layer or as a silicon dioxide layer deposited on the device layer. Additionally and/or alternatively, the stand-off can be formed of silicon dioxide deposited on the piezoelectric layer.

(53) Further, the piezoelectric layer can be patterned and etched to form a sidewall in the piezoelectric layer, wherein a first dielectric layer can be interposed between the piezoelectric layer and the metal conductive layer, and a second dielectric layer can be disposed on the sidewall of the piezoelectric layer. In addition, an opening in the handle layer can be exploited to expose the device layer, an orifice in the device layer can be used to expose the piezoelectric layer, and the device layer can include an aperture.

(54) In accordance with a disclosed aspect the device layer can be selectively or partially removed, the piezoelectric layer can in an embodiment comprise aluminum nitride or in another embodiment can comprise: an aluminum nitride (AlN) seed layer, a bottom metal layer, and an aluminum nitride (AlN) layer. Further, an infra-red (IR) absorption layer can be deposited on a portion of the device layer and/or the infra-red (IR) absorption layer can be deposited on a portion of the piezoelectric layer.

(55) In accordance with a further embodiment, a method is described and disclosed. The method can comprise a sequence of machine executable operations that can include depositing an insulation layer over a handle layer that comprises a first surface and a second surface, wherein the second surface comprises a cavity and the insulation layer is formed on the second surface of the handle layer; bonding a first surface of a device layer to the insulation layer; depositing a piezoelectric layer on a second surface of the device layer; depositing a metal conductivity layer over the piezoelectric layer; partially depositing a bond layer over the metal conductivity layer; forming a stand-off on the second surface of the device layer; and establishing an electrical connection between the metal conductivity layer and a silicon substrate.

(56) Further machine executable method operations can include: depositing a silicon layer or a silicon dioxide layer to form the stand-off; depositing a silicon dioxide layer to form a stand-off positioned on the piezoelectric layer; patterning and etching of the piezoelectric layer to form a sidewall; interposing a first dielectric layer between the piezoelectric layer and the metal conductive layer; disposing a second dielectric layer on the sidewall of the piezoelectric layer; exposing the device layer via a first opening in the handle layer; and exposing the piezoelectric layer through the first opening and a second opening in the device layer.

(57) Additional machine executed method acts can also include: selectively removing a portion of the device layer; depositing an infra-red (IR) absorption layer on a selected portion of the device layer; and depositing an infra-red (IR) absorption layer on a selected portion of the piezoelectric layer.

(58) In accordance with further embodiments the disclosure describes a micro-electro-mechanical device that can comprise: a first silicon substrate bonded to a second silicon substrate, comprising: an electrode on the second silicon substrate that electrically contacts a conductivity layer disposed on the first silicon substrate; the conductivity layer on the first silicon substrate is disposed over a piezoelectric layer on the first silicon substrate; the piezoelectric layer on the first silicon substrate is deposited over a device layer that comprises a stand-off formed on the first silicon substrate; and the device layer on the first silicon substrate is bonded to an dielectric layer that is deposited over a surface of a handle layer on the first silicon substrate that comprises a cavity.

(59) As used in this application, the term or is intended to mean an inclusive or rather than an exclusive or. That is, unless specified otherwise, or clear from context, X employs A or B is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then X employs A or B is satisfied under any of the foregoing instances. In addition, the articles a and an as used in this application and the appended claims should generally be construed to mean one or more unless specified otherwise or clear from context to be directed to a singular form. In addition, the word coupled is used herein to mean direct or indirect electrical or mechanical coupling. In addition, the words example and/or exemplary are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as example and/or exemplary is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word exemplary is intended to present concepts in a concrete fashion.

(60) What has been described above includes examples of the subject disclosure. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the subject matter, but it is to be appreciated that many further combinations and permutations of the subject disclosure are possible. Accordingly, the claimed subject matter is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

(61) In particular and in regard to the various functions performed by the above described components, devices, systems and the like, the terms (including a reference to a means) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., a functional equivalent), even though not structurally equivalent to the disclosed structure, which performs the function in the herein illustrated exemplary aspects of the claimed subject matter.

(62) The aforementioned systems have been described with respect to interaction between several components. It can be appreciated that such systems and/or components can include those components or specified sub-components, some of the specified components or sub-components, and/or additional components, and according to various permutations and combinations of the foregoing. Sub-components can also be implemented as components communicatively coupled to other components rather than included within parent components (hierarchical). Additionally, it should be noted that one or more components may be combined into a single component providing aggregate functionality or divided into several separate sub-components, and any one or more middle layers, may be provided to communicatively couple to such sub-components in order to provide integrated functionality. Any components described herein may also interact with one or more other components not specifically described herein.

(63) In addition, while a particular feature of the subject disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms includes, including, has, contains, variants thereof, and other similar words are used in either the detailed description or the claims, these terms are intended to be inclusive in a manner similar to the term comprising as an open transition word without precluding any additional or other elements.