Control circuit for an electronic converter, related integrated circuit, electronic converter and method

Abstract

A control circuit for controlling switching operation of a switching stage of a converter includes a phase detector circuit that generates a pulse-width modulated (PWM) signal in response to a phase comparison of two clock signals. A first clock signal has a frequency determined as a function of a first feedback signal proportional to converter output voltage. A first transconductance amplifier generates a first current indicative of a difference between a reference voltage and the first feedback signal, and a second transconductance amplifier generates a second current indicative of a difference between the reference voltage and a second feedback signal proportional to a derivative of the converter output voltage. A delay line introduces a delay in the first clock signal that is dependent on the first and second currents as well as a compensation current dependent on a selected operational mode of the converter.

Claims

1. A control circuit for a switching stage of an electronic converter configured to provide an output voltage, the control circuit comprising: a first terminal configured to provide a drive signal to an electronic switch of said switching stage; a second terminal configured to receive a first feedback signal proportional to said output voltage; a third terminal configured to receive a second feedback signal proportional to a derivative of said output voltage; a phase detector circuit configured to generate said drive signal in response to a phase difference between a first clock signal and a second clock signal; a first oscillator circuit configured to generate said first clock signal having a frequency that is determined as a function of said first feedback signal; and a first controlled delay line connected between said first oscillator and a first input of said phase detector, said first controlled delay line configured to apply a delay to said first clock signal in response to a combination of said first feedback signal, said second feedback signal and a compensation signal indicative of a requested mode of operation for said electronic converter.

2. The control circuit according to claim 1, wherein said drive signal is pulse-width modulated (PWM).

3. The control circuit according to claim 1, further comprising a second oscillator circuit configured to generate said second clock signal having a frequency that is determined as a function of a reference voltage.

4. The control circuit according to claim 1, further comprising a second oscillator circuit configured to generate said second clock signal having a frequency that is determined as a function of said first feedback signal.

5. The control circuit according to claim 4, further comprising a differential amplifier circuit configured to generate a differential signal in response to a comparison of said first feedback signal to a reference voltage, and wherein a first current output and a second current output of said differential signal are applied to control the frequencies of the first and second oscillator circuits, respectively.

6. The control circuit according to claim 4, further comprising a second controlled delay line connected between said second oscillator and a second input of said phase detector, said second controlled delay line configured to apply a delay to said second clock signal in response to said combination of said first feedback signal, said second feedback signal and the compensation signal.

7. The control circuit according to claim 6, further comprising: a first differential amplifier circuit configured to generate a first differential signal in response to a comparison of said first feedback signal to a reference voltage, and wherein a first output and a second output of said first differential signal are applied to control the delays of the first and second controlled delay lines, respectively.

8. The control circuit according to claim 7, further comprising: a second differential amplifier circuit configured to generate a second differential signal in response to a comparison of said second feedback signal to a reference voltage, and wherein a first output and a second output of said second differential signal are applied to control the delays of the first and second controlled delay lines, respectively.

9. The control circuit according to claim 8, wherein said compensation signal comprises a differential compensation signal and wherein a first output and a second output of said differential compensation signal are applied to control the delays of the first and second controlled delay lines, respectively.

10. The control circuit according to claim 6, further comprising: a second differential amplifier circuit configured to generate a second differential signal in response to a comparison of said second feedback signal to a reference voltage, and wherein a first output and a second output of said second differential signal are applied to control the delays of the first and second controlled delay lines, respectively.

11. The control circuit according to claim 10, wherein said compensation signal comprises a differential compensation signal and wherein a first output and a second output of said differential compensation signal are applied to control the delays of the first and second controlled delay lines, respectively.

12. The control circuit according to claim 1, wherein said driver circuit is configured to selectively operate said switching stage in Continuous-Conduction Mode (CCM) or Discontinuous-Conduction Mode (DCM) as a function of said requested mode of operation.

13. The control circuit according to claim 12, wherein said compensation signal has a first value when said requested mode of operation indicates DCM operation, and has a second value when said requested mode of operation indicates CCM operation, and wherein said second value is greater than said first value.

14. The control circuit according to claim 1, wherein said electronic converter is a buck or boost converter.

15. The control circuit according to claim 1, further comprising said one or more electronic switches of said switching stage.

16. The control circuit according to claim 1, further comprising a feedback circuit configured to generate said first feedback signal.

17. The control circuit according to claim 1, further comprising an analog differentiator configured to generate said second feedback signal from said first feedback signal.

18. An integrated circuit comprising a control circuit according to claim 1.

19. An electronic converter comprising: a switching stage, and a control circuit according to claim 1.

20. A control circuit for a switching stage of an electronic converter configured to provide an output voltage, the control circuit comprising: one or more first terminals configured to provide one or more drive signals, respectively, to one or more electronic switches of said switching stage; a second terminal configured to receive from a feedback circuit a first feedback signal proportional to said output voltage; a third terminal configured to receive from an analog differentiator a second feedback signal proportional to a derivative of said output voltage; a fourth terminal configured to receive a control signal indicative of a requested mode of operation from a processing circuit; a driver circuit configured to generate said one or more drive signals as a function of a Pulse-Width Modulation (PWM) signal, wherein said driver circuit is configured to change mode of operation as a function of said control signal; and a PWM signal generator circuit configured to generate said PWM signal as a function of said first feedback signal, said second feedback signal and a reference voltage, wherein said PWM signal generator circuit comprises: a first oscillator configured to generate a first clock signal; a second oscillator configured to generate a second clock signal; wherein a frequency of at least one of the first and second clock signals is determined as a function of said first feedback signal; a first operational transconductance amplifier configured to generate a first current indicative of a difference between said reference voltage and said first feedback signal; a second operational transconductance amplifier configured to generate a second current indicative of a difference between said reference voltage and said second feedback signal; a current generator configured to generate a compensation current as a function of said control signal; a phase detector providing said PWM signal at an output; one or more first current-controlled delay lines connected between said first oscillator and a first input of said phase detector; and one or more second current-controlled delay lines connected between said second oscillator and a second input of said phase detector; wherein a delay of the first clock signal provided by said one or more first current-controlled delay lines and a delay of the second clock signal provided by said one or more second current-controlled delay lines is controlled by said first current, said second current and said compensation current; and wherein said phase detector generates said PWM signal as a function of a phase difference between the delayed first and second clock signals.

21. The control circuit according to claim 20, wherein said first oscillator is a voltage controlled oscillator configured to generate said first clock signal with a frequency determined as a function of said first feedback signal, and wherein said second oscillator is configured to generate said second clock signal with a frequency determined as a function of a reference voltage.

22. The control circuit according to claim 20, wherein said first oscillator is a current controlled oscillator configured to generate said first clock signal with a frequency determined as a function of a third current, and wherein said second oscillator is a current controlled oscillator configured to generate said second clock signal with a frequency determined as a function of a fourth current, and wherein the control circuit comprises: a third operational transconductance amplifier configured to provide said third current and said fourth current, wherein a difference between said third and fourth currents is proportional to a difference between a reference voltage and said first feedback signal.

23. The control circuit according to claim 20, wherein: said one or more first current-controlled delay lines comprise a first current-controlled delay line having a delay determined as a function of a fifth current; and said one or more second current-controlled delay lines comprise a second current-controlled delay line having a delay determined as a function of a sixth current.

24. The control circuit according to claim 23, wherein said first operational transconductance amplifier is a differential operational transconductance amplifier configured to provide a seventh current and an eighth current, wherein a difference between said seventh and eighth currents is proportional to a difference between a reference voltage and said first feedback signal; wherein said second operational transconductance amplifier is a differential operational transconductance amplifier configured to provide a ninth current and a tenth current, wherein a difference between said ninth and tenth currents is proportional to a difference between said reference voltage and said second feedback signal; and wherein said control circuit further comprises: a first summation node providing said fifth current by adding said seventh current to said ninth current; and a second summation node providing said sixth current by adding said eighth current to said tenth current.

25. The control circuit according to claim 24, wherein said compensation current is subtracted from said first summation node.

26. The control circuit according to claim 24, wherein said compensation current is added to said second summation node.

27. The control circuit according to claim 24, wherein a portion of said compensation current is subtracted from said first summation node, and a portion of said compensation current is added to said second summation node.

28. The control circuit according to claim 20, wherein said driver circuit is configured to selectively operate said switching stage in Continuous-Conduction Mode (CCM) or Discontinuous-Conduction Mode (DCM) as a function of said control signal.

29. The control circuit according to claim 28, wherein said compensation current has a first value when said control signal indicates DCM operation, and has a second value when said control signal indicates CCM operation, and wherein said second value is greater than said first value.

30. The control circuit according to claim 20, wherein said electronic converter is a buck or boost converter.

31. The control circuit according to claim 20, further comprising said one or more electronic switches of said switching stage.

32. The control circuit according to claim 20, further comprising said feedback circuit.

33. The control circuit according to claim 20, further comprising said analog differentiator.

34. The control circuit according to claim 20, further comprising said processing circuit.

35. An integrated circuit comprising a control circuit according to claim 20.

36. An electronic converter comprising: a switching stage, and a control circuit according to claim 20.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The embodiments of the present disclosure will now be described with reference to the annexed plates of drawings, which are provided purely to way of non-limiting example and in which:

(2) The features and advantages of the present invention will become apparent from the following detailed description of practical embodiments thereof, shown by way of non-limiting example in the accompanying drawings, in which:

(3) FIG. 1 shows an example of an electronic converter;

(4) FIG. 2 shows an example of a buck converter;

(5) FIG. 3 shows exemplary waveforms of the buck converter of FIG. 2;

(6) FIG. 4A shows waveforms when the buck converter of FIG. 2 is operated in a CCM mode;

(7) FIG. 4B shows waveforms when the buck converter of FIG. 2 is operated in a DCM mode;

(8) FIG. 5 shows an example of a boost converter;

(9) FIG. 6 shows an example of an electronic converter using a PWM signal;

(10) FIG. 7 shows an example of PWM signal of the electronic converter of FIG. 7;

(11) FIG. 8 shows a first embodiment of a control circuit for the electronic converter of FIG. 6;

(12) FIG. 9 shows exemplary waveforms of the control circuit of FIG. 8;

(13) FIG. 10 shows waveforms when the electronic converter is operated in a CCM mode;

(14) FIG. 11 shows a second embodiment of a control circuit for the electronic converter of FIG. 6;

(15) FIG. 12 shows exemplary waveforms of the control circuit of FIG. 11;

(16) FIG. 13 shows a third embodiment of a control circuit for the electronic converter of FIG. 6; and

(17) FIG. 14 shows a fourth embodiment of a control circuit for the electronic converter of FIG. 6.

DETAILED DESCRIPTION

(18) In the ensuing description, various specific details are illustrated aimed at enabling an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.

(19) Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(20) The references used herein are only provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.

(21) In FIGS. 8 to 14 described below, parts, elements or components that have already been described with reference to FIGS. 1 to 7 are designated by the same references used previously in these figures. The description of these elements has already been made and will not be repeated in what follows in order not to burden the present detailed description.

(22) As explained in the foregoing, various embodiments of the present description relate to an improved time-based control circuit 22a for an electronic converter. For a general description of electronic converters using a PWM signal reference can be made to the previous description of FIGS. 1 to 7.

(23) FIG. 8 schematically shows a time-based control circuit 22a, e.g., in the form of an integrated circuit. Specifically, also in this case, the control circuit 22a comprises: a PWM signal generator 220a configured to generate a PWM signal DRV as a function of a feedback signal FB indicative of the output voltage V.sub.out generated by the switching stage 26 of the electronic converter and a reference voltage V.sub.REF; and a driver circuit 222 configured to drive a switching stage 26 as a function of the PWM signal DRV.

(24) Specifically, in the embodiment considered, the PWM signal generator 220a comprises: a first voltage-controlled oscillator 2220 configured to generate a first clock signal CLK1 as a function of the feedback signal FB; an analog differentiator 2222 configured to generate a signal indicative of (and preferably proportional to) the derivative of the feedback signal FB, e.g., implemented with a capacitor C.sub.D and a resistor R.sub.D connected in series between the feedback signal FB and a reference voltage, e.g., ground (which may correspond, e.g., to the negative input terminal 200b or the negative output terminal 202b), wherein the intermediate node between the capacitor C.sub.D and the resistor R.sub.D corresponds to the signal indicative of the derivative of the feedback signal FB; a first delay line 2224 having a delay as a function of the feedback signal FB and a second delay line 2226 having a delay as a function of the signal indicative of the derivative of the feedback signal FB, wherein the first and second delay lines are connected in cascade and generate a delayed first clock signal CLK1′; a second voltage-controlled oscillator 2228 configured to generate a second clock signal CLK2 as a function of the reference voltage V.sub.REF; and a phase detector circuit 2230 configured to generate the PWM signal DRV, wherein the duty cycle of the PWM signal DRV is determined as a function of the phase difference Φ between the clock signal CLK2 and the delayed clock signal CLK1′.

(25) Delay lines having a programmable delay as a function of a voltage or current signal are well known in the art. For example, in this context may be cited U.S. Pat. Nos. 5,650,739 A or 7,696,799 B2.

(26) For example, as shown in FIG. 9, the phase detector circuit 2230 may be configured to set the signal DRV to high when the second clock signal CLK2 is high and the delayed first clock signal CLK1′ is low. For example, the phase detector 2230 may be implemented with one or more logic gates and/or one or more latches.

(27) In the embodiment considered, the second voltage-controlled oscillator 2228 provides thus a clock signal CLK2 having a given (fixed or settable) frequency as a function of the reference voltage V.sub.REF. Conversely, the first voltage-controlled oscillator 2220 varies the frequency of the first clock signal CLK1 until the feedback signal FB corresponds to the reference voltage V.sub.REF, and in this steady condition the frequency of the first clock signal CLK1 corresponds to the frequency of the second clock signal CLK2, but the clock signals are phase shifted by a given phase Φ.sub.I. The first oscillator 2220 thus implements a regulator with an integral component of the phase Φ.sub.I. Conversely, the first delay line 2224 and the second delay line 2226 introduce an additional phase Φ.sub.P being proportional to the feedback signal FB and an additional phase Φ.sub.D being proportional to the derivative of the feedback signal FB, i.e., the total phase shift Φ corresponds to:
Φ=Φ.sub.I+Φ.sub.P+Φ.sub.D

(28) wherein, as shown in FIG. 9, the phase shift Φ is proportional to (and preferably corresponds to) the switch on duration T.sub.ON (e.g., T.sub.ON=T.sub.SW(Φ/2π)), i.e., the signal DRV is a PWM signal wherein the switch-on duration T.sub.ON/the duty cycle is varied via a time-based control (with PID regulation) of the phase shift Φ as a function of the feedback signal FB and the reference voltage V.sub.REF. Accordingly, the phase detector 2230 may also perform other operations, such as a down-scaling operation of the frequency of the clock signals CLK1/CLK2, and it is only relevant that the phase detector 2230 is configured to generate a PWM signal DRV, wherein the switch-on duration T.sub.ON of the signal DRV is determined as a function of the phase shift Φ.

(29) The inventors have observed that in many applications a large flexibility is requested to the electronic converter. In order to maximize efficiency and performance, it is typically requested to work in different modes (e.g., DCM, CCM, asynchronous mode, synchronous mode, optimized to follow TDMA variations, deterministic/repetitive abruptly load/line variations, etc.) and to maintain very high performance in different scenarios. In such conditions, the design of a DC-DC converter is rather complicate.

(30) As described in the foregoing, a DC-DC converter is usually a closed loop system with a certain loop bandwidth. In this respect, the inventors have observed that a feed-forward action may be used as an additional “out-of-the-loop compensation action”, which may help to compensate specific events or variabilities. These feed-forwards acting out of the main loop, which is by definition “slow” and has limited bandwidth, are designed to be very fast and quickly compensate a specific event, so that the main loop does not have to take care of the input event.

(31) For example, as described in the foregoing, a control circuit 20a may decide to operate the converter in CCM or DCM mode. Accordingly, the control circuit 20a may use a feed-forward action to compensate the transition between these operating modes, such as the switching from CCM to DCM (and vice versa) in a buck or boost DC-DC.

(32) Specifically, in steady-state (e.g., constant input voltage V.sub.in and load 30) the control circuit 20a operates the converter with a duty-cycle given by the operating conditions. If the control circuit 20a is forced to switch from the CCM to DCM mode, the required duty-cycle to maintain regulation will be different.

(33) For example, usually, the converter should be operated in DCM mode when a smaller load 30 is connected to the output terminals 202a, 202b. In fact, as shown in FIG. 10, when the load decreases, the current I.sub.L at the end of the interval T.sub.2 may become negative in the CCM mode. However, when the control circuit is forced to switch in this condition from CCM to DCM (see also FIG. 4B), the negative current will be suppressed, because the switch Q2 will be deactivated at the instant when the current I.sub.L becomes negative. Accordingly, this (missing negative current) results in an excessive charge transferred to the output capacitor Cout, which increases the output voltage V.sub.out. Accordingly, without any feed-forward action, this transition is simply managed by the converter loop (the feedback circuit 24, the PWM signal generator 220a and the driver 222), e.g., by:

(34) 1) the converter is in steady-state in CCM,

(35) 2) DCM operation is forced,

(36) 3) since in DCM during the current I.sub.L is not allowed to become negative in the inductance L (in contrast to CCM), at the output 202a/202b may be transferred a charge in excess which increases the output voltage V.sub.out,

(37) 4) the control loop (negative feedback) detects such deviation and produces a correction action, and

(38) 5) a new steady-state point is reached with a new duty-cycle.

(39) Such new duty-cycle in DCM is different from (and usually smaller than) the previous one in CCM. However, as mentioned before, during such variations of the set-point or operating mode of the converter, overshoots or undershoots of the output voltage V.sub.out may occur, which are usually undesired.

(40) Conversely, with a properly designed specific feed-forward compensation, when the passage from CCM to DCM is forced, a feed-forward compensator may turn on and in open loop it may move the control action to reduce the duty cycle and directly obtain the new one. In such a way, the output voltage V.sub.out does not experience any unwanted transient or such a transient is at least reduced.

(41) FIG. 11 shows a second embodiment of a time-based PWM signal generator 220a.

(42) Specifically, in the embodiment considered, the following modifications have been performed, which also may be used separately: the voltage-controlled oscillators 2220 and/or delay lines 2224 and 2226 have been replaced with current-controlled oscillators and/or delay lines; the delay lines 2224 and 2226 have been combined into the same delay line 2234; a differential approach is used, wherein the oscillators 2220/2228 and/or the delay lines 2234/2235 are driven with differential signal.

(43) Specifically, in the embodiment considered, again a feedback circuit 24 is used to determine a feedback signal FB proportional to the output voltage V.sub.out. For example, in various embodiments, the feedback circuit 24 is implemented with a voltage divider 24 comprising two or more resistors R.sub.FB1 and R.sub.FB2 connected in series between the terminals 202a and 202b, wherein the voltage V.sub.FB at one of the resistors, e.g., resistor R.sub.FB2, corresponds to the feedback signal FB.

(44) In the embodiment considered, the feedback signal FB and the reference voltage V.sub.REF are provided to a first differential transconductor 2236, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2236 provides: a first current i.sub.I+=i.sub.I0+i.sub.I/2; and a second current i.sub.I−=i.sub.I0−i.sub.I/2.

(45) Specifically, in a differential transconductor 2236 the difference i.sub.I=i.sub.I+−I.sub.I− between the currents i.sub.I+ and i.sub.I− is proportional to the difference between the respective input voltages, i.e., the reference voltage V.sub.REF and the feedback voltage V.sub.FB, i.e., i.sub.I=G.sub.MI(V.sub.REF−V.sub.FB).

(46) In the embodiment considered, the current i.sub.I+ is provided to the current-controlled oscillator 2228 and the current i.sub.I− is provided to the current-controlled oscillator 2220, such as two ring-oscillators. Accordingly, the oscillator 2228 generates a clock signal CLK2 having a frequency proportional to the current i.sub.1+ and the oscillator 2220 generates a clock signal CLK1 having a frequency proportional to the current i.sub.I−. Thus, when the feedback voltage V.sub.FB corresponds to the reference voltage V.sub.REF, both oscillators are supplied with the current i.sub.I0, which thus determines the steady state frequency of the clock signals CLK1 and CLK2.

(47) Similarly, the feedback signal FB and the reference voltage V.sub.REF are provided to a second differential transconductor 2238, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2238 provides: a first current i.sub.P+=i.sub.P0+i.sub.P/2; and a second current i.sub.P−=i.sub.P0−i.sub.P/2.

(48) Specifically, in the differential transconductor 2238 the difference i.sub.P=i.sub.P+−i.sub.P− between the currents i.sub.P+ and i.sub.P− is proportional to the difference between the respective input voltages, i.e., the reference voltage V.sub.REF and the feedback voltage V.sub.FB, i.e., i.sub.P=G.sub.MP(V.sub.REF−V.sub.FB).

(49) In the embodiment considered, again an analog differentiator 2222 is used to generate a signal V.sub.D proportional to the derivative of the output voltage V.sub.out. For example, in the embodiment considered, the analog differentiator 2222 is implemented with a capacitor C.sub.D and a resistor R.sub.D connected between the output voltage V.sub.out or the feedback signal FB, and a reference voltage, such as ground or preferably the reference voltage V.sub.REF. For example, when connecting the resistor R.sub.D to the reference voltage V.sub.REF the derivative signal V.sub.D has an offset of V.sub.REF to which the derivative component of the output voltage V.sub.out is added.

(50) In the embodiment considered, the derivative signal V.sub.D, e.g., the voltage at the intermediate node between the capacitor C.sub.D and the resistor R.sub.D, and the reference voltage V.sub.REF are provided to a third differential transconductor 2240, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2240 provides: a first current i.sub.D+=1.sub.D0+i.sub.D/2; and a second current i.sub.D−=i.sub.D0−i.sub.D/2.

(51) Specifically, in the differential transconductor 2240 the difference i.sub.D=i.sub.D+−i.sub.D− between the currents i.sub.D+ and i.sub.D− is proportional to the difference between the respective input voltages, i.e., the reference voltage V.sub.REF and the derivative signal V.sub.D, i.e., i.sub.P=G.sub.MD(V.sub.REF−V.sub.D).

(52) Similar to the description of FIG. 7, the currents i.sub.P+ and i.sub.D+ and/or the currents i.sub.P− and i.sub.D− may be provided to respective delay lines, such as: two delay lines connected in series (essentially corresponding to the delay lines 2224 and 2226) may be configured to generate a delayed version CLK1′ of the clock signal CLK1 as a function of the currents i.sub.P− and i.sub.D−, respectively; and/or two delay lines connected in series may be configured to generate a delayed version CLK2′ of the clock signal CLK2 as a function of the currents i.sub.P+ and i.sub.D+.

(53) Generally, the term “and/or” highlights the possibility that these delay lines may be provided for each clock signal (as shown in FIG. 11 for a differential approach) or only for a single clock signal (as shown in FIG. 8).

(54) Conversely, in the embodiment considered, the currents i.sub.P+ and i.sub.D+ are provided to a first summation node, which thus provides a current I.sub.R=i.sub.P++i.sub.D+, and/or the currents i.sub.P− and i.sub.D− are provided to a second summation node, which thus provides a current I.sub.F=i.sub.P−+i.sub.D−. In the embodiment considered, the current I.sub.R is provided to the delay line 2235 and/or the current I.sub.F is provided to the delay line 2234, such as a sequence of delay stages having a delay as a function of a respective supply current, i.e., the currents I.sub.F and I.sub.R.

(55) Accordingly, in the embodiment considered and as also shown in FIG. 12, the delay stage 2235 generates a delayed clock signal CLK2′ having a delay t.sub.d2 with respect to the clock signal CLK2 and/or the delay stage 2235 generates a delayed clock signal CLK1′ having a delay t.sub.d1 with respect to the clock signal CLK1.

(56) In the embodiment considered, the delayed clock signals CLK2′ and CLK1′ are then provided to a phase detector, which is configured, for example, to: set the signal DRV to a first logic level (e.g., high) at the rising edge of CLK2′; and set the signal DRV to a second logic level (e.g., low) at the rising edge of the signal CLK1′.

(57) Thus, in the embodiment considered, in steady state, the feedback signal V.sub.FB corresponds to the reference voltage V.sub.REF, and by connecting the analog differentiator to the reference voltage V.sub.REF, also the signal V.sub.D corresponds to the reference voltage V.sub.REF. Thus, in the steady state, the differential currents i.sub.D, i.sub.P and i.sub.I are zero, and (when using a differential approach) the delay t.sub.d1 of the delay line 2234 corresponds to the delay t.sub.d2 of the delay line 2235. Moreover, the oscillators 2220 and 2228 provide two clock signals CLK1 and CLK2 having the same frequency and a phase-shift Φ.sub.I. Due to the fact, that the delay lines 2234 and 2235 introduce the same delay t.sub.d1=t.sub.d2 in the embodiment considered, the phase shift Φ between the delayed clock signals CLK1′ and CLK2′ corresponds to Φ.sub.I, e.g., the duration T.sub.ON corresponds to (or is proportional to) the delay Φ.sub.I, e.g., T.sub.ON=T.sub.SW(Φ.sub.I/2π). Accordingly, the duty cycle D=T.sub.ON/T.sub.SW of the signal DRV corresponds thus to Φ.sub.I/2π. For example, in a buck converter, the duty cycle may be determined (approximately) as a function of the input and output voltage, i.e., D=Φ.sub.I/2π=V.sub.out/V.sub.in.

(58) As mentioned before, also only one of the delay lines 2234 or 2235 could be used or one of the delay lines could introduce a constant delay, i.e., one of the delays t.sub.d1 or t.sub.d2 could be zero or at least constant. In fact, in this case, the oscillators 2220 and 2228 would generate clock signals having a phase shift Φ.sub.I which also compensate the constant delay t.sub.d1 or t.sub.d2.

(59) Thus, when analyzing the delays t.sub.d1 or t.sub.d2, it is possible to observe that: when the delay t.sub.d1 increases (and the delay t.sub.d2 remains constant or decreases), the switch-on duration T.sub.ON/duty cycle D immediately increases, and when the delay t.sub.d2 increases (and the delay t.sub.d1 remains constant or decreases), the switch-on duration T.sub.ON/duty cycle D immediately decreases.

(60) The inventors have thus observed that a switching of the duty cycle of the signal DRV (e.g., due to a changing operating condition) may be obtained by changing the delay t.sub.d1 of the delay line 2234 and/or the delay t.sub.d2 of the delay line 2235.

(61) For example, when using current controlled delay lines 2234 and/or 2235, the delays t.sub.d1 and/or t.sub.d2 may be modified by varying the bias currents I.sub.F and/or I.sub.R of the delay lines.

(62) For example, FIG. 13 shows an embodiment, wherein the PWM signal generator circuit 22a comprises a current source 2242 configured to provide a variable current I* (determined as a function of the feed-forward action) which is added to the current provided to the delay line 2235, i.e., I.sub.R=i.sub.P++i.sub.D++I*. However, as mentioned before the current I* could be provided with opposite sign to the delay line 2234, i.e., I.sub.F=i.sub.P−+i.sub.D−−I*, or a given contribution (with opposite signs) may be provided to both delay lines 2234 and 2235, e.g., I.sub.R=i.sub.P++i.sub.D++I*/2 and I.sub.F=i.sub.P−+i.sub.D−−I*/2.

(63) The amount of current I* depends on different factors, starting from the gain K of the current controlled delay lines 2234 and/or 2235, the phenomena/event to compensate and the operation condition of the DC-DC converter.

(64) For example, considering the example of a feed-forward action to compensate the CCM/DCM transition, the feed-forward current I* may be determined as described in the following. For example, assuming a boost converter as described with respect to FIG. 5, wherein the driver circuit 26 is configured to drive the electronic switches S1 and S2 to operate the converter either in CCM or DCM. For example, CCM may be used when the load 30 is high and DCM, when the load is reduced. On-the-fly transitions between such operating modes should be seamless on the output voltage.

(65) For example, as mentioned before, the drive signal DRV.sub.1 may correspond to the PWM signal DRV. Moreover, in CCM, the drive signal DRV.sub.2 may correspond to the complementary version of the PWM signal DRV (possibly with additional dead times). Conversely, in DCM, the drive signal DRV.sub.2 may be set to high when the PWM signal DRV goes to low (possibly with an additional dead time), and the drive signal DRV.sub.2 may be set to low when the signal CS indicates that the current I.sub.L reaches zero/demagnetization of the inductance L.

(66) For example, in order to determine whether to use CCM or DCM, the control circuit 20a may be configured to monitor the output current i.sub.out or the peak or average value of the current I.sub.L, e.g., as a function of the signal CS. For example, assuming that the control circuit 20a is configured to use: CCM when the verification operation indicates that the output current i.sub.out is greater than a given threshold, e.g., 100 mA; and DCM when the verification operation indicates that the output current i.sub.out is smaller than the given threshold, e.g., 100 mA (possibly also using a hysteresis operation).

(67) For example, based on the value of the input voltage V.sub.in and the output voltage V.sub.out and the characteristics of the converter, the PWM signal DRV may have a frequency of 1.5 MHz and: in CCM (at 100 mA) a switch-on duration T.sub.ON of 95 ns; and in DCM (at 100 mA) a switch-on duration T.sub.ON of 65 ns.

(68) Accordingly, when switching from CCM to DCM, the switch-on duration T.sub.ON should be reduced by 30 ns, i.e., the current generator 2242 should provide a current I* which, e.g.: reduces the delay t.sub.d1 by 30 ns, i.e., increases the current I.sub.F; increases the delay t.sub.d2 by 30 ns, i.e., decreases the current I.sub.R; or in general, reduces the delay t.sub.d1 by a time t1, and increases the delay t.sub.d2 by a time t2, with t1+t2=30 ns.

(69) For example, assuming current controlled delay lines 2234 and 2235 having a gain K=100 ns/μA and in steady-state are biased with a current I.sub.F=I.sub.R=i.sub.D0+i.sub.P0 of 4.5 μA, the current I* can be calculated as:
I*=(−30 ns)/(100 ns/μA)=−0.3 μA

(70) In general, the current may thus be applied with a given proportion k, with 0≤k≤1 (e.g., k=0.5) to the delay lines 2234 and 2235, i.e.:
I.sub.R=i.sub.P++i.sub.D+k.Math.I*.
I.sub.F=i.sub.P−+i.sub.D−−(1−k).Math.I*.

(71) Thus, due to the fact that I* is negative, the current I.sub.R will be reduced, thereby increasing the value t.sub.d2, and/or the current I.sub.F will be increased, thereby decreasing the value t.sub.d1. Generally, when switching from DCM to CCM, the current I* has again to be removed.

(72) Accordingly, as shown in FIG. 14, in various embodiments, the control circuit 20a may also comprise a (digital and/or analog) processing circuit 2246 configured to monitor one or more operating parameters of the switching stage 26 and decide whether to activate a given operating mode of the driver circuit 222, such as a DCM or CCM mode. For example, in FIG. 14, the processing circuit 2246 monitors the measurement signal CS. Next, the processing circuit 2246 generates one or more control signal CTRL for the driver circuit 222, e.g., in order to activate the DCM or the CCM mode. Similarly, the processing circuit 2246 provides one or more control signals CTRL (which may also correspond to the previously mentioned control signals for the driver circuit 222) in order to select a given compensation current I*. For example, when only supporting a DCM and a CCM mode, the control circuit 20a may be configured to provide the current I* in the DCM mode and not provide the current I* in the CCM mode, which is schematically shown via an electronic switch 2244 between the current generator 2242 and the delay line 2235, which is closed when the DCM mode is activated and opened when the CCM mode is activated.

(73) The proposed solution permits thus a feed-forward control to overcome specific phenomena/events maintaining high performance. The proposed solution has a negligible impact on power consumption, since it simply involves the generation of a proper current sourced to (or sunk from) the input of the delay line 2234 and/or 2235.

(74) In terms of system complexity and area consumption, there are negligible differences with respect to an implementation without the proposed feed-forward compensation and the advantages overcome such added minor complexity. Eventually, it simply requires a minimal logic to trigger the feed-forward in response to the phenomena to compensate, and a current generator 2242, e.g., implemented with a current mirror, to create the proper feed-forward current I*.

(75) In general, the proposed feed-forward implementation allows more than one feed-forward to work, regardless of the others (i.e., the presence of a specific feed-forward does not preclude/impair the action of another feed-forward), e.g., because a plurality of feed-forward currents I* may be summed.

(76) As mentioned before, in various embodiments, the control circuit 20a may also be integrated in an integrated circuit. In this case, the integrated circuit may comprise: a terminal for connection to a feedback circuit 24, which may also be integrated in the same integrated circuit; a terminal for connection to an analog differentiator 2222, which may also be integrated in the same integrated circuit; one or more terminals for providing respective one or more drive signals to a switching stage 26 of an electronic converter, wherein also the one or more of the switches of the switching stage 26 may be integrated in the integrated circuit; a terminal for receiving at least one control signal CTRL from a control circuit 2246, which may also be integrated in the same integrated circuit; a driver circuit 222 configured to generate the one or more drive signals as a function of a PWM signal DRV, wherein the driver circuit 222 is configured to change mode of operation as a function of the control signal CTRL; and a PWM signal generator circuit 220a configured to generate the PWM signal DRV, wherein the PWM signal generator circuit 220a comprising at least one current-controlled delay line 2234 and/or 2235 (or similarly 2224 or 2226), wherein the respective control current (I.sub.F and/or I.sub.R) is varied (substantially instantaneously) as a function of the control signal CTRL.

(77) Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.

(78) For example, in various embodiments, the delay lines 2234 and 2235 may be implemented with current-controlled delay lines, while the oscillators 2220 and 2228 may be voltage-controlled oscillators as shown in FIG. 8 or current-controlled oscillators as shown in FIG. 11. In fact, in both cases at least the oscillator 2220 has a frequency determined as a function of the feedback signal FB. For example, the oscillator 2228 could also be supplied with the (constant) bias current i.sub.I0 and only the oscillator 2220 could be supplied with the variable current i.sub.I. Alternatively, the oscillator 2220 could also be supplied with the (constant) bias current i.sub.I0 and only the oscillator 2228 could be supplied with the variable current i.sub.I+.

(79) Moreover, when using single ended transconductance amplifiers 2238 and 2240, the respective currents i.sub.P, i.sub.D and the compensation current I* (each having a respective offset bias current) may be provided in any suitable combination to the delay lines 2234 and/or 2235, which may also be implemented with a series of separate delay lines driven by a respective current or combination of currents, e.g.: the current i.sub.P, i.sub.D and I* may be provided to the delay line 2234, such as a first, second and third delay line receiving the currents i.sub.P, i.sub.D and I*, respectively, and the delay line 2235 may be omitted; the current i.sub.P, i.sub.D may be provided to the delay line 2234 and the compensation current I* may be provided to the delay line 2236.

(80) Accordingly, in various embodiments, one or more first delay lines 2234 are connected between the oscillator 2220 and the phase detector 2230 and/or one or more second delay lines 2235 are connected between the oscillator 2228 and the phase detector 2230, wherein the one or more first delay lines 2234 and/or the one or more second delay lines 2235 are driven via the currents i.sub.P, i.sub.D and I*.

(81) The claims form an integral part of the technical teaching of the description provided herein.