TUNABLE FILTER

Abstract

A tunable filter is provided. The tunable filter includes: a filter input; a filter output; at least one feedback loop coupled between the filter output and the filter input, where the at least one feedback loop includes at least one tunable feedback capacitance which is configured to tune a cut-off frequency of the tunable filter; and an active element, coupled between the filter input and the filter output and configured to drive the at least one tunable feedback capacitance, the active element having a transfer function with a primary pole and at least one secondary pole, where the active element includes a first stabilization element that is coupled to a first internal node of the active element.

Claims

1. A closed loop analogue circuit comprising: an input; an output; at least one feedback loop coupled between the output and the input, wherein the at least one feedback loop comprises at least one tunable feedback capacitance; and an operational amplifier, coupled between the input and the output, wherein the operational amplifier comprises a first stabilization element that is coupled to a first internal node of the operational amplifier, and the first stabilization element comprises at least one capacitance, or a combination of at least one capacitance and at least one resistor.

2. The closed loop analogue circuit of claim 1, wherein the first stabilization element is tunable.

3. The closed loop analogue circuit of claim 1, wherein the first stabilization element comprises at least one of the following (a) and (b): (a) a capacitance, coupled between the first internal node and a reference voltage; and (b) a capacitance, coupled between the first internal node and the output.

4. The closed loop analogue circuit of claim 3, wherein the capacitance coupled between the first internal node and the reference voltage is variable.

5. The closed loop analogue circuit of claim 3, wherein the capacitance coupled between the first internal node and the output is fixed or variable.

6. The closed loop analogue circuit of claim 1, wherein the operational amplifier is a differential operational amplifier or a non-differential operational amplifier.

7. The closed loop analogue circuit of claim 1, wherein the operational amplifier comprises: a first current source, coupled between the first internal node and a reference voltage; a first transistor, coupled between a first input terminal of the operational amplifier and the first internal node, a control terminal of the first transistor is coupled to the first input terminal, and a second terminal of the first transistor is coupled to the first internal node.

8. The closed loop analogue circuit of claim 7, wherein the operational amplifier further comprises: a second current source, coupled between a first terminal of the first transistor and a ground terminal.

9. The closed loop analogue circuit of claim 8, wherein the operational amplifier further comprises: a second transistor, coupled between a first output terminal of the operational amplifier and the first internal node, and the output comprises the first output terminal; and a control terminal of the second transistor is coupled to the first internal node.

10. The closed loop analogue circuit of claim 9, wherein the operational amplifier further comprises: a third current source, coupled between a first terminal of the second transistor and the ground terminal; a second terminal of the second transistor is coupled to the reference voltage; and the first terminal of the second transistor is coupled to the first output terminal of the operational amplifier.

11. The closed loop analogue circuit of claim 7, wherein the first internal node comprises a first non-inverse internal node and a first inverse internal node, the first current source comprises a first non-inverse current source and a first inverse current source, the first input terminal comprises a first non-inverse input terminal and a first inverse input terminal, and the first transistor comprises a first non-inverse transistor and a first inverse transistor; the first non-inverse current source is coupled between the first non-inverse internal node and the reference voltage, and the first inverse current source is coupled between the first inverse internal node and the reference voltage; the first non-inverse transistor is coupled between the first non-inverse input terminal and the first non-inverse internal node, a control terminal of the first non-inverse transistor is coupled to the first non-inverse input terminal, and a second terminal of the first non-inverse transistor is coupled to the first non-inverse internal node; and the first inverse transistor is coupled between the first inverse input terminal and the first inverse internal node, a control terminal of the first inverse transistor is coupled to the first inverse input terminal, and a second terminal of the first inverse transistor is coupled to the first inverse internal node.

12. The closed loop analogue circuit of claim 8, wherein the second current source comprises: a second non-inverse current source, coupled between a first terminal of the first non-inverse transistor and a ground terminal; and a second inverse current source, coupled between a first terminal of the first inverse transistor and a ground terminal.

13. The closed loop analogue circuit of claim 9, wherein the second transistor comprises a second non-inverse transistor and a second inverse transistor, the first output terminal comprises a first non-inverse output terminal and a first inverse output terminal; the second inverse transistor is coupled between the first inverse output terminal and the first non-inverse internal node, and a control terminal of the second inverse transistor is coupled to the first non-inverse internal node; and the second non-inverse transistor is coupled between the first non-inverse output terminal and the first inverse internal node, and a control terminal of the second non-inverse transistor is coupled to the first inverse internal node.

14. The closed loop analogue circuit of claim 10, wherein the third current source comprises a third non-inverse current source and a third inverse current source; the third inverse current source is coupled between a first terminal of the second inverse transistor and the ground terminal, a second terminal of the second inverse transistor is coupled to the reference voltage, and the first terminal of the second inverse transistor is coupled to the first inverse output terminal; and the third non-inverse current source is coupled between a first terminal of the second non-inverse transistor and the ground terminal, a second terminal of the second non-inverse transistor is coupled to the reference voltage, and the first terminal of the second non-inverse transistor is coupled to the first non-inverse output terminal.

15. The closed loop analogue circuit of claim 12, further comprising: a capacitance and a resistor are coupled in parallel between the first terminal of the first non-inverse transistor and the first terminal of the first inverse transistor.

16. A tunable filter comprising: a filter input; a filter output; at least one feedback loop coupled between the filter output and the filter input, wherein the at least one feedback loop comprises at least one tunable feedback capacitance; and an operational amplifier, coupled between the filter input and the filter output, wherein the operational amplifier comprises a first stabilization element that is coupled to a first internal node of the operational amplifier, and the first stabilization element comprises at least one capacitance, or a combination of at least one capacitance and at least one resistor.

17. The tunable filter of claim 16, wherein the first stabilization element is tunable.

18. The tunable filter of claim 16, wherein the first stabilization element comprises at least one of the following (a) and (b): (a) a capacitance, coupled between the first internal node and a reference voltage; and (b) a capacitance, coupled between the first internal node and the filter output.

19. The tunable filter of claim 18, wherein the capacitance coupled between the first internal node and the reference voltage is variable.

20. The tunable filter of claim 18, wherein the capacitance coupled between the first internal node and the filter output is fixed or variable.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Examples of the disclosure are described with respect to the following figures, in which:

[0023] FIG. 1 shows a circuit diagram illustrating a MFB low pass filter 100;

[0024] FIG. 2 shows a circuit diagram illustrating the MFB low pass filter 100 together with electrical components of the OPAMP;

[0025] FIG. 3 shows a circuit diagram illustrating the MFB low pass filter 100 including internal capacitances Co;

[0026] FIGS. 4a, 4b show frequency diagrams of the MFB low pass filter 100 illustrating trade-off between gain bandwidth products versus Cmax/Cmin tuning ranges;

[0027] FIGS. 5a-5d show frequency diagrams;

[0028] FIG. 6 shows a circuit diagram illustrating a tunable filter 600 according to a first implementation form;

[0029] FIG. 7 shows a circuit diagram illustrating a tunable filter 700 according to a second implementation form;

[0030] FIG. 8 shows a circuit diagram illustrating a tunable filter 800 according to a third implementation form;

[0031] FIG. 9 shows a performance diagram 900 illustrating a tuning range for a tunable filter according to the disclosure; and

[0032] FIG. 10 shows performance diagrams 1000a, 1000b illustrating OPAMP cross-over frequency and phase margin for a tunable filter according to the disclosure.

DETAILED DESCRIPTION

[0033] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense.

[0034] It is understood that comments made in connection with a described device, circuit or system may also hold true for a corresponding method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

[0035] It is the object of the disclosure to provide an improved tuneable filter design providing large gain at cutoff frequency and wide and stable tuning range.

[0036] A basic idea of the disclosure is to break the limitation on MAX GBW product set by Cmax by moving the primary pole together with the secondary poles during frequency tuning.

[0037] In this way the following holds at CMIN (fo_max): Since p2 is at its highest frequency, location of pole p1 can be moved at higher frequencies (see FIG. 5c). In this condition the maximum possible GBW is achieved (is what is needed to operate at fo_max). At CMAX (fo_min) the following holds: Since p2 is at its lowest frequency, location of pole p1 can be moved at lower frequencies to improve stability (see FIG. 5d). In this condition GBW is reduced (for operation at fo_min, GBW can be reduced with respect to operation at fo_max).

[0038] In order to describe the disclosure in detail, the following terms, abbreviations and notations may be used:

[0039] OPAMP: Operational Amplifier;

[0040] fo_min: minimum cutoff frequency;

[0041] fo_max: maximum cutoff frequency;

[0042] MFB: Multiple Feedback;

[0043] Q: quality factor;

[0044] GBW: gain bandwidth product;

[0045] p1: primary pole or dominant pole;

[0046] p2: secondary pole(s).

[0047] FIG. 6 shows a circuit diagram illustrating a tunable filter 600 according to a first implementation form. The tunable filter 600 includes an active element 601 that may correspond to the OPAMP 101 described above with respect to FIGS. 1 to 3. In contrast to the OPAMP 101, the active element 601 additionally includes one or more stabilization elements CP, CF coupled to the internal node D+, D for providing large gain at cutoff frequency and wide and stable tuning range as described in the following. The one or more stabilization elements may be a first pole capacitance, or a combination of capacitances and resistors.

[0048] The active element 601 includes a non-inverse input VIN+, an inverse input VIN, a non-inverse output VOUT+ and an inverse output VOUT. The tunable filter 600 further includes load capacitances CL coupled to the active element 601 which may correspond to the capacitances C1 and C2 as described above with respect to FIG. 1.

[0049] The active element 601 includes a non-inverse input path between a reference voltage VDD and ground GND including a first (non-inverse) current source MP+, a first (non-inverse) transistor Q1+ and a second current source (non-inverse) Iin+. A control terminal of Q1+ is coupled to the non-inverse input Vin+ of the active element 601. The active element 601 includes an inverse output path between a reference voltage VDD and ground GND including a second (inverse) transistor QF and a third (inverse) current source Iout. A control terminal of QF is coupled to a first (non-inverse) node D+ of the active element 601 which is located between MP+ and Q1+. A first terminal of QF is coupled to the inverse output VOUT of the active element. A second terminal of QF is coupled to the reference voltage VDD. The inverse output VOUT of the active element 601 is coupled to a load having a (variable) load capacitance CL which determines the location of the secondary poles. The load capacitance CL is an equivalent capacitance associated to capacitance C1 and C2 of FIG. 2. The above described components are additionally used in inverse form as described in the following.

[0050] The active element 601 further includes an inverse input path between a reference voltage VDD and ground GND including a first (inverse) current source MP, a first (inverse) transistor Q1and a second (inverse) current source Iin. A control terminal of Q1 is coupled to the inverse input Vinof the active element. The active element 601 includes a non-inverse output path between a reference voltage VDD and ground GND including a second (non-inverse) transistor QF+ and a third (non-inverse) current source Iout+. A control terminal of QF+ is coupled to a first (inverse) node D of the active element 601 which is located between MP and Q1. A first terminal of QF+ is coupled to the first output 121 (VOUT+) of the active element 601. A second terminal of QF+ is coupled to the reference voltage VDD. The non-inverse output VOUT+of the active element is coupled to the load having the (variable) load capacitance CL which determines the location of the secondary poles.

[0051] A capacitance Cs and a resistor Rs are coupled in parallel between the first terminal of Q1+ and the first terminal of Q1. A further cascode circuit may be coupled between the differential part and the non-differential part of the active element 601.

[0052] The first and/or second transistors Q1+, Q1, QF+, QF may be realized as bipolar transistors; in this case the control terminal is a base terminal, the first terminal is an emitter terminal and the second terminal is a collector terminal. Alternatively, the first and/or second transistors Q1+, Q1, QF+, QF may be realized as Field Effect transistors; in this case, the control terminal is a gate terminal, the first terminal is a source terminal and the second terminal is a drain terminal.

[0053] Note that the active element 601 can be realized as a differential active element or alternatively as a non-differential active element. The differential active element is shown in FIG. 6 while a non-differential active element comprises of half the elements as depicted in FIG. 6, i.e. one first current source MP, one first transistor Q1, one second current source Iin, one third current source Iout, one input and one output without the differentiation of non-inverse and inverse components.

[0054] A basic design of the tunable filter 600 can be described using the following words: The tunable filter 600 includes: a filter input VIN+; a filter output VOUT+; at least one feedback loop coupled between the filter output VOUT+ and the filter input VIN+, wherein the at least one feedback loop comprises at least one tunable feedback capacitance C1, C2 which is configured to tune a cut-off frequency fo of the tunable filter; and an active element 601, in particular an operational amplifier (OPAMP), coupled between the filter input and the filter output and configured to drive the at least one tunable feedback capacitance C1, C2, said active element having a transfer function with a primary pole .sub.p1, and at least one secondary pole .sub.p2, wherein the active element 601 comprises a first pole capacitance CP, CF coupled to a first internal node D+ of the active element 601, wherein the first pole capacitance CP, CF is configured to establish a linear relationship between a location of the primary pole .sub.p1 and a location of the at least one secondary pole .sub.p2 of the active element.

[0055] The location of the at least one secondary pole .sub.p2 may change with a tuning of the cut-off frequency fo of the tunable filter; and the first pole capacitance CP, CF may be configured to change the location of the primary pole .sub.p1 in accordance to the change of the at least one secondary pole .sub.p2. The first pole capacitance CP, CF may be configured to move the location of the primary pole .sub.p1 to higher frequencies when the location of the at least one secondary pole .sub.p2 is tuned to higher frequencies. The first pole capacitance CP, CF may be configured to move the location of the primary pole .sub.p1 to lower frequencies when the location of the at least one secondary pole .sub.p2 is tuned to lower frequencies. The first pole capacitance CP, CF may be a function of the at least one feedback capacitance C1, C2.The primary pole may be associated to an internal node total capacitance of the first internal node, the internal node total capacitance being proportional to the at least one feedback capacitance C1, C2. An internal node total capacitance of the first internal node D+ may be proportional to the first pole capacitance, the first pole capacitance being tunable and configured to be tuned of an amount proportional to the change of the at least one feedback capacitance C1, C2. A proportionality constant of the tuning may be a function of the first pole capacitance CF. The active element 601 may include: a first transistor Q1+ coupled between a first input terminal Vin+ and the first internal node D+ of the active element 601; and a second transistor QF coupled between a first output terminal VOUT and the first internal node D+ of the active element 601.

[0056] The first transistor Q1+ may include a first terminal, a second terminal and a control terminal, wherein the control terminal of Q1+ is coupled to the first input terminal VIN+ of the active element 601. The second transistor QF may include a first terminal, a second terminal and a control terminal, wherein the first terminal of QF is coupled to the first output terminal VOUT of the active element. The first internal node D+ may be configured to couple the second terminal of Q1+ to the control terminal of QF. The first pole capacitance CP may be coupled between the first internal node D+ and a reference voltage VDD. The first pole capacitance CP may be variable proportional to a change of a load capacitance CL of a load applied to the tunable filter 600.

[0057] The active element 601 may include: a first current source MP+ coupled between the first internal node D+ and a reference voltage GND; a second current source Iin coupled between the first terminal of Q1+ and a ground terminal GND; and a third current source Iout coupled between the first terminal of QF and a ground terminal GND.

[0058] The active element 601 may be a differential voltage active element, further including: a differential first transistor Q1 coupled between a differential first input terminal VIN and a differential first internal node D of the active element 601; a differential second transistor QF coupled between a differential first output terminal VOUT+ and the differential first internal node D of the active element 601; and a differential first pole capacitance CP, CF corresponding to the first pole capacitance CP, CF, wherein the differential first pole capacitance CP, CF may be coupled to the differential first internal node D of the active element 601.

[0059] The active element 601 may further include a cascode circuit coupled between the second terminal of Q1+ and the second terminal of Q1.

[0060] The above described active element 601 (e.g. OPAMP) may be used in a filter with variable operating frequency fo. The tuning of the frequency fo may be performed by changing its capacitances and this change can be modeled (in its simplest form) as a change in the capacitance CL at the output VOUT. The change of capacitance CL moves locations of secondary poles located at nodes VOUT. The tunable filter 600 according to the disclosure includes the following features: (i) the addition of capacitances CP and/or CF and (ii) a method to vary CP and/or CF of an amount proportional to the change of CL. Different examples can be derived from the tunable filter 600 by applying the following restrictions: (a) CP is variable and CF is fixed, (b) CP is variable and no CF is used, (c) no CP is used and fixed CF is used, (d) no CP is used and variable CF is used.

[0061] The basic principle of the disclosure is described in the following. The input impedance at the base of the voltage follower (the capacitance associated to this node contributes to the capacitance of the primary pole of the OPAMP) can be written as:

[00002]$\mathrm{ZF}\left(s\right)=\frac{1}{s.Math.\left(C_{}+C_F\right)}+\frac{1}{s.Math.C_L}+\frac{1}{s^2.Math.C_L.Math.\left(C_{}+C_F\right).Math.g_m\left(\mathrm{QF}\right)},$

where C.sub. is the base-emitter capacitance of the Bipolar (or alternatively FET) transistor QF and gm(QF) is its transconductance.

[0062] The above equation shows that 1) ZF has a negative real part. This is due to simplification of modeling all feedback loops with a single capacitance CL and is not relevant hereinafter. The input capacitance (that contributes to the capacitance of the primary pole) is a function of CL and CF.

[0063] If capacitance CP is also taken into account, the total capacitance at the node D (i.e. the primary pole capacitance) can be written as:

[00003]$C_D=C_o+C_P+\frac{\left(C_{}+C_F\right).Math.C_L}{C_{}+C_F+C_L}.$

[0064] The above equation can be analyzed in following two cases resulting in the second and third implementation forms as described below with respect to FIGS. 7 and 8.

[0065] FIG. 7 shows a circuit diagram illustrating a tunable filter 700 according to a second implementation form.

[0066] The tunable filter 700 corresponds to the tunable filter 600 described above with respect to FIG. 6; however the active element 701 of the tunable filter 700 does not include the stabilization element CF, instead only the stabilization element CP is implemented.

[0067] This corresponds to the implementation of no CF and low input capacitance voltage follower, i.e.: C.sub.F=0 C.sub.<<C.sub.P. In this case C.sub.D=C.sub.P+C.sub.o and the tracking of the primary pole can be done by varying CP of the same amount as CL.

[0068] FIG. 8 shows a circuit diagram illustrating a tunable filter 800 according to a third implementation form.

[0069] The tunable filter 800 corresponds to the tunable filter 600 described above with respect to FIG. 6; however the active element 801 of the tunable filter 800 does not include the stabilization element CP, instead only the stabilization element CF is implemented.

[0070] This corresponds to the implementation of a fixed value according to C.sub.F and C.sub.P=0. In this case the following relation holds:

[00004]$C_D=C_o+\frac{\left(C_{}+C_F\right).Math.C_L}{C_{}+C_F+C_L}..Math.\mathrm{If}.Math..Math.C_{}+C_F=C_L,\mathrm{then}.Math..Math.C_D=C_o+\frac{C_L}{2}.$

[0071] The above equation shows that the capacitance at the primary pole is proportional to CL, i.e. when CL changes, same change is applied to CD.

[0072] The three implementation forms 600, 700, 800 show the following advantages of the disclosed tunable filter: Since the primary pole is not limited by maximum load capacitance, very large GBW can be achieved when load capacitance is low (i.e. filter is programmed to fo_max). This allows to implement a filter with closed loop approach at fo>700-MHz in an exemplary implementation. At very large fo, G_OPAMP cannot be very high to consider it infinite. The filter shape (i.e. its quality factor) will depend upon G_OPAMP. Since the primary pole is programmable the following relation holds: G_OPAMP(fo_max)=G_OPAMP(fo_min). Since G_OPAMP is more stable across filter tuning range, filter response (i.e. Quality factor of filter) may be more uniform across the tuning range.

[0073] The disclosed tunable filter designs can be used for all filter with very large tuning range or any closed loop systems with very large different loading capacitances.

[0074] FIG. 9 shows a performance diagram 900 illustrating a tuning range for a tunable filter according to the disclosure.

[0075] The tunable filter has been realized with a 4.sup.th order Low Pass Filter (LPF) with a 1 GHz Bandwidth. Performances are shown in FIG. 9. The filter achieves 90-700 MHz 1 dB Bandwidth tuning range. With such large tuning range, the disclosed tunable filter using adaptive stability compensation allows to have 10 GHz Gain*Bandwidth product with 60 degree phase margin and a filter that operates between 90-700 MHz.

[0076] FIG. 10 shows performance diagrams 1000a, 1000b illustrating OPAMP cross-over frequency and phase margin for a tunable filter according to the disclosure.

[0077] BGW 1000a and Phase Margin 1000b of the OPAMP used in the tunable filter according to the disclosure are depicted for the following three cases: (A): Fixed CF, CP=0; (B): Fixed CF and variable CP; (C): fixed CF and CP set at maximum value. The A case yields good results, i.e. the phase margin is kept almost constant across the complete tuning range. The B-case yields the best result in terms of phase margin, i.e. phase margin is improved when operating frequency is reduced. The C-case is reported as a reference and can be useful in case that a maximum phase margin is needed, regardless of the bandwidth achieved.

[0078] According to a first aspect, the disclosure relates to a tunable filter, comprising: a filter input; a filter output; at least one feedback loop coupled between the filter output and the filter input, wherein the at least one feedback loop comprises at least one tunable feedback capacitance which is configured to tune a cut-off frequency of the tunable filter; and an active element, in particular an operational amplifier, coupled between the filter input and the filter output and configured to drive the at least one tunable feedback capacitance, said active element having a transfer function with a primary pole .sub.p1 and at least one secondary pole .sub.p2, wherein the active element comprises a first stabilization element, in particular a first pole capacitance coupled to a first internal node of the active element, wherein the first stabilization element is configured to establish a linear relationship between a location of the primary pole .sub.p1 and a location of the at least one secondary pole .sub.p2 of the active element.

[0079] By establishing a linear relationship between a location of the primary pole .sub.p1 and a location of the at least one secondary pole .sub.p2, the tunable filter provides the advantage of large gain at cutoff frequency and wide and stable tuning range, since the primary pole is not limited by the maximum load capacitance. A large GBW can be achieved when load capacitance is low which allows implementing filter with closed loop approach at high cutoff frequency, e.g. 700 MHz and higher.

[0080] In a first possible implementation form of the tunable filter according to the first aspect, the location of the at least one secondary pole .sub.p2 changes with a tuning of the cut-off frequency (fo) of the tunable filter; and the first stabilization element is configured to change the location of the primary pole .sub.p1 in accordance to the change of the at least one secondary pole .sub.p2.

[0081] This provides the advantage that due to the linear relationship of the location of the primary pole and the secondary poles .sub.p2, the tunable filter provides the advantage of large gain at cutoff frequency and wide and stable tuning range, since the primary (i.e. primary) pole is not limited by the maximum load capacitance.

[0082] In a second possible implementation form of the tunable filter according to the first aspect as such or according to the first implementation form of the first aspect, the first stabilization element is configured to move the location of the primary pole .sub.p1 to higher frequencies when the location of the at least one secondary pole .sub.p2 is tuned to higher frequencies.

[0083] This provides the advantage that due to the linear relationship of the location of the primary pole and the secondary poles .sub.p2, the filter gain is stable across the whole filter tuning range.

[0084] In a third possible implementation form of the tunable filter according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the first stabilization element is configured to move the location of the primary pole .sub.p1 to lower frequencies when the location of the at least one secondary pole .sub.p2 is tuned to lower frequencies.

[0085] This provides the advantage of large GBW when load capacitance is low.

[0086] In a fourth possible implementation form of the tunable filter according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the first stabilization element is a function of the at least one feedback capacitance.

[0087] When the first stabilization element is a function of the at least one feedback capacitance, the filter shows improved stability.

[0088] In a fifth possible implementation form of the tunable filter according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the primary pole is associated to an internal node total capacitance of the first internal node, the internal node total capacitance being proportional to the at least one feedback capacitance.

[0089] Such a proportionality results in improved stability at high tuning ranges.

[0090] In a sixth possible implementation form of the tunable filter according to the third implementation form of the first aspect, an internal node total capacitance of the first internal node is proportional to the first stabilization element, the first stabilization element being tunable and configured to be tuned of an amount proportional to the change of the at least one feedback capacitance.

[0091] When the first stabilization element is tunable and tuned of an amount proportional to the change of the feedback capacitance, optimal performance tuning ranges of the filter can be easily adjusted.

[0092] In a seventh possible implementation form of the tunable filter according to the sixth implementation form of the first aspect, a proportionality constant of the tuning is a function of the first stabilization element.

[0093] This provides the advantage of better stability, as the stability condition depends on a quotient of the location of the second poles and the location of the first pole. A proportionality relaxes the stability condition.

[0094] In an eighth possible implementation form of the tunable filter according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the active element comprises: a first transistor coupled between a first input terminal and the first internal node of the active element; and a second transistor coupled between a first output terminal and the first internal node of the active element.

[0095] In a ninth possible implementation form of the tunable filter according to the eighth implementation form of the first aspect, the first transistor comprises a first terminal, a second terminal and a control terminal, wherein the control terminal of the first transistor is coupled to the first input terminal of the active element, wherein the second transistor comprises a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the first output terminal of the active element; and wherein the first internal node is configured to couple the second terminal of the first transistor to the control terminal of the second transistor.

[0096] This provides the advantage that the filter design can be flexibly implemented, e.g. by two bipolar transistors or by two FET transistors.

[0097] In a tenth possible implementation form of the tunable filter according to the ninth implementation form of the first aspect, the first stabilization element is coupled between the first internal node and a reference voltage.

[0098] This provides the advantage that the first stabilization element can be easily implemented by introducing a capacitive coupling between the first internal node and the reference voltage.

[0099] In an eleventh possible implementation form of the tunable filter according to the ninth implementation form of the first aspect, the first stabilization element is variable proportional to a change of a load capacitance of a load applied to the tunable filter.

[0100] This provides the advantage that due to the proportionality the stability condition holds for large gains and broad tuning ranges.

[0101] In a twelfth possible implementation form of the tunable filter according to any of the eighth to the eleventh implementation forms of the first aspect, the active element comprises: a first current source coupled between the first internal node and a reference voltage; a second current source coupled between the first terminal of the first transistor and a ground terminal; and a third current source coupled between the first terminal of the second transistor and a ground terminal.

[0102] This provides the advantage that these current sources can be flexibly designed, for example by transistors.

[0103] In a thirteenth possible implementation form of the tunable filter according to any of the eighth to the twelfth implementation forms of the first aspect, the active element is a differential voltage active element, further comprising: a differential first transistor coupled between a differential first input terminal and a differential first internal node of the active element; a differential second transistor coupled between a differential first output terminal and the differential first internal node of the active element; and a differential first stabilization element corresponding to the first stabilization element, wherein the differential first stabilization element is coupled to the differential first internal node of the active element.

[0104] This provides the advantage that a differential design is of higher quality and shows improved linearity.

[0105] In a fourteenth possible implementation form of the tunable filter according to the thirteenth implementation form of the first aspect, the active element further comprises: a cascode circuit coupled between the second terminal of the first transistor and the second terminal of the differential first transistor.

[0106] A cascode circuit provides the advantage of decoupling of the inverse and non-inverse parts resulting in improved linearity and stability.

[0107] While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms include, have, with, or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term comprise. Also, the terms exemplary, for example and e.g. are merely meant as an example, rather than the best or optimal. The terms coupled and connected, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

[0108] Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

[0109] Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

[0110] Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the present disclosure has been described with reference to one or more particular examples, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the present disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.