Identification of a phase-to-ground inverter short circuit

Abstract

Arrangements and methods for identifying a phase-to-ground inverter short circuit in an IT (isolé-terre or isolated ground) network are provided. In the method, AC current values of all three phases and DC current values are measured and evaluated at a frequency that is higher than the clock frequency of the inverter. An AC short-circuit current is also identified by subtracting the fundamental wave from the AC current sensor values. An AC component of the DC current sensor value is also identified, and it is identified whether this component is higher than a value predefined for regular operation. The AC short-circuit current and the AC component of the DC current sensor value are also compared. A short circuit is identified for the phase if the two values of the AC short-circuit current and the AC component of the DC current sensor value are approximately equal.

Claims

1. A method for identifying a phase-to-ground inverter short circuit in an isolé-terre (IT) network, the method comprising: measuring and evaluating alternating current (AC) current sensor values of all three phases and direct current (DC) current sensor values at a frequency that is higher than a clock frequency of an inverter; identifying an AC short-circuit current by subtracting a fundamental wave from the AC current sensor values; identifying an AC component of the DC current sensor value and identifying whether the AC component is higher than a value predefined for regular operation; comparing the AC short-circuit current and the AC component of the DC current sensor value; and identifying a short circuit for a phase for which two values of the AC short-circuit current and the AC component of the DC current sensor value are approximately equal.

2. The method of claim 1, further comprising: checking whether the frequency of the AC short-circuit current and the frequency of the AC component of the DC current sensor value are approximately equal.

3. The method of claim 2, wherein the IT network is monitored using an insulation monitor.

4. The method of claim 1, wherein the IT network is monitored using an insulation monitor.

5. The method of claim 1, further comprising: modifying a modulation of the inverter such that the AC short-circuit current is reduced.

6. The method of claim 5, wherein the modifying of the modulation of the inverter comprises actively locking a short-circuited phase to either DC+ potential or DC− potential.

7. The method of claim 6, wherein the modifying of the modulation of the inverter further comprises reducing the clock frequency of the inverter.

8. The method of claim 5, wherein the modifying of the modulation of the inverter comprises reducing the clock frequency of the inverter.

9. An arrangement for identifying a phase-to-ground inverter short circuit in an isolé-terre (IT) network, the arrangement comprising: at least three alternating current (AC) current measurement units for measuring and evaluating AC current sensor values of all three phases; at least one direct current (DC) measurement unit for measuring DC current sensor values at a frequency that is higher than a clock frequency of an inverter; a DC ripple current identification unit for identifying an AC component of the DC current sensor value and identifying whether the AC component is higher than a value predefined for regular operation; an AC ripple current identification unit for identifying an AC short-circuit current by subtracting a fundamental wave from the AC current sensor values; a comparison unit for comparing the AC short-circuit current and the AC component of the DC current sensor value; and a short circuit identification unit for identifying a short circuit for a phase for which two values of the AC short-circuit current and the AC component of the DC current sensor value are approximately equal.

10. The arrangement of claim 9, further comprising: a modification unit for modifying a modulation of the inverter such that the AC short-circuit current is reduced.

11. The arrangement of claim 10, wherein the modifying of the modulation of the inverter comprises actively locking a short-circuited phase to either DC+ potential or DC− potential.

12. The arrangement of claim 11, wherein the modifying of the modulation of the inverter further comprises reducing the clock frequency of the inverter.

13. The arrangement of claim 10, wherein the modifying of the modulation of the inverter comprises reducing the clock frequency of the inverter.

14. The arrangement of claim 9, further comprising: an insulation monitor configured to monitor the IT network.

15. The arrangement of claim 14, wherein the insulation monitor is configured to check whether the frequency of the AC short-circuit current and the frequency of the AC component of the DC current sensor value are approximately equal.

16. A non-transitory computer program product comprising a computer program configured to be loaded directly into a a non-transitory computer readable medium of a processor of an isolé-terre (IT) network, wherein the computer program, when executed by the processor, causes the IT network to: measure and evaluate alternating current (AC) current sensor values of all three phases and direct current (DC) current sensor values at a frequency that is higher than a clock frequency of an inverter; identify an AC short-circuit current by subtracting a fundamental wave from the AC current sensor values; identify an AC component of the DC current sensor value and identify whether the AC component is higher than a value predefined for regular operation; compare the AC short-circuit current and the AC component of the DC current sensor value; and identify a short circuit for a phase for which two values of the AC short-circuit current and the AC component of the DC current sensor value are approximately equal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The disclosure is explained again in more detail below with reference to the appended figures on the basis of exemplary embodiments. In the figures:

(2) FIG. 1 depicts a schematic illustration of an example of a 3-phase 2-level inverter.

(3) FIG. 2 shows a schematic illustration of an example of a vector diagram of a 3-phase 2-level inverter.

(4) FIG. 3 shows a schematic illustration of an example of an inverter in an IT network drivetrain, in which by way of example phase W has a phase-to-ground short circuit.

(5) FIG. 4 depicts an example of an oscillogram of a result of a phase-to-ground short-circuit test in a drivetrain in an IT network.

(6) FIG. 5 depicts a flowchart that illustrates a method for identifying a phase-to-ground short circuit according to one exemplary embodiment.

(7) FIG. 6 depicts a flowchart that illustrates a method for reconfiguring an IT network following a phase-to-ground short circuit according to a first exemplary embodiment.

(8) FIG. 7 depicts a flowchart that illustrates a method for reconfiguring an IT network following a phase-to-ground short circuit according to a second exemplary embodiment.

(9) FIG. 8 depicts a flowchart that illustrates a method for reconfiguring an IT network following a phase-to-ground short circuit according to a third exemplary embodiment.

(10) FIG. 9 depicts a schematic illustration of an example of a vector diagram of an inverter with a reconfiguration in the case of a phase-to-ground short circuit.

(11) FIG. 10 depicts a schematic illustration of an example of an arrangement for identifying a phase-to-ground inverter short circuit.

(12) FIG. 11 depicts a schematic illustration of an example of a reconfiguration arrangement.

DETAILED DESCRIPTION

(13) FIG. 1 shows a schematic illustration of a three-phase system. SUch a three-phase system has a half-bridge HB1, HB2, HB3 for each of the three phases. By virtue of switching the half-bridges HB1, HB2, HB3, the output voltage of the individual phases U, V, W is able to be set both to the positive and to the negative intermediate circuit potential UDC. As may be seen in the circuit, only one switch S.sub.U0, S.sub.U1, S.sub.V0, S.sub.V1, S.sub.W0, S.sub.W1 may ever be closed in each half-bridge, because otherwise the intermediate circuit voltage within the half-bridge is short-circuited. For the further comments, it is assumed that a respective switch S.sub.U0, S.sub.U1, S.sub.V0, S.sub.V1, S.sub.W0, S.sub.W1 is closed in each half-bridge HB1, HB2, HB3. A certain potential is thus present in each phase at each time. Each half-bridge HB1, HB2, HB3 may therefore adopt two states. In the first state, the upper switch S.sub.U1, S.sub.V1, S.sub.W1 is closed, and in the second state, the lower switch S.sub.U0, S.sub.V0, S.sub.W0 is closed.

(14) At the time of the switchover between the switched-on state of the upper half-bridge and the switched-on state of the lower half-bridge, the switch that is currently switched on first of all has to be switched off. There is then a very short wait until the other switch is then switched on. This is what is known as the bridge locking time, during which both switches are switched to “Off” within the half-bridge. This is very short in comparison with the cycle time, specifically of the order of magnitude of approximately 1% of the cycle time.

(15) Each half-bridge HB1, HB2, HB3 may adopt two different switch settings. Because three half-bridges are required for a three-phase current system, this results in 2.sup.3 possible switch settings and thus 8 switching states. At each switch setting, this results in a different voltage constellation at the motor between the phases U, V, W and thus also a different voltage space vector. The two switch settings in which either all three upper switches S.sub.U1, S.sub.V1, S.sub.W1 or all three lower switches S.sub.U0, S.sub.V0, S.sub.W0 are closed constitute an exception. In these switch settings, all three phases are short-circuited. It is thus not possible to measure any voltage, or any voltage as a first approximation, between the phases. These two voltage vectors are referred to as null voltage space vectors.

(16) FIG. 2 shows the schematic illustration of a vector diagram 20 of a 3-phase 2-level inverter. The vector diagram 10 shows the individual voltage space vectors that may be set in the case of a three-phase two-level inverter.

(17) Such a three-phase system (see FIG. 2) may be implemented using three half-bridges HB1, HB2, HB3 connected in parallel.

(18) The individual phases are assigned different vectors. [100] means, for example, that the three phases U, V, W are switched to U+, V− and W−. One revolution corresponds to one full electrical rotation of the electrical machine. A total of 8 base voltage vectors U.sub.0 to U.sub.7 are illustrated. U.sub.0 and U.sub.7 are what are known as null voltage space vectors in the case of which it is not possible to measure any voltage between the phases. There are also 6 active voltage space vectors U.sub.1 to U.sub.6. The table below depicts in each case the chained output voltages from the 8 switch settings that may occur.

(19) TABLE-US-00001 Half- Half- Half- Base voltage bridge 1 bridge 2 bridge 3 space vector SU.sub.1/SU.sub.0 SV.sub.1/SV.sub.0 SW.sub.1/SW.sub.0 U.sub.UV U.sub.VW U.sub.WU U.sub.0 0 0 0 0 V 0 V 0 V U.sub.1 1 0 0 +U.sub.DC 0 V −U.sub.DC U.sub.2 1 1 0 0 V +U.sub.DC −U.sub.DC U.sub.3 0 1 0 −U.sub.DC +U.sub.DC 0 V U.sub.4 0 1 1 −U.sub.DC 0 V +U.sub.DC U.sub.5 0 0 1 0 V −U.sub.DC +U.sub.DC U.sub.6 1 0 1 +U.sub.DC −U.sub.DC 0 V U.sub.7 1 1 1 0 v  0 V 0 V

(20) The basic principle is that of generating a rotating field in the motor: Three individual electromagnetic fields are generated in the motor from the three individual sinusoidal currents, phase-shifted by 120° with respect to one another, of the individual phases. These are overlaid to form a resultant revolving rotating field that generates the torque. The currents are in turn generated by applying voltages to the motor inductance in a targeted manner.

(21) To achieve this, the basic principle of space vector modulation is applied as prior art. If it is desired for example to output a voltage space vector U.sub.a that has exactly half the angle of the voltage space vector U.sub.1 and U.sub.2, this voltage space vector U.sub.a may be created by alternately outputting the voltage space vector U.sub.1 and the voltage space vector U.sub.2. The duration for which each voltage space vector is applied depends on the switching frequency of the modulation. What is decisive for the resultant voltage space vector is just the ratio between the two times for the respective voltage space vectors U.sub.1 and U.sub.2. If the voltage space vector U.sub.a is thus intended to be situated precisely between the two voltage space vectors U1 and U2, then the two times thus have to be selected to be of exactly equal length in order to achieve the desired voltage space vector. The low-pass effect of the stator windings results, in the three-phase current machine, in an averaged current and thus the desired space vector with the desired orientation.

(22) The control logic thus has to initially check in which of the six sectors the desired voltage space vector is located, and alternately output the two relevant base voltage space vectors. The ratio between the times for which each of the two voltage space vectors U.sub.1, U.sub.2 has to be applied results from the relative angle of the desired voltage space vector with respect to the angles of the relevant base voltage space vectors.

(23) If the amplitude of the output voltage, that is to say also the magnitude of the voltage space vector, is intended to be selected as desired, then the null voltage space vectors U.sub.0, U.sub.7 are also required. If it is then desired for example to output the voltage space vector U.sub.b, then the ratio between the output times of the voltage space vectors U.sub.1 and U.sub.2 has to be exactly equal. In order to be able to reduce the magnitude of the resultant voltage space vector U.sub.b, an additional time is introduced in which a null voltage space vector is output. The magnitude of the resultant voltage space vector thus depends on the ratio between the switched-on time of the active voltage space vector and the switched-on time of the null voltage space vector.

(24) To output any desired voltage space vectors, each switching period is divided for example into three time intervals. In two of these time intervals, the two active voltage space vectors are output, and in the third time interval, a passive voltage space vector, that is to say a null voltage space vector U.sub.0, U.sub.7, is output. The three voltage space vectors that are involved are thus pulse width-modulated.

(25) A modulation in which the time interval of the null vector is broken down into two regions within one cycle is particularly commonly selected in the prior art. The vector/time areas therefore do not change, because only the null vector time is divided into two time sections. There are then thus four time voltages per cycle, as it were. FIG. 3 illustrates a schematic illustration of an arrangement 30 of an inverter 31 in an IT network drivetrain. The arrangement includes a battery BA that provides a DC voltage across the two terminals HV1, HV2. The inverter 31 is connected to the DC voltage of the battery BA. The inverter 31 is installed in a housing, which may be made from metal and is grounded. The inverter 31 includes a bridge circuit 33 that has the structure illustrated in FIG. 1. Also forming part of the inverter 31 are two Y-capacitors Y that galvanically isolate the DC voltage side of the inverter 31 with respect to the housing, but capacitively couple it thereto and thus provide voltage symmetry of DC+ and DC− of the IT network with respect to ground. A DC current measurement unit 32, which measures the current strength in the DC current region, is also located on the DC voltage side (on the left in FIG. 3). Three AC current measurement units

(26) 34a, 34b, 34c are located on the output side of the bridge circuit, that is to say to the right of the bridge circuit 33 of the inverter 31. Each of the AC current measurement units 34a, 34b, 34c measures the AC current in one of the phase lines U, V, W of a three-phase current. The three-phase current is forwarded by the inverter 31 to a three-phase current motor M. If a short circuit occurs, for example in the phase W, as illustrated in FIG. 3, then the short-circuit current is channeled from the phase W via ground and via the (e.g., grounded) inverter housing, via the Y-capacitor to the inverter and back to the W-phase.

(27) FIG. 4 shows an oscillogram 40 of a result of a phase-to-ground short-circuit test in a drivetrain in an IT network. The oscillogram shows a measurement result of a phase-to-ground short-circuit test performed on a test bench with a drivetrain inserted into a prototype. The three phase currents I.sub.u, I.sub.v, I.sub.w are each controlled sinusoidally through space vector modulation. The W-phase exhibits a ripple component, that is to say a high-frequency AC current that is overlaid on the slow sinusoid. This short-circuit current flows through the Y-capacitors and the current sensors (see FIG. 3). The DC current sensor is located between a Y-capacitor and the bridge circuit and therefore measures the short-circuit current.

(28) FIG. 5 illustrates a flowchart 500 of a method for identifying a phase-to-ground short circuit according to one exemplary embodiment. In act 5.I, evaluation of current sensor values from three AC current measurement units and from one DC current measurement unit is clocked at a frequency that is higher than the clock frequency of the switches of the inverter of the IT network. In act 5.II, the AC current sensor values I.sub.AC are evaluated by subtracting a fundamental wave I.sub.G from the respective current measured value. A required condition for the occurrence of a phase-to-ground short-circuit current is then that there is still a significant AC component in a phase. This is higher than is caused by normal current ripple I.sub.RMS. The magnitude of the normal current ripple depends on the clock frequency, the DC voltage, and the motor inductance. If it is identified in act 5.II that the measured ripple current is greater than the normal ripple current I.sub.RMS, this being denoted “y” in FIG. 5, then there is a transition to act 5.III. If on the other hand in act 5.II a ripple current is measured that corresponds to the normal ripple current I.sub.RMS in terms of magnitude, this being denoted “n” in FIG. 5, then there is a return to act 5.I, and the monitoring process illustrated in FIG. 5 is performed again at act 5.I or 5.II.

(29) In act 5.III, it is checked further whether the DC current I.sub.DC has an AC component I.sub.AC-DC that is higher than the usual AC component. The usual AC component depends on the DC voltage, the clock frequency, and the magnitude of the controlled AC current at a given motor inductance. If it is identified in act 5.III that the AC component I.sub.AC-DC is greater than a predetermined threshold value SW, this being denoted “y” in FIG. 5, then there is a transition to act 5.IV. If on the other hand in act 5.III an AC component I.sub.AC-DC is measured that does not exceed the predefined threshold value in terms of magnitude, this being denoted “n” in FIG. 5, then there is a return to act 5.I, and the monitoring process illustrated in FIG. 5 is performed again at act 5.I or 5.II.

(30) In act 5.IV, it is identified, as a third required condition, whether the two high ripple currents recorded in act 5.II and act 5.III are of approximately equal magnitude. The evaluation that took place in act 5.II already gives the information as to the phase in which the short circuit occurred, such that the short-circuit current is able to be located accurately. Even more additional acts may be performed in order to make the diagnosis more reliable. If it is identified in act 5.IV that the two ripple currents are of approximately equal value, this being denoted “y” in FIG. 5, then there is a transition to act 5.V. If on the other hand it is identified in act 5.IV that the two ripple currents differ significantly in terms of magnitude, this being denoted “n” in FIG. 5, then there is a return to act 5.I, and the monitoring process illustrated in FIG. 5 is performed again at act 5.I or 5.II.

(31) In act 5.V, in the exemplary embodiment illustrated in FIG. 5, a frequency comparison between the frequencies of the ripple currents recorded in acts 5.II and 5.III is additionally performed. If these are approximately equal, then this also indicates the occurrence of a phase-to-ground short circuit. If the two frequencies were identified as approximately equal, this being denoted “y” in FIG. 5, then there is a transition to act 5.VI. If on the other hand the two frequencies were identified as differing significantly from one another, this being denoted “n” in FIG. 5, then there is a return to act 5.I, and the monitoring process illustrated in FIG. 5 is performed again at act 5.I or 5.II.

(32) In act 5.VI, the reliability of diagnosing the occurrence of a short circuit is increased further by detecting or confirming the short circuit using an insulation monitor external to the inverter. If the insulation monitor indicates an insulation rupture, then this attests to the correctness of the diagnosis in the previous acts. If it was identified in act 5.VI using the insulation monitor that an insulation rupture was present, this being denoted “y” in FIG. 5, then a reconfiguration on the basis of the short-circuit diagnosis that took place is performed in act 5.VII. If on the other hand such a short circuit is not confirmed in act 5.VI, this being denoted “n” in FIG. 5, then there is a return to act 5.I, and the monitoring process illustrated in FIG. 5 is continued at act 5.I or 5.II.

(33) As already discussed, fault diagnosis using insulation monitors unfortunately requires a relatively large amount of time, in some cases several 100 ms.

(34) An additional application for an insulation monitor in connection with identifying a short circuit would therefore be more expedient for a subsequent plausibility check in such a case, in other words in order to be able to possibly return the inverter to the original state in the case of a fault diagnosis to which a response has however already been provided. Act 5.VI would thus take place in such an exemplary embodiment only following a fault diagnosis and a performed reconfiguration, as illustrated in FIG. 6, and would be used to confirm the insulation integrity of the system.

(35) FIG. 6 shows a flowchart 600 that illustrates a method for reconfiguring an IT network following a short circuit recorded using the method shown in FIG. 5. In act 6.I, following detection of the short-circuited phase in accordance with the method explained in FIG. 5, the short-circuited phase is locked to one of the DC voltage potentials DC+ or DC−. This means that the corresponding switch at DC+ or DC− remains permanently switched on, instead of changing its switch setting at the clock frequency. In act 6.II, a region A (see FIG. 9) of the vector diagram is run through. This region corresponds to the space vectors U.sub.4 to U.sub.6 illustrated in FIG. 2 and FIG. 9. In region A, it is possible to switch all of the voltage space vectors required to generate a sinusoidal wave, such that no interference, such as for example harmonics, occurs in the current and torque in this region. In act 6.III, a region B (see FIG. 9) is run through, in which only the space vector U.sub.6 is still able to be driven. There is reduced reproduction accuracy of the sinusoidal current in this region, because the space vector U.sub.1 is unavailable. In act 6.IV, region C is run through (see FIG. 9). It is not possible to generate any space vectors in this region, that is to say that the rotor of the three-phase current motor drifts through this region by virtue of its moment of inertia. In act 6.V, region B (see FIG. 9) is run through again, in which only the space vector U.sub.4 is able to be driven. There is then a return to act 6.II, and region A is run through again.

(36) FIG. 7 shows a flowchart 700 that illustrates a method for reconfiguring an IT network following a short circuit recorded using the method shown in FIG. 5. Unlike the reconfiguration method illustrated in FIG. 6, in the method shown in FIG. 7, the short-circuited phase is not locked to either the DC+ or DC− potential. The clock frequency of the complete space vector modulation is rather reduced in act 7.I. To the same extent as the clock frequency is reduced, the magnitude of the RMS ripple current is also reduced, because the current flows through a capacitive reactance. This means that the ripple current arises due to the switching-induced change in the voltage potential via the capacitances to ground, e.g., the Y-capacitors. An integer reduction in the clock frequency is particularly easy to implement in technical terms. A non-integer reduction or a sliding reduction may however also be implemented. At lower clock frequencies, however, the ripple currents that are normally also present in the case of an intact network increase. The proportion of harmonics and thus motor losses increase. In the case of a greatly reduced clock frequency, although it is possible to obtain the maximum power, this is possibly not able to be maintained for as long as in normal operation. There furthermore continues to be increased loading of components that are not designed for this, and there are also increased losses due to higher control-induced ripple current.

(37) In act 7.II, a region A (see FIG. 9) of the vector diagram is run through. This region corresponds to the space vectors U.sub.4 to U.sub.6 illustrated in FIG. 2 and FIG. 9. In region A, as in the method illustrated in FIG. 6 as well, it is possible to switch all of the voltage space vectors required to generate a sinusoidal wave, such that no interference, such as for example harmonics, occurs in the current and torque in this region. In act 7.III, a region B (see FIG. 9) is run through. Because, in the method shown in FIG. 7, it is possible to switch all of the space vectors, in this case, unlike in the method shown in FIG. 6, there is no reduced reproduction accuracy of the sinusoidal current. In act 7.IV, region C is run through (see FIG. 9). In this region, unlike in the method illustrated in FIG. 6, it is then possible to generate all of the space vectors. This means that the rotor of the three-phase current motor does not drift through this region by virtue of its moment of inertia, but rather runs through it in accordance with a sinusoidal wave generated by the voltage space vectors. In act 7.V, region B (see FIG. 9) is run through again, in which all of the space vectors are likewise able to be driven. There is then a return to act 7.II, and region A is run through again.

(38) FIG. 8 shows a flowchart 800 that illustrates a method for reconfiguring an IT network following a short circuit recorded using the method shown in FIG. 5. The method illustrated in FIG. 8 constitutes a kind of combination of the two method variants illustrated in FIG. 6 and FIG. 7. In the method illustrated in FIG. 8, the short-circuited phase is first of all locked to the DC voltage potential DC+ in act 8.I. This means that the corresponding switch at DC+ remains switched on for a relatively long time, instead of changing its switch setting at the clock frequency. In act 8.II, a region A (see FIG. 9) of the vector diagram is run through. This region corresponds to the space vectors U.sub.4 to U.sub.6 illustrated in FIG. 2 and FIG. 9. In region A, it is possible to switch all of the vectors required to generate a sinusoidal wave such that no interference, (e.g., harmonics), occurs in the current and torque in this region. In act 8.III, a region B (see FIG. 9) is run through in which only the space vector U.sub.6 is still able to be driven. There is reduced reproduction accuracy of the sinusoidal current in this region, because the space vector U.sub.1 is unavailable. In act 8.IV, the switch of the short-circuited phase is set to DC− when region C is driven (see FIG. 9). By virtue of this switchover, it is possible to switch all of the vectors required for a sinusoidal wave in region C as well such that no interference, (e.g., harmonics), occurs in the current and torque in this region. In act 8.V, region B (see FIG. 9) is run through again in which only the space vector U.sub.3 is able to be driven. There is then a return to act 8.I and the short-circuited phase is locked to the DC voltage potential DC+, and then region A is run through again.

(39) FIG. 9 shows a schematic illustration of a vector diagram of an inverter with a reconfiguration in the case of a phase-to-ground short circuit. The vector diagram has different sectors A, B, and C. Sector A has the characteristic that the phase w is in this case at DC+. The two sectors B are transition regions in which the phase w is switched over to DC−. In sector C, the phase w is at DC−.

(40) FIG. 10 schematically illustrates an arrangement 100 for identifying a phase-to-ground inverter short circuit. The arrangement 100 has a DC measurement unit 32 for measuring DC current values I.sub.DC. The DC measurement unit is located on that side of the IT network to which DC current is applied, as shown for example in FIG. 3. The measurement takes place at a frequency f that is higher than the clock frequency f.sub.T of the inverter 31 (see FIG. 3). Three AC current measurement units 34a, 34b, 34c are also part of the arrangement 100 shown in FIG. 10. The AC current measurement units 34a, 34b, 34c, as shown in FIG. 3, are arranged on that side of the IT network 30 to which three-phase current is applied. AC current values I.sub.AC of all three phases U, V, W are measured by the AC current measurement units 34a, 34b, 34c. The arrangement 100 furthermore has a DC ripple current identification unit 101. The DC ripple current identification unit 101 measures an AC component I.sub.AC-DC of the DC current sensor value I.sub.DC. The ripple current identification unit 101 is furthermore used to identify whether this component is higher than a value predefined for regular operation.

(41) An AC ripple current identification unit 102 is also part of the arrangement 100. The AC ripple current identification unit 102 identifies an AC short-circuit current I.sub.KP as a component of the three-phase current. The AC short-circuit current I.sub.KP is identified by subtracting the fundamental wave I.sub.G from the AC current sensor values I.sub.AC. The fundamental wave is the regular sinusoidal wave that is generated by the inverter and that is offset by 120° in the different phases U, V, W. A comparison unit 103, which is connected downstream both of the DC ripple current identification unit 102 and of the AC ripple current identification unit 102, is also part of the arrangement 100. The comparison unit 103 compares a value of the AC short-circuit current I.sub.KP and a value of the AC component I.sub.AC_DC of the DC current I.sub.DC and identifies a comparison result VE. Additionally, the arrangement 100 includes a short circuit identification unit 104. The short circuit identification unit 104 locates a short circuit on the basis of the identified comparison result VE. The short circuit is located in the phase for which the two values of the AC short-circuit current and the AC component of the DC current, that is to say the ripple currents, are approximately equal. “Approximately equal” in this connection is intended to mean that the amplitude of the smaller value of the ripple current reaches at least 50% of the larger value of the ripple current. This is because there are a few stray current paths through which the ripple current flows. The current therefore may never be equal through the two sensors. The arrangement 100 then outputs a modulation command MB to a modification unit 111, as shown in FIG. 11.

(42) FIG. 11 shows a reconfiguration arrangement 110. The reconfiguration arrangement 110 includes the arrangement 100 shown in FIG. 10. The reconfiguration arrangement 110 furthermore includes a modification unit 111. The modification unit 111 serves to modify the modulation behavior of the inverter such that the AC short-circuit current is reduced. To this end, the modification unit 111 receives a corresponding modulation command MB from the arrangement 100. The modification is performed by changing the duty cycle of the pulse width modulation in order to drive the switches of the inverter of the IT network. This modification is explained in detail in connection with FIG. 6 to FIG. 8.

(43) Finally, it is once again pointed out that the described methods and devices are merely exemplary embodiments, and that the disclosure may be varied by a person skilled in the art without departing from the field of the disclosure, insofar as this is specified by the claims. Other variations may be derived herefrom by the person skilled in the art, without departing from the scope of protection of the disclosure. It is therefore intended that the foregoing description be regarded as illustrative rather than limiting, and that it be understood that all equivalents and/or combinations of embodiments are intended to be included in this description.

(44) For the sake of completeness, it is also pointed out that the use of the indefinite article “a” or “an” does not rule out the fact that the feature in question may also be present multiple times. Likewise, the term “unit” does not exclude this including a plurality of components that may possibly also be spatially distributed.

(45) It is to be understood that the elements and features recited in the appended claims may be combined in different ways to produce new claims that likewise fall within the scope of the present disclosure. Thus, whereas the dependent claims appended below depend from only a single independent or dependent claim, it is to be understood that these dependent claims may, alternatively, be made to depend in the alternative from any preceding or following claim, whether independent or dependent, and that such new combinations are to be understood as forming a part of the present specification.