Adaptive CC-CV transition circuit and power management method

Abstract

An adaptive constant current-constant voltage (CC-CV) transition circuit comprises an amplifier, a series-pass device with current sense, a feedback network and a constant current controller to provide a stable and smooth transition between a constant voltage mode and a constant current mode, and vice versa. A voltage regulator loop comprises an amplifier, an optional buffer, a series-pass device with current sense and a feedback network which provides a feedback voltage to the amplifier. A current regulation loop comprises the amplifier, the optional buffer, the series-pass device, the feedback network and a constant current controller comprising a trans-impedence amplifier and a transconductance comparator which generate a current signal to a pseudo-constant bias (PCB) and a voltage signal to the adaptive compensation network (ACN) of the amplifier.

Claims

1. A linear regulator which implements a constant voltage to constant current (CV-CC) transition and a constant current to constant voltage (CC-CV) transition comprises: an amplifier A.sub.0 having a first and second input and an output, said first input connects to feedback voltage (V.sub.FB), said second input connects to reference voltage (V.sub.REF), said amplifier A.sub.0 having a pseudo-constant bias (PCB) which automatically biases and controls the transconductance of amplifier A.sub.0 as a function of an operating mode and connecting with an adaptive compensation network (ACN) which adaptively alters speed and stability for current regulation; a series-pass device responsive to said amplifier A.sub.0 output and to second supply voltage (VDD.sub.2) and having a first output current (I.sub.OUT) output and having a second output current (I.sub.SEN) output, said series-pass device controlling the current from VDD.sub.2 to I.sub.OUT and I.sub.SEN; a feedback network having two inputs which sense voltage differential between output voltage (V.sub.OUT) and ground and generates an output V.sub.FB to amplifier A.sub.0; and a constant current (CC) controller having a trans-impedence amplifier Z.sub.1 and a transconductance device Gm.sub.1 and a first input I.sub.SEN from the series-pass device and a second input I.sub.REF wherein amplifier Z.sub.1 compares I.sub.SEN and I.sub.REF and generates V.sub.SEL as voltage for a signal to ACN for amplifier A.sub.0 and device Gm.sub.1 generates a current control I.sub.SEL to the PCB, wherein a voltage regulation loop to the amplifier A.sub.0 comprises a series-pass device and a feedback network which applies V.sub.FB to said amplifier A.sub.0 and a current regulation loop comprises the series-pass device, the feedback network and the CC controller which applies an a control current (I.sub.SEL) to said PCB and a voltage control (V.sub.SEL) to said ACN.

2. The linear regulator of claim 1 wherein a buffer is interposed between the amplifier A.sub.0 and the series-pass device.

3. The linear regulator circuit of claim 1, further comprising a compensation capacitor C.sub.C disposed in the voltage regulation loop and the current regulation loop.

4. The linear regulator of claim 1, wherein in the constant voltage (CV) mode, V.sub.OUT is regulated, and I.sub.SEN is monitored by amplifier Z.sub.1.

5. The linear regulator of claim 1, further comprising a compensation capacitor C.sub.C disposed in the constant voltage (CV) feedback loop and the CC feedback loop and wherein when the regulator is in a CV mode, the compensation capacitor C.sub.C is reduced by ACN to preserve stability and in CC mode, the CC feedback loop dominates and the compensation capacitor C.sub.C is magnified by ACN for frequency compensation.

6. The linear regulator of claim 1 wherein in the CC mode, I.sub.OUT is regulated and V.sub.FB is monitored by PCB and when V.sub.FB ramps up and approaches V.sub.REF, the regulator is triggered to implement a CC to CV mode transition.

7. The linear regulator of claim 1 wherein V.sub.OUT is regulated to be approximately $V_{\mathrm{OUT}}=\left\{\frac{{\mathrm{Gm}}_0{R}_0{\mathrm{Gm}}_{\mathrm{pass}}{R}_{\mathrm{OUT}}}{1+{\mathrm{Gm}}_0{R}_0{\mathrm{Gm}}_{\mathrm{pass}}{R}_{\mathrm{OUT}}}\right)V_{\mathrm{REF}}$ where Gm.sub.0 and R.sub.0 are the transconductance and output impedance of A.sub.0 respectively, Gm.sub.pass is the transconductance of series-pass device, R.sub.OUT is impedance of output load and is the scaling factor of feedback network.

8. The linear regulator of claim 1 wherein I.sub.OUT is regulated to be approximately $I_{\mathrm{OUT}}=\left\{\frac{Z_1{\mathrm{Gm}}_1{R}_0{\mathrm{Gm}}_{\mathrm{pass}}{R}_{\mathrm{OUT}}}{1+M{Z}_1{\mathrm{Gm}}_1{R}_0{\mathrm{Gm}}_{\mathrm{pass}}{R}_{\mathrm{OUT}}}\right)I_{\mathrm{REF}}$ where Z.sub.1 and Gm.sub.1 is the trans-impedance gain and the transconductance gain of CC controller respectively, R.sub.0 is output impedance of A.sub.0, Gm.sub.pass is transconductance of series-pass device and M is the scaling ratio I.sub.OUT to I.sub.SEN.

9. A linear regulator which implements a constant voltage to constant current (CV-CC) transition and a constant current to constant voltage (CC-CV) transition comprises: an amplifier A.sub.0 having a first and second input and an output, said first input connects to feedback voltage (V.sub.FB), said second input connects to reference voltage (V.sub.REF), said amplifier A.sub.0 having a pseudo-constant bias (PCB) which automatically biases and controls transconductance of amplifier A.sub.0 as function of operating mode and having an adaptive compensation network (ACN) which adaptively alters speed and stability for current regulation; a buffer connected to the amplifier A.sub.0 output and having a buffer output; a series-pass device connected to said buffer output and to second supply voltage (VDD.sub.2) and having a first output current (I.sub.OUT) output and having a second output current (I.sub.SEN) output, said series-pass device controlling the current from VDD.sub.2 to I.sub.OUT and I.sub.SEN; a feedback network having two inputs which senses voltage differential between output voltage (V.sub.OUT) and ground and generates an output V.sub.FB to amplifier A.sub.0; and a constant current (CC) controller having a trans-impedence amplifier Z.sub.1 and a transconductance device Gm.sub.1 and a first input I.sub.SEN from the series-pass device and a second input I.sub.REF wherein the amplifier Z.sub.1 compares I.sub.SEN and reference current (I.sub.REF) and generates voltage control (V.sub.SEL) as voltage for the signal to ACN for amplifier A.sub.0 and device Gm.sub.1 generates a current control (I.sub.SEL) to the PCB.

10. The linear regulator circuit of claim 9, wherein the series-pass device has a current sensor.

11. The linear regulator of claim 10, wherein in the constant voltage (CV) mode V.sub.OUT is regulated and I.sub.SEN is monitored by amplifier Z.sub.1.

12. The linear regulator of claim 10, wherein when I.sub.SEN is larger than I.sub.REF, the regulator undergoes a CV to CC mode transition.

13. The linear regulator circuit of claim 9, wherein the series-pass device comprises a component selected from the group consisting of a p-channel MOSFET, an n-channel MOSFET and a bipolar junction transistor.

14. The linear regulator circuit of claim 9, wherein a constant voltage (CV) feedback loop to amplifier A.sub.0 operates in a constant voltage (CV) mode and a CC feedback loop to amplifier A.sub.0 operates in a CC mode.

15. The linear regulator circuit of claim 14, further comprising a compensation capacitor C.sub.C disposed in the CV feedback loop and the CC feedback loop and wherein when the regulator is in a CV mode, the compensation capacitor C.sub.C is reduced by ACN to preserve stability and in CC mode, the CC feedback loop dominates and the compensation capacitor C.sub.C is magnified by ACN for frequency compensation.

16. A power management method for managing constant voltage to constant current (CV-CC) and constant current to constant voltage (CC-CV) transition modes in a circuit comprising: controlling a constant voltage (CV) mode of operation by a first bias to an amplifier to control transconductance Gm.sub.0 in the amplifier so that the amplifier has a gain of Gm.sub.0*R.sub.0 to amplify the difference between feedback voltage (V.sub.FB) and reference voltage (V.sub.REF) wherein a CV feedback loop keeps an output voltage (V.sub.OUT) to a desired level; and controlling a constant current (CC) mode of operation by a second bias to the amplifier so that for a second transconductance Gm.sub.1 the amplifier provides a gain Gm.sub.1*R.sub.0 to amplify the difference between second output current (I.sub.SEN) and reference current (I.sub.REF) wherein a CC feedback loop provides output current (I.sub.OUT) at a desired level.

17. The power management method of claim 16 further comprising operating the amplifier in a high gain region in CV and CC modes.

18. The power management method of claim 16 further comprising activating a compensation network to the band width for the CC mode and disabling the compensation network in the CV mode.

19. The power management method of claim 16 further comprising in the CV mode regulating the output voltage (V.sub.OUT) and amplifying the second output current I.sub.SEN by an amplifier Z.sub.1 such that when I.sub.SEN>I.sub.REF, the CV mode transitions to a CC mode.

20. The power management method of claim 16 wherein in the CC mode, the regulating the first output current (I.sub.OUT) and monitoring the V.sub.FB so that when V.sub.FB ramps up and approaches V.sub.REF, the CC mode transitions to the CV mode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic circuit diagram of a linear regulator;

(2) FIG. 2 is a graphical representation of the operating mode for the linear regulator of FIG. 1;

(3) FIG. 3 is a schematic diagram of a voltage regulator loop for the linear regulator of FIG. 1;

(4) FIG. 4 is a schematic diagram of a current regulation loop for the linear regulator of FIG. 1;

(5) FIG. 5 is a schematic circuit diagram of a transistor-level implementation for a linear regulator; and

(6) FIG. 6 is a graphical representation of a simulator with an output voltage of 3V and an over current protection of 100 mA for the linear regulator of FIG. 5.

DETAILED DESCRIPTION

(7) The proposed architecture is demonstrated by a linear regulator 10 as shown in FIG. 1. It illustrates a generalized case wherein the architecture can be supplied by a single supply, where VDD.sub.1 equals to VDD.sub.2, or two different supply voltages, VDD.sub.1 and VDD.sub.2, depending on the system requirement. V.sub.OUT is the regulated output voltage, C.sub.OUT is the output's decoupling capacitor and output load is connected in parallel with C.sub.OUT. All the node voltages are referred to ground GND in the following discussion.

(8) The architecture comprises five blocks, namely, amplifier A.sub.0 20, buffer 30, series-pass device with current sense 40, feedback network 50 and CC controller 60. The first block is an amplifier, A.sub.0 20, which has two input terminals and one output terminal. One of the inputs is a non-inverting input that connects to feedback voltage, V.sub.FB, which is generated by feedback network. The other input is an inverting input that connects to reference voltage, V.sub.REF, from reference generator, which is not shown in the figure. The output of the amplifier 20 is connected to a buffer 30. The said amplifier has two special features, Pseudo-Constant Bias (PCB) and Adaptive Compensation Network (ACN). PCB automatically biases the amplifier 20 and hence controls transconductance of the amplifier, Gm.sub.0, depending on the operating mode of the linear regulator. ACN adaptively alters speed and stability trade-off for a current regulation loop during the CC mode.

(9) The second block is a buffer 30 that has one input connecting to the output of amplifier, A.sub.0, and its output connecting to series-pass device 40. The main purpose is to pass the signal at the output of amplifier A.sub.0 to the input of series-pass device 40 without degradation. It isolates capacitive load seen by amplifier A.sub.0 from the series-pass device and enhances driving capability of amplifier A.sub.0. Buffer 30 acts as a level translator in case VDD.sub.1 and VDD.sub.2 have a different potential. The buffer is optional depending upon system requirement. It can be bypassed with the amplifier A.sub.0 output directly connecting to the input of series-pass device. It is assumed that the buffer has unity gain in the following discussion.

(10) The third block is a series-pass device with current sense. It has two inputs; one connects to the buffer output and another one connects to supply voltage, VDD.sub.2. Series-pass device 40 has two outputs, I.sub.OUT and I.sub.SEN, flowing current output from the block. The series-pass device controls the current flowing from VDD.sub.2 to I.sub.OUT and I.sub.SEN, biased on the voltage or current signal from the buffer. The series-pass device 40 can be implemented by a p-channel or n-channel MOSFET or bipolar junction transistor. For MOSFET implementation, the output voltage signal from the buffer is used to alter the amount of current flow through the MOSFET from VDD.sub.2. For bipolar junction transistor implementation, the output current signal from the buffer is used to alter the amount of current through the transistor from VDD.sub.2. The total current through the series-pass device 40 equals to the sum of I.sub.OUT and I.sub.SEN, wherein I.sub.OUT is supplied to the output load and feedback network, and whereas I.sub.SEN is a tracked, scaled down version of I.sub.OUT for modes detection. There are various ways to realize I.sub.SEN in the transistor level.

(11) The forth block is feedback network 50 which has of two inputs and one output. The two inputs sense the differential voltage between output voltage, V.sub.OUT, and ground, as demonstrated in FIG. 1. The output of feedback network 50, V.sub.FB, is a scaled down version of the said differential voltage, which can have different scaling factor based on the voltage signal's frequency range.

(12) The fifth block is CC controller 60 which has a trans-impedance amplifier, Z.sub.1, and a transconductance amplifier, G.sub.MI. The CC controller takes two input current signals, I.sub.SEN from series-pass device with current sense and reference current signal, I.sub.REF. Z.sub.1 compares I.sub.SEN and I.sub.REF, and then generates a voltage signal, V.sub.SEL, which is a voltage control signal for ACN in A.sub.0. V.sub.SEL is further transformed to current control signal, I.sub.SEL, for the PCB in A.sub.0.

(13) Working Principle

(14) The proposed architecture in FIG. 1 operates in two modes, namely CV mode and CC mode, depending on loading condition, V.sub.OUT and I.sub.OUT. The operating mode is illustrated in FIG. 2. The y-axis represents output voltage of a linear regulator, V.sub.OUT, whereas the x-axis represents output current, I.sub.OUT. Consider a regulator is set to maintain V.sub.OUT to be V.sub.TAG with a maximum output current of I.sub.TAG. The regulator operates along the lines AB in CV mode, where a voltage regulation loop is dominated. It delivers current to the output load in order to keep V.sub.OUT equal to V.sub.TAG. When I.sub.OUT equals to I.sub.TAG, CC mode is activated, and a current regulation loop is introduced that overpowers the voltage regulation loop in order to keep I.sub.OUT equal to I.sub.TAG. Therefore, the regulator operates along line BC and V.sub.OUT drops. When current requested by the load decreases, the regulator's operating point moves back from C to B as V.sub.OUT increases. At the time V.sub.OUT equals to V.sub.TAG, the current regulation loop passes the control to the voltage regulation loop and hence back to CV mode. There is a mode transition or handover from CV to CC mode and from CC to CV mode around point B.

(15) Voltage Regulation Loop

(16) For the proposed architecture, the voltage regulation loop 70 comprises amplifier A.sub.0 20, buffer 30, series-pass device with current sense 40 and feedback network 50, forming a negative feedback loop as shown in FIG. 3. The objective of the voltage regulation loop 70 is to maintain V.sub.FB to be equal to V.sub.REF, since V.sub.FB is a scaled-down version of V.sub.OUT, V.sub.OUT is regulated to be approximately

(17) $\begin{array}{cc}{V}_{\mathrm{OUT}}=\left\{\frac{{\mathrm{Gm}}_0{R}_0{\mathrm{Gm}}_{\mathrm{pass}}{R}_{\mathrm{OUT}}}{1+{\mathrm{Gm}}_0{R}_0{\mathrm{Gm}}_{\mathrm{pass}}{R}_{\mathrm{OUT}}}\right)V_{\mathrm{REF}}& \left(1\right)\end{array}$

(18) where Gm.sub.0 and R.sub.0 are the transconductance and output impedance of A.sub.0 respectively, Gm.sub.pass is the transconductance of series-pass device, R.sub.OUT is impedance of output load and is the scaling factor of feedback network. Consider an increase of I.sub.OUT, V.sub.OUT drops and hence V.sub.FB drops to be less than V.sub.REF. A.sub.0 amplifies the error (V.sub.FBV.sub.REF) to be V.sub.AMP with a gain of Gm.sub.0*R.sub.0. V.sub.AMP is given by equation (2).
V.sub.AMP=Gm.sub.0R.sub.0(V.sub.FBV.sub.REF)(2)

(19) As a result, the series-pass device allows more current to flow from VDD.sub.2 to V.sub.OUT, which compensates for the increase of I.sub.OUT. Therefore, V.sub.OUT restores to the targeted value as in equation (1). With a negative feedback loop, frequency compensation is required to ensure loop stability. As suggested in FIG. 3, a capacitor, C.sub.OUT, is placed at the output of the linear regulator. It introduces a low frequency pole as dominant pole and hence stabilizes the negative feedback loop.

(20) Current Regulation Loop

(21) The current regulation loop 80 comprises amplifier A.sub.0 20, buffer 30, series-pass device 40 and CC controller 60, forming another negative feedback loop as shown in FIG. 4. The objective of the current regulation loop 80 is to maintain I.sub.SEN to be equal to I.sub.REF, since I.sub.SEN is a scaled-down version of I.sub.OUT, I.sub.OUT is regulated to be approximately

(22) $\begin{array}{cc}{I}_{\mathrm{OUT}}=\left\{\frac{Z_1{\mathrm{Gm}}_1{R}_0{\mathrm{Gm}}_{\mathrm{pass}}{R}_{\mathrm{OUT}}}{1+M{Z}_1{\mathrm{Gm}}_1{R}_0{\mathrm{Gm}}_{\mathrm{pass}}{R}_{\mathrm{OUT}}}\right)I_{\mathrm{REF}}& \left(3\right)\end{array}$

(23) where Z.sub.1 and Gm.sub.1 is the trans-impedance gain and the transconductance gain of CC controller respectively, R.sub.0 is output impedance of A.sub.0, Gm.sub.pass is transconductance of series-pass device and M is the scaling ratio I.sub.OUT to I.sub.SEN. Consider an increase of I.sub.OUT, I.sub.SEN also increases as it is a scaled-down version of I.sub.OUT. I.sub.OUT is then compared with I.sub.SEN and the difference is converted to voltage signal, V.sub.SEL, by Z.sub.1. After that, V.sub.SEL is transformed to a current signal, I.sub.SEN by Gm.sub.1 inside CC controller. I.sub.SEN is further amplified by output impedance of A.sub.0 to V.sub.AMP through PCB and R.sub.0. V.sub.AMP is given by equation (4).
V.sub.AMP=Gm.sub.1R.sub.0Z.sub.1(I.sub.REFI.sub.SEN)(4)

(24) It is noted that the output impedance stage of A.sub.0, R.sub.0, is re-used in current regulation loop. V.sub.AMP controls the input of the series-pass device and allows less current to pass through. Finally, I.sub.OUT restores to a targeted value as in equation (3). From a loop stability concern, C.sub.OUT does not help stabilizing the loop as V.sub.OUT is not used in the current regulation loop. Therefore, a compensation capacitor, C.sub.C, is added for frequency compensation. Since C.sub.C is also located inside the voltage regulation loop, it also affects frequency compensation of voltage regulation loop. Here, ACN is introduced to alleviate the stated concern. It adaptively adjusts the value of C.sub.C base on the operating mode. When the regulator is in CV mode, the voltage regulation loop dominates and then C.sub.C is reduced by ACN to minimize effect on voltage regulation loop's stability. On the other hand, when the regulator is in CC mode, and current regulation loop dominates, the C.sub.C is then magnified by ACN and acts as the dominant role for frequency compensation.

(25) CV-CC Mode Transition

(26) Since there are two different modes for the regulator with two different loops that control V.sub.OUT and I.sub.OUT independently, while sharing same circuit blocks and resources, the mode transition and loop settling issues must be resolved. The mode transition issue refers to criteria or condition to switch from CV mode to CC mode and vice versa. The loop settling issue refers to how to handover from voltage regulation loop in CV mode to current regulation loop in CC mode, such that both loops settle smoothly and bias correctly and vice versa.

(27) When a regulator is working in CV mode, although the CC controller is not involved in voltage regulation, it is neither disabled nor shut down. The CC controller continuously monitors whether I.sub.SEN reaches upper bound that is set by I.sub.REF. Owing to the continuous monitoring, the regulator can detect mode change from CV to CC immediately, that is the instant when I.sub.SEN is larger than or equal I.sub.REF. Under CV mode, I.sub.SEN should be less than I.sub.REF, and Z.sub.1 acts as a comparator with a high bandwidth. V.sub.SEL behaves as a digital signal, which is bounded by VDD.sub.1 and GND, and disables the ACN. I.sub.SEL also behaves as a digital signal, which prevents PCB from changing Gm.sub.0 of A.sub.0. Hence, A.sub.0 functions as an amplifier that amplifies the error V.sub.FBV.sub.REF for voltage regulation with a gain Gm.sub.0*R.sub.0. The output, V.sub.AMP, controls the amount of current flow through the series-pass device. When I.sub.OUT is gradually increased due to load variation, I.sub.SEN is also increased and approaches I.sub.REF. At the time I.sub.SEN is larger than or equal to I.sub.REF, both V.sub.SEL and I.sub.SEL flip their state owing to the impedance gain, Z.sub.1 and transconductance gain Gm.sub.1. The regulator is changed from CV mode to CC mode, and both ACN and PCB are activated. It is noted that both V.sub.SEL and I.sub.SEL behave as an analog signal and contain the error term, I.sub.REFI.sub.SEN, as shown in equations (5) and (6).
V.sub.SEL=Z.sub.1(I.sub.REFI.sub.SEN)(5)
I.sub.SEL=Gm.sub.1Z.sub.1(I.sub.REFI.sub.SEN)(6)

(28) The error term, I.sub.REFI.sub.SEN, is used to regulate I.sub.SEN and hence current goes into the load, I.sub.OUT. Since ACN is activated, the compensation capacitor, C.sub.C, is magnified and used to compensate the current regulation loop for better stability. PCB is also enabled which degenerates the transconductance Gm.sub.0 used in voltage regulation loop. In addition, output impedance, R.sub.0, from A.sub.0 is re-used to amplify and convert I.sub.SEL to V.sub.AMP. Therefore, V.sub.AMP adjusts current passing through the series-pass device for current regulation. The overall gain for the current regulation loop is given by equation (7).
Gain=Gm.sub.1R.sub.0Z.sub.1(7)
CC-CV Mode Transition

(29) From the CV-CC mode transition, it is observed that the transition is triggered by an over current event, that is, I.sub.SEN is larger than or equal to I.sub.REF. After the transition, the voltage regulation loop is suppressed and the regulator is dominated by the current regulation loop, such that the regulator outputs a regulated current, I.sub.OUT.

(30) Consider another case when a regulator is working in the CC mode, although amplifier, A.sub.0, does not amplify the voltage error, V.sub.FBV.sub.REF, it is neither disabled nor shut-down. Owing to the unique bias scheme by PCB, Gm.sub.0 is degenerated and output impedance, R.sub.0, is re-used to amplify I.sub.SEL. The current regulation loop is stabilized by C.sub.C owing to ACN. Under CC mode, V.sub.FB should be less than V.sub.REF as the sourcing current by the output load is larger than the sinking current provided by the series-pass device. With the help of the PCB, the large difference between V.sub.FB and V.sub.REF does not interfere with V.sub.AMP, and A.sub.0 is not saturated nor distorted; instead it is maintained in a high gain operating point. When current drawn by the output load is gradually decreased, V.sub.OUT increases as excess current is stored in C.sub.OUT. At the time V.sub.FB ramps up and becomes close to V.sub.REF, the PCB is deactivated, Gm.sub.0 is regained while Gm.sub.1 is suppressed. As a result, A.sub.0 amplifies the voltage difference between V.sub.FB and V.sub.REF, the voltage regulation loop takes over the control of the regulator from the current regulation loop. I.sub.OUT gradually decreases since the regulator tries to regulate V.sub.OUT to a desired value. As I.sub.OUT and hence I.sub.SEN decreases, V.sub.SEL flips its state and turns off ACN. As a result, Z.sub.1 regains its bandwidth and keeps track of I.sub.SEN again. At this moment, the regulator is back to CV mode. Unlike CV-CC mode transition, the triggering event is determined by V.sub.OUT, specifically V.sub.FB being larger than V.sub.REF. Since the mode transitions are based on two different observations, the regulator will not be tripped in a metastable state, where the regulator's state oscillates between the CV-CC mode transition and the CC-CV mode transition.

(31) Features

(32) As noted, the CV and CC modes are commonly employed in power management unit. The foregoing disclosure addresses the mode transition issues and emphasizes the stability and smooth transition. The disclosed architecture improves CV-CC and CC-CV modes transition with the following three distinct features. 1. The Pseudo-Constant Bias (PCB) is a controller that provides proper bias for the amplifier, A.sub.0. In CV mode operation, PCB provides a bias such that Gm.sub.0 in A.sub.0 comes into effect. As a result, A.sub.0 has a gain of Gm.sub.0*R.sub.0 to amplify the difference between V.sub.FB and V.sub.REF. The control is then dominated by the voltage regulation loop, keeping V.sub.OUT to a desired value. In the CC mode operation, PCB provides another bias condition such that Gm.sub.0 in A.sub.0 is degenerated. Owing to the unique biasing scheme, output impedance of A.sub.0, R.sub.0, is re-used with Gm.sub.1 in the CC controller. This provides a gain of Gm.sub.1*R.sub.0 to amplify the difference between I.sub.SEN and I.sub.REF for output current regulation. It is noted that the amplifier, A.sub.0, is always operating in high gain region in both the CV and CC modes. This ensures that A.sub.0 and hence loop gains for both voltage regulation loop and current regulation loop are high enough to provide a high accuracy control during the CV-CC and CC-CV mode handover. It is recalled that the output of A.sub.0, V.sub.AMP, controls the series-pass device to adjust current pass through in all modes and transitions owing to the sharing of output impedance, R.sub.0, by PCB. 2. The Adaptive Compensation Network (ACN) is a controller that adjusts bandwidth and stability for the current regulation loop. In the CV mode, ACN disables the compensation network by C.sub.C and hence extends the bandwidth of the current regulation loop; therefore Z.sub.1 acts as a comparator and V.sub.SEL behaves as a digital signal. This helps the regulator to keep track of I.sub.SEN and responses to over current event immediately. In the CC mode, ACN is activated, and it magnifies the value of C.sub.C and hence limits the bandwidth of the current regulation loop. The ACN guarantees a compensated, stabilized negative feedback loop for current regulation in the CC mode. It is noted that the CV-CC transition has a fast response as it is desired to stop over current at once. On the other hand, the CC-CV transition has a slower response since the CC mode has a limited bandwidth. This allows a smooth transition from current regulation loop to voltage regulation loop without any glitches. 3. The trigger events for the CV-CC mode and CC-CV mode transitions are based on two different observations. As a result, the regulator will not fall into a case that oscillates between the two transitions. Under the CV mode, V.sub.OUT is regulated and I.sub.SEN is monitored by Z.sub.1. When I.sub.SEN is larger than I.sub.REF, the regulator is triggered and undergoes CV-CC mode transition and then enter CC mode. Under CC mode, I.sub.OUT is regulated and V.sub.FB is monitored by PCB. When V.sub.FB ramps up and approaches V.sub.REF, the regulator is triggered and undergoes the CC-CV mode transition and then enters the CV mode.
Transistor-Level Implementation

(33) One embodiment of the transistor-level implementation for the proposed architecture as a linear regulator 12 is shown in FIG. 5. The amplifier, A.sub.0, comprises P0, P1, P2, P3, N0, N1, N2 and N3, where Gm.sub.0 is the transconductance of P0, P1 pair and R.sub.0 is the drain-source impedance of P3 and N3. The buffer is optional depending upon system requirement. The series-pass device with current sense is implemented as a pair of matched PMOS, P4 and P5, with a size ratio of M to 1. The amplifier A.sub.2 and N8 form a negative loop to track the drain-source voltages of P4 and P5. Since gate-source and drain-source voltages for P4 and P5 are matched, the drain currents are matched with a ratio of M to 1 and drain current of P5 is equivalent to I.sub.SEN. The feedback network is formed by a resistive divider, R.sub.1 and R.sub.2. The CC controller is formed by Z.sub.1 and N7, where Gm.sub.1 is the transconductance of N7.

(34) The Pseudo-Constant Bias (PCB) is formed by N4, N5, N6, N7 and V.sub.BH. The objective is to bias transistors in A.sub.0 in the CV and CC mode. Gate voltage and hence drain current of N5 and N7 are controlled by Z.sub.1. N4, N5 and V.sub.BH are employed to reduce systematic offset of A.sub.0 due to the introduction of N5 and N7. V.sub.BN is a voltage source that matches with voltage level high when Z.sub.1 acts a comparator in the CV mode.

(35) Consider the linear regulator 12 in the CV mode wherein V.sub.SEL is high level and a large drain current can pass through N5 and N7. However, the drain currents for all transistors in A.sub.0 are limited by I.sub.BIAS and hence transconductance of N5 and N7 are degenerated. The transconductance from P0, P1 pair is dominant and hence the voltage regulation loop takes over the regulator's control.

(36) Consider the linear regulator 12 in the CC mode. Since source impedance between N1, N3 pair and the N0, N2 are imbalanced, hence transconductance Gm.sub.0 from P0, P1 pair is then degenerated. As a result, Gm.sub.1 from N7 is dominant and the current regulation loop comes into effect. The output impedance by P3 and N3 amplifies V.sub.SEL to V.sub.AMP which re-uses the same transistors in A.sub.0 for silicon area and power saving. It is noted that P0, P1, P2, N0, N1, N2 and I.sub.BIAS couple V.sub.SEL to the gate of P3, forming a push-pull output stage. It is also noted that owing to the high loop gain, drain current of P3, N3 are forced to be the same, meaning that four branch currents, with N4, N5, N6 and N7 at the bottom, are forced to be the same. This enforces A.sub.0 to stay in high gain region in both the CC and CV mode.

(37) The Adaptive Compensation Network (ACN) comprises N3, N7, P3, buffer (optional) and C.sub.C. The objective is to magnify the capacitance C.sub.C in the loop transfer function depending on the operating mode. In the CV mode, the capacitance of C.sub.C is the same as its physical value. In the CC mode, the effective capacitance of C.sub.C is amplified by a gain of Gm.sub.1*R.sub.0 due to the Miller effect. Due to the Miller effect, the current regulation loop is compensated.

(38) Simulation Results

(39) The transistor-level embodiment of linear regulator 12 in FIG. 5 is verified by simulation. A linear regulator with output voltage of 3V and over current protection of 100 mA is designed. FIG. 6 shows the simulation results. VDD is the supply voltage of the regulator, V.sub.OUT is the output voltage of the regulator, IDD is the supply current that sinks from VDD. V.sub.SEL is the internal node voltage in the CC controller. From time=0 ms to 4 ms, VDD and hence V.sub.OUT ramp up. From time=4 ms to 25 ms, V.sub.OUT is regulated to the desired value, and the regulator is in CV mode. At time=25 ms, the output is suddenly shorted to ground. IDD is limited to 100 mA and V.sub.OUT is discharged. The regulator enters CC mode so that V.sub.SEL is set to a low voltage. At time=50 ms, the short circuit load is released, the regulator is still operating in CC mode. From time=50 ms to 54 ms, IDD is held at 100 mA and the excess current is used to charge up output capacitor. When V.sub.OUT is close to 3V, the regulator switched back to CV mode and V.sub.SEL is pulled high at the same time.

(40) While preferred embodiments of the foregoing have been set forth for purposes of illustration, the foregoing description should not be deemed a limitation of the invention herein. Accordingly, various modifications, adaptations and alternatives may occur to one skilled in the art without departing from the spirit and the scope of the present invention.