Method for Block Cipher Enhanced by Nonce Text Protection and Decryption Thereof

Abstract

A method for block cipher enhanced by nonce text protection comprises: (a) providing a plain text data block; (b) inputting a corresponding nonce text based-on the plain text; (c) combining the plain text data with the nonce text to form a mix text with block length equal to block length of the plain text plus block length of the nonce text; and (d) utilizing a block encryption process to encrypt the mix text to generate a cipher text.

Claims

1. A method for block cipher enhanced by nonce text, applied to an electronic device for executing data encryption, comprising: (a) providing a plain text of M-bit with a first block length, (b) inputting a nonce text of N-bit corresponding the plain text of M-bit, wherein the nonce text having a second block length, (c) combining the plain text with the nonce text to form a mix text of (M+N)-bit with block length equal to the first block length of the plain text plus the second block length of the nonce text, and (d) utilizing a block encryption process to encrypt the mix text to generate a cipher text with (M+N)-bit.

2. The method for block cipher encryption enhanced by nonce text of claim 1, wherein the nonce text is produced by a non-constant generator.

3. The method for block cipher encryption enhanced by nonce text of claim 2, wherein the non-constant generator comprises random number generator.

4. The method for block cipher encryption enhanced by nonce text of claim 1, wherein the method for block cipher further comprises adding a key.

5. The method for block cipher encryption enhanced by nonce text of claim 4, wherein block length of the key is chosen from the used of algorithm of conventional encryption according to encrypting fixed block length.

6. The method for block cipher encryption enhanced by nonce text of claim 1, wherein the method for block cipher encryption further comprises conventional encryption of fixed block length.

7. A method for block cipher decryption applied to an electronic device, where the block cipher is encrypted by the method of claim 1, comprising: (a) utilizing a method for block cipher decryption corresponding to the method for block cipher encryption of claim 1 for decrypting the cipher text to form the mix text, and (b) utilizing a resolver corresponding to the combining method of claim 1 for resolving the mix text into the plain text.

8. The method for block cipher decryption of claim 7, the block cipher is encrypted by the method of claim 1, wherein a key for the block cipher encryption and decryption are the same.

9. The method for block cipher decryption of claim 8, the block cipher is decrypted by the method of claim 1, wherein block length of the key is chosen from the used of algorithm of conventional encryption according to encrypting fixed block length.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The components, characteristics and advantages of the present invention may be understood by the detailed descriptions of the preferred embodiments outlined in the specification and the drawings attached:

[0016] FIG. 1 illustrates a block diagram of a method for block cipher enhanced by nonce text encryption according to the present invention of an embodiment.

[0017] FIG. 2 illustrates a block diagram of a method for block cipher enhanced by nonce text decryption according to the present invention of an embodiment.

[0018] FIG. 3 illustrates a block diagram of a method for block cipher enhanced by nonce text encryption according to the present invention of another embodiment.

[0019] FIG. 4 illustrates a block diagram of a method for block cipher enhanced by nonce text decryption according to the present invention of another embodiment.

DETAILED DESCRIPTION

[0020] Some preferred embodiments of the present invention will now be described in greater detail. However, it should be recognized that the preferred embodiments of the present invention are provided for illustration rather than limiting the present invention. In addition, the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is not expressly limited except as specified in the accompanying claims.

[0021] Please refer to FIG. 1, a method for block cipher enhanced by nonce text encryption according to the present invention, comprising: M-bit plain text 102 and N-bit nonce text 104 are combined to form (M+N)-bit mix text 108 by a combiner 106, wherein the nonce text 104 is produced through a random number generator outside, also, the mix text 108 is encrypted by a (M+N)-bit conventional encryption 100 to form a (M+N)-bit cipher text 114. In the block cipher step of mix text 108, adding an encryption key 110 for block cipher, the block length of encryption key 110 is chosen standing on the algorithm of conventional encryption 100, which could be referred as key in the present invention.

[0022] In FIG. 1, the logical relation between plain text 102, nonce text 104, mix text 108 could be described by IEEE standard Verilog as below:

mix_text[M+N1:0]=(plain_text[0]<<A.sub.0)|(plain_text[1]<<A.sub.1)| . . .

(plain_text[M1]<<A.sub.M1)|(nonce_text[0]<<B.sub.0)|(nonce_text[1]<<B.sub.1)| . . .

(nonce_text[N1]<<B.sub.N1)

wherein the parameters A.sub.0 A.sub.M1, B.sub.0B.sub.N1 are chosen from the integers between 0 to (M+N1), said logical relation also meet the following condition:

(1<<A.sub.0)|(1<<A.sub.1)| . . . (1<<A.sub.M1)|(1<<B.sub.0)|(1<<B.sub.1)| . . . (1<<B.sub.N1)=={(M+N){1b1}}

[0023] The parameter A.sub.0A.sub.M1, B.sub.0B.sub.N1 are chosen from the integers between 0 to (M+N1) with M non-repetitive integers for arbitrary arrangement, then assigning to A.sub.0A.sub.M1 in order, also, arbitrary arrangement of the rest N integers are made, then assigning to B.sub.0B.sub.N1 in order.

[0024] According to one embodiment of the present invention, the combiner 106 in electrical device may be achieved by hardware, software, or a combination of hardware and software.

[0025] In FIG. 1, the method could be implemented by prior art except the combiner 106. Thus, the method for block cipher enhanced by nonce text encryption according to the present invention could be achieved by hardware, software, or a combination of hardware and software through the prior art.

[0026] As illustrating in FIG. 2, the method for block cipher enhanced by nonce text decryption according to the present invention, comprising: the (M+N)-bit cipher text 114 is decrypted via a (M+N)-bit conventional decryption 200 to form a (M+N)-bit mix text 108, which then be resolved into M-bit plain text 102 and N-bit nonce text 104 by a resolver 206.

[0027] The above method of conventional encryption 100 and conventional encryption 200 are used for encrypting a fixed block length mix text 108 and decrypting a fixed block length cipher text 114 respectively, wherein the same key is used for encryption and decryption.

[0028] Please refer to FIG. 2, the logical relation between plain text 102, nonce text 104, mix text 108 could be described by IEEE standard Verilog as below:

plain_text[M1:0]={mix_text[A.sub.M1],mix_text[A.sub.M2], . . . , mix_text[A.sub.0] }

nonce_text[N1:0]={mix_text[B.sub.N1],mix_text[B.sub.N2], . . . , mix_text[B.sub.0]}

wherein the parameters A.sub.0A.sub.M1, B.sub.0B.sub.N1 should equal to A.sub.0A.sub.M1, B.sub.0B.sub.N1 which is chosen in the method for block cipher enhanced by nonce text encryption.

[0029] Similarly, the combiner 206 in electrical device may be achieved by hardware, software, or a combination of hardware and software.

[0030] As illustrating in FIG. 2, the method could be implemented by prior art except the combiner 206.

[0031] Thus, the method for block cipher enhanced by nonce text decryption according to the present invention could be achieved by hardware, software, or a combination of hardware and software through the prior art.

[0032] Take AES algorithm, block length 128-bit of encryption key 310, M=64, N=64 as an embodiment, the method for block cipher enhanced by nonce text encryption could be achieved, as illustrating in FIG. 3, comprising: 64-bit plain text 302 and 64-bit nonce text 304, combined to form 128-bit mix text 308 by a combiner 306, wherein the mix text 308 is encrypted through AES encryption 300 into 128-bit cipher text 314. In the block cipher step of mix text 308, adding a 128-bit encryption key 310 for block cipher.

[0033] According to above, integers are chosen from between 64127, then assigning to A.sub.0A.sub.31 in order; integers are chosen from between 063, then assigning to B.sub.0B.sub.31 in order.

[0034] According to above, the logical relation between plain text 302, nonce text 304, mix text 308 could be described by IEEE standard Verilog as below:

mix_text[127:0]=(plain_text[0]<<64)|(plain_text[1]<<65)| . . .

(plain_text[63]<<127)|(nonce_text[0]<<0)|(nonce_text[1]<<1)| . . .

(nonce_text[63]<<63)

the above description could further simplified as below:

mix_text[127:0]={plain_text[63:0],nonce_text[63:0]}

[0035] Similarly, the combiner 306 in electrical device may be achieved by hardware, software, or a combination of hardware and software.

[0036] In FIG. 3, the method could be implemented by prior art except the combiner 306. Thus, the method for block cipher enhanced by nonce text encryption according to the present invention could be achieved by hardware, software, or a combination of hardware and software through the prior art.

[0037] Take AES algorithm, M=64, N=64 as an embodiment, the method for block cipher enhanced by nonce text decryption of the present invention could be achieved, as illustrating in FIG. 4, comprising: A 128-bit cipher text 314, decrypted to 128-bit mix text 308 via AES decryption 400, which then be resolved into 64-bit plain text 302 and 64-bit nonce text 304 by a resolver 406.

[0038] Similarly, the logical relation between plain text 302, nonce text 304, mix text 308 could be described by IEEE standard Verilog as below:

plain_text[63:0]={mix_text[127],mix_text[126], . . . ,mix_text[64]}

nonce_text[63:0]={mix_text[63],mix_text[62], . . . ,mix_text[0]}

the above description could further simplified as below:

plain_text[63:0]=mix_text[127:64]

nonce_text[63:0]=mix_text[63:0]

[0039] Similarly, the resolver 406 in electrical device may be achieved by hardware, software, or a combination of hardware and software.

[0040] In FIG. 4, the method could be implemented by prior art except the resolver 406.

[0041] Thus, adopting AES algorithm, key block length 128-bit, M=64, N=64, the method for block cipher enhanced by nonce text decryption according to the present invention could be achieved by hardware, software, or a combination of hardware and software through the prior art.

[0042] The advantages of the present invention including:

1. A method for block cipher enhanced by nonce text encryption and may be applied to the conventional block cipher, the data confidentiality is reinforced since the enforcement adding the nonce text produced by non-constant generator.
2. Said non-constant generator could be a random number generator, which is art of mature for now on.
3. The use of the method in the present invention with block cipher in ECB mode, the combination of the nonce text resulting in two benefits. On the one hand, it improves the weakness of less data confidentiality in ECB mode, that is, it would result in different encrypt text for the same plain text encrypted in different times, on another hand, the advantage of different block ciphers independent on each other and could be decrypted independently would still be reserved.
4. It could increase the data confidentiality in streaming media data quite apparently for adopting the method of ECB mode with the present invention.
5. Also, the data confidentiality in non-contact IC card could increase quite apparently for adopting the method of ECB mode with the present invention as well.

[0043] As will be understood by persons skilled in the art, the foregoing preferred embodiment of the present invention illustrates the present invention rather than limiting the present invention. Having described the invention in connection with a preferred embodiment, modifications will be suggested to those skilled in the art. Thus, the invention is not to be limited to this embodiment, but rather the invention is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation, thereby encompassing all such modifications and similar structures. While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made without departing from the spirit and scope of the invention.