SINGLE LAMINATION BLIND AND METHOD FOR FORMING THE SAME

Abstract

A method and structure that forms a PCB while removing or eliminating a stub from a via without back-drilling or doing multi-laminations. In the preferred embodiment, the printed circuit board includes a via extending through a plurality of stacked layers. The via includes a plated through hole that is connected to at least two other metalized layers. There is a portion of the via that is extraneous and that has a negative performance on the functionality of the printed circuit board. The single lamination buried via method adds a seed layer resist that prevents an electrical connection during electroplating thus preventing the via from metalizing where it is not desired.

Claims

1. A method of forming a printed circuit board (PCB) while removing or preventing a stub from forming a via of a printed circuit board (PCS) the steps comprising: forming a multi-layered printed circuit board (PCB) of individual layers that are pressed together by first etching each of said individual layers of said PCB except for the an outer layer; placing a first signal trace on any one of said layers of said PCB; placing a second signal trace on another layer of said PCB; adding or inserting seed resist material to said layers of said PCB; drilling at least one via hole through said PCB and intersecting said first signal trace and said second signal trace with a conductive material that is electro-deposited on said layers of said first and said signal traces; applying plating seed resist layer by electroless plating; and etching outer layers thereby preventing electrically conductive material from attaching to the walls of said vias prior to electro-deposition of conductive material thereby electro-plating said via and adding or inserting seed-resist material on a wall of said via; adding or inserting a seed-resist material into said PCB on said via hole to prevent electrically conductive material from attaching to a wall of said vias prior to electro-deposition of conductive material.

2. The method according to claim 1 when said multiple layers of said PCB include copper, copper clad core and partially cured dielectric (pre-preg).

3. The method according to claim 1 where said seed-resist material separates at the top and bottom electrical transmission lines showing said via while removing electrically isolation from each via.

4. A structure for a multi-layered a printed circuit board (PCB) comprising: a multi-layered printed circuit board (PCB) formed of individual layers that pressed together that are first etching each of said individual layers of said PCB except for an outer layer; a first signal trace placed on any one of said layers of said PCB; a second signal trace placed on another layer of said PCB; adding or inserting seed resist material to said layers of said PCB; At least one via hole drilled through said PCB and intersecting said first signal trace and said second signal trace with a conductive material that is electro-deposited on said layers of said first and said signal traces; plated seed resist layer applied by electroless plating to said layers; and said outer layers being etched thereby preventing electrically conductive material from attaching to walls of said vias prior to electro-deposition of conductive material thereby electro-plating said via and adding or inserting seed-resist material on a wall of said via; seed-resist material added or inserted into said PCB on said via hole to prevent electrically conductive material from attaching to a wall of said vias prior to electro-deposition of conductive material.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0006] FIG. 1 illustrates a common construction of a PCB before the individual layers have been pressed together in accordance with the teachings of the present invention.

[0007] FIG. 2 illustrates the component of the FIG. 1 following their lamination to form the PCB.

[0008] FIG. 3 illustrates the drilling process for the vias of FIG. 1.

[0009] FIG. 4 shows deposition of a conductive layer used for electro-plating also referred to as a seed layer for FIG. 1

[0010] FIG. 5 shows the PCB of the electroplating of FIG. 1. In FIG. 5, the conductive material in the via (9) is formed by an electro-plating process. The seed-resist gap in the seed-resist layer can be selectively preventing plating by breaking the electrical conduction path which is required for electro-plating.

[0011] FIG. 6 illustrates the final board stage after the top and bottom layer are meshed and etched as part of a typical PCB fabrication process of FIG. 5. In FIG. 6, the top and bottom layers are masked and etched as part of a typical PCB fabrication process.

[0012] FIG. 7 shows the methodology of the present invention in which the seed-resist material is employed to separate the top and bottom electrical paths thus permitting two electrical transmission lines to share the via while remaining isolated from each other.

[0013] FIG. 8 is a flowchart showing a standard example of a via plating process for a PCB as described in FIGS. 1-6; and

[0014] FIG. 9 is a flow chart showing the single lamination methodology as described in FIG. 8 and in accordance with the teachings of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0015] Referring now to FIGS. 1-9 of the drawings, FIG. 1 illustrates a common construction of a PCB before the individual layers are pressed together. A typical PCB is formed of multiple layers copper, copper clad core (1) and a partially cured dielectric also known as pre-preg (2). A seed-resist material (4) is deposited on two layers. FIG. 1 shows a common construction of a PCB before the individual layers have been pressed together. A typical PCB is made up of multiple layers of copper, copper clad core (1), and partially cured dielectric also known as pre-preg (2). Deposited on two layers is the seed-resist (4).

[0016] FIG. 2 shows the components in FIG. 1 after they have been laminated to form the PCB (10) or printed circuit board (10). FIG. 2 shows the components in FIG. 1 after they have been laminated. This forms the PCB (10) or circuit board.

[0017] FIG. 3 illustrates the drilling process for vias (9) formed in the PCB (10).

[0018] FIG. 4 shows deposition of a conductive layer used for electro-plating also referred to as a seed layer for FIG. 1. FIG. 4 shows the deposition of a conductive layer used for electroplating (6). This is sometimes referred to as the seed layer. Examples of this are electroless CU, Pd colloidal system, carbon colloidal system, or conductive polymer system. The deposited seed-resist material (4) will not allow the conductive seed layer to bond to the surface creating a gap in the seed layer at that location (7). Examples of this type of material are Teflon or Kapton.

[0019] FIG. 5 shows the PCB of the electroplating of FIG. 1. FIG. 5 shows the same board after electroplating. The conductive material in the via is formed by an electroplating process. The seed-resist gap in the seed layer can selectively prevent plating by breaking the electrical conduction path that is required for electroplating.

[0020] FIG. 6 illustrates the final board stage after the top and bottom layer are meshed and etched as part of a typical PCB fabrication process of FIG. 5. FIG. 6 shows the final board stage after the top and bottom layer are masked and etched as part of a typical PCB fabrication process.

[0021] FIG. 7 shows the methodology of the present invention in which the seed-resist material is employed to separate the top and bottom electrical paths thus permitting two electrical transmission lines to share the via while remaining isolated from each other. FIG. 7 shows the methodology and structure of the present invention. In this embodiment, the seed-resist material is used to separate the top and bottom electrical paths. This allows for two electrical transmission lines to share the via without while remaining electrically isolated from each other.

[0022] FIG. 8 is a flowchart showing a standard example of a via plating process for a PCB. FIG. 8 illustrates a standard example of constructing a via plating process for a PCB.

[0023] FIG. 9 is a flow chart showing the single lamination methodology in accordance with the teachings of the present invention. FIG. 9 describes the methodology of the present invention. In FIG. 8, the present invention discloses a method of forming a printed circuit board (PCB) while removing or preventing a stub from forming a via of a printed circuit board (PCB).

[0024] First a multi-layered printed circuit board (PCB) of individual layers is formed that are pressed together by first etching each of said individual layers of said PCB except for an outer layer.

[0025] Next a first signal trace is placed on any one of said layers of said PCB.

[0026] Then a second signal trace is placed on another layer of said PCB adding or inserting seed resist material to said layers of said PCB.

[0027] At least one via hole is drilled through said PCB and intersecting said first signal trace and said second signal trace with a conductive material that is electro-deposited on said layers of said first and said signal traces. Plated seed resist layer is then applied by electroless plating.

[0028] The outer layers are etched thereby preventing electrically conductive material from attaching to walls of said vias prior to electro-deposition of conductive material thereby electro-plating said via and adding or inserting seed-resist material on a wall of said via.

[0029] A seed-resist material is added or inserted into the PCB on said via hole to prevent electrically conductive material from attaching to a wall of said vias prior to electro-deposition of conductive material.

[0030] Embodiments described herein may include PCBs in various stages of manufacture, and related methods of fabrication of PCBs. For example, the description describes a single lamination PCB board manufacturing process, but the embodiment of this method extends to multi-lamination PCBs or other alternate construction methodologies.

[0031] In the foregoing description, numerous details are set forth to provide an understanding of the present invention.

[0032] The FIGS. depict the embodiments, implementations, and the configurations of the invention, and not the invention itself.

[0033] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that it is not intended to limit the invention to the particular form disclosed, but rather, the invention is to cover all modifications, equivalents, and alternatives falling with the scope and spirit of the invention.