Method for producing an organic CMOS circuit and organic CMOS circuit protected against UV radiation

Abstract

An organic CMOS circuit including a substrate having an N-type organic transistor and a P-type organic transistor formed thereon, the transistors respectively including a layer of N-type semiconductor material and a layer of P-type semiconductor material. A surface of each of the semiconductor material layers, opposite to the substrate, is covered with an anti-ultraviolet layer made of electrically-insulating material absorbing and/or reflecting ultra-violet rays.

Claims

1. A method of manufacturing an organic CMOS circuit comprising a substrate having an N-type organic transistor and a P-type organic transistor formed thereon, the method comprising the steps of: forming first, second, and third separate conductive electrodes on a surface of a support; depositing over an entire surface of the support a first layer of organic semi-conductor material of a first conductivity type; partially removing the first layer of semiconductor material to only keep a first portion of semiconductor material at least partially covering the first electrode, at least partially covering the second electrode, and covering an area of a surface of a support connecting the first and second electrodes; depositing over the entire surface of the support a second layer of an organic semiconductor material of a second conductivity type, opposite to the first conductivity type; partially removing the second layer of semiconductor material to only keep a second portion at least partially covering the second electrode, at least partially covering the third electrode, and covering an area of a surface of a support connecting the second and third electrodes; wherein prior to the partial removal of the first layer of semiconductor material, an anti-ultraviolet layer made of an electrically-insulating material absorbing and/or reflecting ultraviolet rays is deposited on the first portion of semiconductor material; and wherein prior to the partial removal of the second layer of semiconductor material, an anti-ultraviolet layer made of electrically-insulating material absorbing and/or reflecting ultraviolet rays is deposited on the second portion of semiconductor material.

2. The method of manufacturing the organic CMOS circuit of claim 1, wherein the anti-ultraviolet layers comprise an organic matrix having ZnO, TiO.sub.2, CeO.sub.2, and/or organoclay particles.

3. The organic CMOS circuit manufacturing method of claim 2, wherein the particles are coated with silica.

4. The organic CMOS circuit manufacturing method of claim 2, wherein the particles have their dimensions in the range from 1 nanometer to 200 nanometers.

5. The organic CMOS circuit manufacturing method of claim 4, wherein the particles have their dimensions in the range from 20 nanometers to 30 nanometers.

6. The organic CMOS circuit manufacturing method of claim 2, wherein the particles amount to from 45% to 55% of the mass of the anti-ultraviolet layer.

7. The organic CMOS circuit manufacturing method of claim 2, wherein the organic matrix is made of a fluorinated polymer.

8. The organic CMOS circuit manufacturing method of claim 7, wherein the organic matrix comprises an amorphous fluoropolymer.

9. The organic CMOS circuit manufacturing method of claim 1, wherein the anti-ultraviolet layers comprise polystyrene latex and/or pyrene carboxylic acid.

10. The organic CMOS circuit manufacturing method of claim 1, wherein the anti-ultraviolet layers have a thickness in the range from 50 nanometers to 800 nanometers.

11. The organic CMOS circuit manufacturing method of claim 10, wherein the anti-ultraviolet layers have a thickness in the range from 100 nanometers to 200 nanometers.

12. The organic CMOS circuit manufacturing method of claim 1, wherein the anti-ultraviolet layers have a thickness greater than 800 nanometers, and wherein the anti-ultraviolet layers are removed after completion of the first and second portions of semiconductor material.

13. The organic CMOS circuit manufacturing method of claim 1, wherein the partial removals of the layers of semiconductor material are performed by means of a plasma etching.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will be better understood on reading of the following description provided as an example only in relation with the accompanying drawings, where the same reference numerals designate the same or similar elements, among which:

(2) FIGS. 1 to 11 are simplified cross-section views illustrating a method according to a first embodiment of the invention; and

(3) FIGS. 12 to 14 are simplified cross-section views illustrating a method according to a second embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

(4) As known per se, a CMOS circuit comprises a P-type organic transistor and an N-type organic transistor sharing a common gate, the source of a transistor further being the drain of the other transistor, or the transistors sharing a common drain. In the following, a high gate-type transistor topology is described. Of course, the invention applies to any type of topology, particularly to a low gate-type topology. Similarly, electrodes common to the two transistors are described, such electrodes for example being formed of a single element which fulfils two functions. It should be understood that the invention also applies to any type of electrode and of connection diagram thereof.

(5) A method of manufacturing an organic CMOS circuit according to a first embodiment will now be described in relation with FIGS. 1 to 11.

(6) The method starts (FIG. 1) with the forming of an organic or inorganic substrate 10 having a thickness in the range from 25 micrometers to 1 millimeter, made of silica, or silicon, of polyethylene terephthalate (PET), of polyethylene naphthalate (PEN), of polyimide (PI), of polyether imide (PEI), of polyether sulfone (PES), of polysulfone (PSF), of polyphenylene sulphide (PPS), of polyether ether ketone (PEEK), of polyacrylate (PA), of polyamide imide (PAI), of polystyrene, of polyethylene, of polypropylene, of a polyamine resin, of a carbonate resin, or of a cellulose resin. For example, the substrate is made of PET or of PEN having a thickness in the range from 100 micrometers to 150 micrometers, particularly 125 micrometers, which enables to define a flexible substrate having a good temperature behavior and a good mechanical behavior.

(7) The method carries on (FIG. 2) by the deposition of a layer of conductive material 12 over a thickness in the range from 20 nanometers to 100 nanometers, preferably 30 nanometers, followed by an etching, for example, chemical, implemented to define a first, a second, and a third electrodes 14, 16, 18 defining the drain and source electrodes of two organic transistors (FIG. 3). The material forming electrodes 14, 16, 18 is a metal, for example, gold (Au), silver (Ag), copper (Cu), nickel (Ni), palladium (Pd), platinum (Pt), aluminum (Al), titanium (Ti), chromium (Cr), molybdenum (Mo), a conductive polymer, for example, poly(3,4-ethylenedioxythiophene) (PEDOT) mixed with poly(styrene sodium sulfonate) (PSS), polyaniline (Pani), or a conductive metal oxide, for example, indium-tin oxide (ITO), aluminum zinc oxide (AZO), tungsten trioxide (WO.sub.3).

(8) Optionally, when the electrodes are made of metal, a material modifying their work function is further deposited thereon to improve the charge injection into the semiconductor materials with which they will subsequently be in contact to form transistors.

(9) Further, first electrode 14 and a portion of second electrode 16, having an N-type semiconductor element constitutive of the N-type transistor subsequently deposited thereon, are covered with a layer of a few nanometers of SAM (self-assembled monolayer), particularly of 4-(methylsulfanyl)-thiophenol (MeSTP), of 4-methoxythiophenol (MeOTP), of 4-methylthiophenol (MeTP), of 4-aminothiophenol (ATP), of 4-nitrothiophenol (NOTP), of cysteamine (CT), of 1-decanethiol (DT), of 1H,1H,2H,2H-perfluorodecanethiol (PFDT), or of 1H,1H,2H,2H-perfluorooctanethiol (PFOT).

(10) Similarly, third electrode 18 and a portion of second electrode 14 having a P-type doped semiconductor element constitutive of a P-type MOS transistor subsequently deposited thereon, are covered with a layer of a few nanometers of SAM, particularly of perfluorobenzenethiol (PFBT).

(11) Advantageously, before the deposition of the SAM layers, substrate 10 and electrodes 14, 16, 18, undergo a cleaning which improves the grafting of SAMs on the electrodes and the bonding of the substrate to the subsequently-deposited semiconductor materials. For example, the cleaning is performed by means of a plasma.

(12) In a next step, a layer of N-type organic semiconductor material 20 is deposited over the entirety of support 10 and of electrodes 14, 16, 18 (FIG. 4). The thickness of the layer of semiconductor material is preferably in the range from 70 nanometers to 120 nanometers so as to decrease, or even to avoid, parasitic resistances in the organic transistors.

(13) The method then carries on with the deposition of a first anti-UV mask 22 on the layer of N-type organic semiconductor material 22, the geometry of the mask corresponding to that of the semiconductor element comprised in the N-type organic transistor (FIG. 5). Anti-UV mask 22 is made of an electrically-insulating organic material further having an anti-UV radiation reflective or absorbing power, which protects against UV rays the portion of semiconductor material 24 on which it is deposited, as will be explained in further detail hereafter.

(14) An etching is then applied to remove N-type semiconductor material layer 20, except for portion 24 having anti-UV mask 22 deposited thereon (FIG. 6). The presence thereof enables to use etchings associated with a UV ray emission, including a high UV emission. Particularly, a plasma etching is implemented, this technique having the advantage of being a dry etching only applied to the targeted surface and enabling to orthogonally etch layer 20. Other etchings are however possible, for example, a chemical etching.

(15) In a next step, a layer of P-type doped semiconductor material 26 is deposited all over the assembly obtained at the previous step (FIG. 7). Layer 26 has a thickness between 70 nanometers and 120 nanometers to limit parasitic resistances.

(16) A second anti-UV mask 28 is then deposited on the layer of organic P-type semiconductor material 26, the geometry of the second mask 28 corresponding to that of the semiconductor element constitutive of the P-type organic transistor (FIG. 8). Second anti-UV mask 26 is made of an electrically-insulating organic material further having an anti-UV radiation reflective or absorbing power which protects against UV rays the portion of semiconductor material 26 on which it is deposited, as will be explained in further detail hereafter.

(17) An etching is then applied to remove the layer of P-type semiconductor material 26, except for portion 30 having anti-UV mask 22 deposited thereon (FIG. 9). Due to the presence thereof, it is also possible to use etchings associated with a UV ray emission, including a high UV emission. Particularly, a plasma etching is implemented. Other etchings are however possible, for example, a chemical etching.

(18) In a next step, an organic dielectric layer 32 is formed to electrically insulate semiconductor material portions 24, 30 and to leave a portion of the second electrode 16 exposed (FIG. 10). For example, the dielectric layer is deposited on support 10, electrodes 14, 16, 18 and the islands formed of semiconductor material portions 24, 30 and of anti-UV masks 22, 28, after which a portion of dielectric layer 32 is etched to expose a portion of second electrode 16. Dielectric layer 32 is for example made of a fluorinated polymer, particularly of CYTOP, of polyvinylphenol (PVP), of polymethyl methacrylate (PMMA) combined or not with acrylate, polystyrene, or polyimide, and has a thickness in the range from 500 nanometers to 1 micrometer.

(19) Finally, the method ends with the deposition of a first and of a second conductive gate electrodes 34, 36 on dielectric layer 32, respectively above the first and second electrodes 14, 16 and above the second and third electrodes 16, 18, by a thickness in the range from 30 nanometers to 1 micrometer, and preferably from 50 nanometers to 200 nanometers, as well as a conductive area 38 of contact with second electrode 38. Electrodes 34, 38 and contacting areas 38 are for example made of a material described in relation with electrodes 14, 16, 18, for example, a material identical to that of electrodes 14, 16, 18.

(20) A CMOS circuit comprising an organic N-type transistor, comprising or formed of the first and the second electrodes 14, 16 respectively forming the drain and the source of the transistor, of N-type semiconductor portion 24, of dielectric layer 32, and of gate 34, and an organic P-type transistor, comprising or formed of the second and the third electrodes 16, 18, respectively forming the source and the drain of the transistor, of P-type semiconductor portion 30, of dielectric layer 32, and of gate 36, has thus been obtained.

(21) The organic semiconductor layers constitutive of the N and P transistors have thus been protected from UV rays during the circuit manufacturing and are protected during the circuit use by anti-UV masks 22, 28.

(22) The embodiment which has just been described further has the following advantages: the presence of anti-UV masks 22, 28 in the CMOS circuit further enables to do away with an upper anti-UV encapsulation layer. the possibility of using a dielectric layer and/or transparent gates, since an anti-UV protection is implemented by the masks. For example, the gates may have a low thickness letting through a significant quantity of visible radiation, and incidentally also a significant quantity of UV rays. Thus, for certain applications, the thickness and/or the choice of the gate materials are selected so that the latter are transparent; each anti-UV mask 22 and 28 is only located on the corresponding semiconductor portion 24, 30. A protection of semiconductor portions 24, 30 is thus obtained while letting light through at the level of the areas of the CMOS circuit where there is no anti-UV protection. The surface area occupied by anti-UV masks is thus decreased to its minimum. The CMOS circuit may thus for example be used in applications requiring a transparency of the circuit, such as for example in an active matrix of a display; anti-UV masks 22, 28 are directly formed in contact with semiconductor layers 22 and 28, the CMOS circuit layers thus being stack in the semiconductor layers/anti-UV masks/dielectric layer order. It has indeed been observed that forming a stack having the semiconductor layers/dielectric layer/anti-UV masks order may result in a significant leakage current when the anti-UV masks are formed of a matrix having anti-UV particles dispersed therein. Indeed, the particles may form particle clusters having points which pierce the underlying dielectric layer on deposition of the anti-UV masks, thus resulting in a poor electric insulation between the gate and the semiconductor layers, and thus in a strong leakage current, or even in a short-circuit; the anti-UV masks also form the masks for the etching, which thus limits the number of CMOS circuit manufacturing steps.

(23) A method according to a second embodiment will now be described in relation with FIGS. 12 to 14.

(24) The first steps of the method according to the second embodiment are identical or similar to the first steps of the first embodiment described in relation with FIGS. 1 to 9, the thickness and the structure of anti-UV masks 22 and 28 being however likely to vary as described hereafter. The second mode thus has the advantages described hereabove in relation with the etching and the anti-UV protection during said etching.

(25) The method carries on with the removal of masks 22 and 28 (FIG. 12). Such a removal is performed by liquid etching with a solvent orthogonal to the active layers of the CMOS, that is, a solvent which is not capable of etching or dissolving them, such as cyclohexane or all fluorosolvents or by other techniques such as laser etching or plasma etching. Particularly, the selection of the material(s) for the above-described masks enables to easily remove these masks, while leaving substantially no residue on the semiconductor layers, the final quality of the circuit being thus substantially unaffected by the presence of a residue.

(26) Dielectric layer 32 is then deposited (FIG. 13) similarly to the step described in relation with FIG. 10, after which gates 34, 36 and contacting area 38 are formed similarly to the step described in relation with FIG. 11.

(27) The semiconductor material of portions 24, 30 is formed of molecules of small molecular mass, currently called small molecules, and particularly of molecules having a molecular mass smaller than 1,000 g/mol, or of polymers formed of macromolecules of larger molecular mass. These two types of organic semiconductors have the common point of having a conjugated system resulting from the alternation of simple and double carbon-carbon bonds, and thus of having a semiconductor effect.

(28) As an example of organic semiconductor materials of small molecular mass, materials of polyacene, oligo-thiophene, or phtalocyanine type may be mentioned.

(29) As an example of polymer organic semiconductor materials, materials of polyacetylene, polyphenylene, polythiophene, or poly(phenylene/vinylene) type may be mentioned.

(30) It may in particular be an organic semiconductor selected from the group comprising pentacene, tetracene, anthracene, naphthalene, alpha-6-thiophene, alpha-4-thiophene, perylene and its derivatives, rubrene and its derivatives, coronene and its derivatives, perylene tetracarboxylic diimide and its derivatives, perylene tetracarboxylic dianhydride and its derivatives, polythiophene and its derivatives, polyparaphenylene-vinylene and its derivatives, polyparaphenylene and its derivatives, polyfluorene and its derivatives, copolymer, polyfluorene-oligothiophene and its derivatives, polythiophene-vinylene and its derivatives, a heterocyclic aromatic copolymer of polythiophene and its derivatives, oligonaphthalene and its derivatives, alpha-5-thiophene oligothiophene and its derivatives, phthalocyanine that contains no metal and its derivatives, pyromellitic dianhydride and its derivatives, pyromellitic diimide and its derivatives, perylene tetracarboxylic acid dianhydride and its derivatives, perylene tetracarboxylic diimide and its derivatives, naphthalene tetracarboxylic diimide and its derivatives, or naphthalene dianhydride-tetracarboxylic acid and its derivatives.

(31) Advantageously, the P-type organic semiconductor material is selected from among pentacene, tetracene, and anthracene, modified TIPS pentacene, polythiophene, P3HT (poly(3-hexylthiophene)), PCDTBT (poly[N-9-heptadecanyl-2,7-carbazole-alt-5,5-(4,7-di-2-thienyl-2,1,3-benzothiadiazole]), and is preferably pentacene.

(32) Advantageously, the N-type organic semiconductor material is selected from among perylene diimide, fullerene, PCBM ([6,6]-phenyl-C.sub.61-methyl butyrate), PCNEPV (poly[oxa-1,4-phenylene-(1-cyano-1,2-vinylene)-(2-methoxy-5-(3,7-dimethyl-octyloxy)-1,4-phenylene)-1,2-(2-cyanovinylene)-1,4-phenylene]), and polyfluorene.

(33) Anti-UV masks 22, 30 are made of a composition comprising an organic matrix, in particular polymer, having particles which block UV radiation by absorption or reflection dispersed therein or deposited thereon. The matrix having the particles dispersed therein is for example deposited by a sol-gel technique, a vacuum deposition technique, a cathode sputtering technique, a spin coating technique, a knife coating technique, or the like.

(34) The organic matrix is advantageously made of a polymer which has no affinity with the semiconductor materials constitutive of the transistors and which accordingly does not deteriorate the latter. Further, in the context of the embodiment where masks 22, 30 are removed, the matrix is also selected to be easily removable by etching without inducing the etching of semiconductor portions 24, 30 on which they are deposited. To achieve this, the matrix of anti-UV masks 22, 30 is made of a fluorinated polymer, particularly CYTOP, which has no affinity with usual organic semiconductor materials, and which may be etched by a so-called orthogonal solvent, such as butyl acetate, ethyl acetate, or methyl acetate, which does not deteriorate organic semiconductor materials either.

(35) Other polymers are also possible, such as for example, vinyl polymers, particularly polystyrene, which may be etched by a solvent such as ethyl acetate.

(36) The particles blocking UV rays are ZnO, TiO.sub.2, and/or CeO.sub.2 particles. As a variation, or additionally, organic anti-UV pigments such as described in application FR 2955115 are dispersed in the organic matrix.

(37) Advantageously, organoclay particles are also dispersed in or deposited on the matrix, to extend the range of blocked UV rays. Organoclays indeed comprise pyrene and/or phenylhydroxybenzotriazole, which block UV rays up to a 400-nanometer wavelength. Organoclays have the advantage of minimizing electric defects, especially traps.

(38) Organoclays are for example described in application FR 2925518. A combination of ZnO particles and of organoclay particles thus enables to block UV rays in the 200-400 nanometer range. Organoclays are for example manufactured by following the operating mode described in application FR 2925359, the size of the obtained organoclay elements being of approximately 30 nanometers. These elements are flat, have an organic surface, and are dispersible up to 30% by mass in water or in organic solvents, such as an alcohol, a ketone, a chlorinated solvent, or a fluorinated solvent, such as for example perfluoro alkane/decane hexane, or perfluoro isobutene. The solution comprising the organoclays thus obtained is then filled with the organic anti-UV particles, for example, according to the operating mode described in application FR 2925359, after which a binder, for example acrylate, is added. The obtained composition is then for example spin coated or knife coated.

(39) Advantageously, the composition also comprises a material which blocks visible wavelengths, for example, a dye, particularly to protect the semiconductor materials during strong emissions in the visible range due to certain etch techniques used, particularly plasma etching.

(40) Advantageously, inorganic particles, for example, ZnO and/or pyrene particles, are added to the composition to shift the UV absorption spectrum.

(41) Advantageously, a polystyrene, a pyrene, or a derivative thereof, for example polystyrene latex and/or pyrene carboxylic acid, is added to the matrix, to inhibit a photocatalytic surface effect of the dispersed particles. Indeed, anti-UV organic particles are usually highly sensitive to oxidation with oxygen and ozone. Further, oxide particles may, under the effect of a photocatalysis, generate free radicals capable of reacting with the organic semiconductor materials and thus of degrading the latter. Thus, if the etching of the semiconductor material layers is postponed, with no specific measure, there is a risk of seeing the particles oxidize. Similarly, the use of a plasma, particularly during a plasma etching, frequently generates ozone, which may also degrade said particles. A derivative of pyrene or of polystyrene thus enables to prevent such a phenomenon. For example, a derivative of pyrene according to the following formulation, with n=1 to 4, may be used:

(42) ##STR00001##

(43) Advantageously, the particles dispersed in the matrix are coated with a silicon shell, which also enables to avoid a photocatalysis thereof. The silicon shell also enables to easily formulate the particles via the silane coupling agent chemistry. By encapsulating the particles, their stability in the mixture is increased and their integration is improved.

(44) Advantageously, the particles have their dimensions ranging from 1 nanometer to 200 nanometers, and preferably from 20 nanometers to 30 nanometers, and amount to from 35% to 55% of the mass of the anti-ultraviolet layer, which allows an easy deposition of the anti-UV layer. Limiting the particle size thus decreases the risk for clusters to form and thus the risk of areas containing no anti-UV particles, which would not protect the semiconductor materials. Further, by selecting such a mass percentage, the composition formed of the matrix and of the dispersed particles easily deposits in the form of a film and may further be easily removed.

(45) As a variation, a colloidal dispersion of ZnO is for example used, where ZnO amounts to 35% by mass and is dispersed in an organic solvent, for example, alcohol or ketone, where such as colloidal sol may be formulated with an organic binder, such as acrylate, for example, and deposited by spin or knife coating on the layer to be protected. Advantageously, ZnO nanoparticles in the form of disks having a diameter of at least 30 nanometers and a 20-nanometer thickness, such as those commercialized by EVONIK and BYK, are used. Disks have the advantage of self-arranging on the substrate to form continuous layers.

(46) The composition and/or the thickness of the anti-UV masks are advantageously selected according to the anti-UV protection type desired for the CMOS circuit.

(47) Particularly, when the CMOS circuit comprises in its final form anti-UV masks 22 and 30, the thickness thereof is selected to disturb as little as possible the transistor operation. Particularly, masks 22, 30 and dielectric layer 32 form together an insulating layer having the function of insulating the gate electrodes from the layers of semiconductor material. Preferably, the total thickness of insulating material between a gate electrode and the associated semiconductor material is smaller than 1 micrometer. Above this, a substantial degradation of the transistor performances can be observed.

(48) The mask thickness is further selected according to the quantity of UV rays capable of impacting anti-UV masks. Particularly, when a plasma etching is used for the manufacturing of transistors, the thickness of the masks is selected according to the power of the plasma. Advantageously, a fluorinated polymer layer having between 45% and 55% by mass of the ZnO particles dispersed therein, with a thickness in the range from 50 to 200 nanometers, enables to efficiently protect the UV radiation generated by plasma having a power lower than 10 watts. Similarly, a thickness greater than 200 nanometers enables to efficiently protect against a plasma power in the range from 10 watts to 50 watts, and a thickness greater than one micrometer enables to protect the semiconductor materials against plasma powers greater than 50 watts.

(49) When the anti-UV masks are removed, and are thus not part of the final CMOS circuit, the user has more degrees of liberty for the selection of the composition and of the thickness of said filters. The filter may thus have a thickness greater than 800 nanometers, or even greater than one micrometer, to guarantee a substantially total protection against UV rays generated by significant plasma powers.

(50) Of course, other types of etching may be used, for example, chemical etchings, to remove the excess semiconductor materials. When anti-UV masks aim at providing a protection against UV rays only, a thickness in the range from 100 nanometers to 200 nanometers provides an efficient protection.