LNA with programmable linearity

Abstract

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source input stage and a common gate output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Claims

1. An amplifier comprising: (a) a plurality of amplifier branches, at least one of which includes a driver field effect transistor (FET) having a drain, source and gate, and a corresponding cascode FET having a drain, source and gate, the drain of the driver FET coupled to the source of the corresponding cascode FET, the drain of each cascode FET coupled together; (b) a plurality of branch control switches, each branch control switch associated with one of the amplifier branches and coupled to the gate of the cascode FET within the corresponding amplifier branch; (c) a load inductance having a first and second terminal, the first terminal coupled to the drains of the cascode FETs and the second terminal coupled to a voltage supply; (d) an output capacitor having a first and second terminal, the first terminal coupled to the drains of the cascode FETs and the second terminal coupled to an amplifier output; (e) a plurality of gain control compensation capacitors, each having a first and second terminal, the first terminal of each gain control compensation capacitor coupled to the drains of the cascode FETs; (f) a plurality of gain control compensation switches, each gain control compensation switch corresponding to one of the plurality of gain control compensation capacitors and having a first and second terminal, the first terminal coupled to the second terminal of the corresponding gain control compensation capacitor and the second terminal of each of the gain control compensation switches coupled to the amplifier output to place the corresponding gain control compensation capacitor in parallel with an output capacitor when the corresponding gain control compensation switch is closed.

2. The amplifier of claim 1, further comprising a plurality of selectable gate to source compensation (GSC) capacitors, each GSC coupled between the gate and the source of a corresponding one of the driver FETs.

3. The amplifier of claim 2, further comprising a plurality of GSC switches, each coupled to a corresponding one of the plurality of GSC capacitors and associated with a corresponding one of the amplifier branches.

4. The amplifier of claim 3, wherein the amplifier has an input impedance and wherein turning on unique combinations of amplifier branches corresponds to unique gain modes and wherein combinations of the GSC capacitors are tuned to mitigate changes between the input impedance in each of the possible gain modes.

5. The amplifier of claim 3, further comprising a plurality of selectable degeneration capacitors coupled to the sources of the driver FETs.

6. The amplifier of claim 5, further comprising a plurality of degeneration switches, each degeneration switch coupled to a corresponding one of the degeneration capacitors.

7. The amplifier of claim 6, wherein the amplifier has an input impedance and wherein turning on unique combinations of amplifier branches corresponds to unique gain modes and wherein combinations of the degeneration capacitors are tuned to reduce input impedance variation between each of the possible gain modes.

8. The amplifier of claim 1, further including a plurality of output impedance compensation (OIC) capacitors, each of which can be placed in parallel with the load inductance.

9. The amplifier of claim 8, further including a plurality of OIC switches, each OIC switch associated with one of the OIC capacitors such that when closed the OIC switch places the OIC capacitor in parallel with the load inductance.

10. The amplifier of claim 9, wherein each of the OIC switches is associated with one of the amplifier branches, such that when a signal turns off the amplifier branch, the associated OIC switch is closed.

11. The amplifier of claim 10, wherein the capacitance of the OIC capacitor associated with the each OIC switch is selected such that closing the associated OIC switch improves the output impedance mismatch when the associated driver FET is turned off.

12. The amplifier of claim 3, wherein the GSC capacitors are post fabrication variable.

13. The amplifier of claim 12, wherein the GSC capacitors are laser trimmed after fabrication to adjust the capacitance to a desired capacitance after fabrication is complete.

Description

DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is an illustration of an LNA of a prior art communications receiver.

(2) FIG. 2 is an illustration of an LNA of a communications receiver capable of operating in several gain and current modes.

(3) FIG. 3 illustrates the LNA of FIG. 2, having a bank of input capacitors that can be selectively placed between a gate and a source of the common source FETs of the amplifier branches of the LNA.

(4) FIG. 4 is an illustration of the LNA of FIG. 3, the LNA additionally having a second bank of input capacitors selectively placed in parallel with a degeneration inductor.

(5) FIG. 5 is an illustration of the LNA of FIG. 4, additionally having compensation provided to ensure that the output impedance of the LNA remains constant in each gain mode.

(6) FIG. 6 is an illustration of the LNA of FIG. 5, additionally having a bank of gain control resistors and a bank of gain control compensation capacitors.

(7) FIG. 7 is an illustration of the LNA of FIG. 6, additionally having a bank of post fabrication variable capacitors selectively placed in parallel with the gate to source capacitance C.sub.GS of the three common source amplifiers

(8) FIG. 8 is a flowchart of a process used to make an LNA having capacitors tuned to values that account for variations in the parameters of components of the LNA during fabrication of the LNA.

(9) Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

(10) FIG. 2 is an illustration of an LNA 200 of one example of a communications receiver capable of operating in several gain modes. The LNA 200 comprises a plurality of amplifier branches 202, 204, 206, each branch having an amplifier. The inputs to each of the amplifier branches are coupled together. In some embodiments, a first FET 210 is configured as a common-source amplifier (i.e., driver) and a second FET 208 is configured as a common-gate amplifier (i.e., cascode). Alternatively, each amplifier branch can be configured as a single common source device or a stack of FET devices. In some embodiments, the branches include combinations of the above configurations. For the sake of simplicity, a cascode LNA is described in more detail below. However, it should be understood that the following description applies equally to other configurations of amplifier branches.

(11) In some embodiments, each branch 202, 204, 206 has a binary-weight . Accordingly, in some such embodiments, the width of the FETs 208, 210 in each branch 202, 204, 206 is proportional to the binary weight of that branch. Accordingly, in some such embodiments, the gain of each branch is also proportional to (i.e., each branch has a binary-weighted gain). In other embodiments, the relative weight of the branches may be distributed differently, such as in a thermometer weighting, geometric or logarithmic weighting, arbitrary weighting or other weighting scheme.

(12) In the case of a binary weighting scheme, the binary weight of each branch is 2.sup.i1/(2.sup.(n)1), where i is the branch number from 1 to n, and n is the total number of branches. In this example, the LNA 200 comprises a total of three branches 202, 204, 206. Therefore, the value of n is 3. The value of i for the first branch is 1. Therefore, the weight of the first branch is 2.sup.0/(2.sup.(3)1)=1/7. The value of i for the second branch is 2, thus the weight of the second branch is 2.sup.1/(2.sup.(3)1))=2/7. The value of i for the third branch is 3, thus the weight of the third branch is 2.sup.2/(2.sup.(3)1)=4/7. The number of branches will depend upon the granularity of weighting steps desired, as will be clear from the following description. In some embodiments, the gain of each branch 202, 204, 206 is proportional to the weight of that branch. In other embodiments, other parameters, such as current, noise contribution, delivered output power, linearity level, etc. could be the primary metric that is weighted.

(13) In some embodiments, the gain of each branch is set by establishing the width of the two FETs 208, 210 proportional to . That is, the width of the FET 210 of the first branch is 1/7.sup.th the width of the amplifier FET that would be needed to achieve the same gain in a conventional LNA that has just one such driver FET (i.e., one branch). Similarly, the width of the FET 208 of the first branch is 1/7.sup.th the width of a cascode amplifier FET that would be needed to achieve the same gain in a conventional LNA having just one such cascode FET.

(14) The width of the FET 210 of the second branch is 2/7.sup.th the width of the driver amplifier FET that would needed to achieve the same gain in a conventional LNA. It should be clear that the width of each other FET 208, 210 is proportional to the binary weight of the branch in which the FET 208, 210 resides.

(15) A pair of branch control switches 212, 214 associated with the first branch 202 controls the bias to the gate of the cascode FET 208 of that branch. A branch 1 switch control signal coupled to the switch 212 controls when the switch is to be opened and closed. For the sake of simplicity, only the switch 212 is shown having a branch switch control signals coupled thereto. However, each of the other branch control switches 214, 220, 222, 224, 226 is controlled by a corresponding switch control signal.

(16) By opening the switch 212 to a bias voltage source 216 and closing the switch 214 to ground, the bias is removed from the gate of a cascode FET 208. Accordingly, the drain current I.sub.d flowing through the branch is turned off, essentially removing that branch from operation and reducing the gain contribution of that branch to the overall gain of the LNA 200 to zero. Similarly, pair of switches 220, 222, 224, 226 associated with the other two branches, respectively, turns those branches on and off. In some embodiments, a gain control module produces branch switch control signals that are coupled to switches 212, 214, 220, 222, 224, 226 to allow the gain control module to turn each branch on or off, depending upon the amount of gain desired. The LNA can thus be operated in steps of 1/7.sup.th the maximum gain. That is, with only the first branch 202 turned on, the LNA 200 will operate at 1/7.sup.th maximum gain. With only the second branch turned on, the LNA 200 will operate at 2/7.sup.th maximum gain. With both the first and the second branch turned on, the LNA 200 will operate at 3/7.sup.th maximum. With only the third branch turned on, the LNA 200 will operate at 4/7.sup.th maximum gain, etc.

(17) Splitting the LNA 200 into several branches allows the bias current through each FET 208, 210 to remain constant at a bias current level at which the branch was designed to operate.

(18) When a branch 202, 204, 206 is turned OFF, its common-gate amplifier formed by the cascode (FET 208 for branch 202, for example) is turned OFF by grounding its gate. Thus, the FET 208 does not draw current. However, in some embodiments, the common-source amplifier formed by the cascode FET 210 is not OFF. Rather, that FET 210 is in triode mode, as its gate is still biased. Therefore, as the different branches are turned on and off, the input impedance of the LNA 200 may change. As noted above, this is undesirable. This is mitigated in some embodiments, in which the input impedance of the LNA 200 is maintained constant for different gain modes (i.e., with different combinations of branches being turned on).

(19) FIG. 3 is an illustration of one embodiment of an LNA 300 similar to the LNA 200 shown in FIG. 2. However, the LNA 300 shown in FIG. 3 comprises a bank of selectable gate-to-source compensation capacitors (GSC Caps) 302, 304, 306. Each GSC Cap 302, 304, 306 corresponds with one of the branches 202, 204, 206 of the LNA 200. Each GSC Cap 302, 304, 306 is coupled to a GSC Cap switch 308, 310, 312 to allow the GSC 302, 304, 306 Cap to be selected. The gate to source capacitance C.sub.gs within a FET changes depending on whether the FET is in the saturation mode or triode mode, thereby changing the input impedance of the LNA 300. In some embodiments, the capacitance of each of the GSC Caps 302, 304, 306 is set equal to the difference between the C.sub.gs of the FET 210 in saturation and the C.sub.gs of the FET 210 in triode mode. Combinations of the GCS Caps 302, 304, 306 are thus selected to mitigate changes in the input impedance in each of the possible gain modes. That is, the resulting change in the input reactance of the LNA 300 due to the change of the C.sub.gs of FETs 210 from saturation mode to triode mode can be mitigated (and essentially eliminated) by closing the GSC Cap switch 308, 310, 312 associated with those branches that are turned off.

(20) In some embodiments, each of the GSC Cap switches 308, 310, 312 are controlled by the gain control module 218, such that the GSC Cap switch 308, 310, 312 coupled to the GSC Cap 302, 304, 306 is closed when the corresponding branch 202, 204, 206 of the LNA 200 is turned off. The GSC Cap switch is then opened when the corresponding branch is turned on. Adding capacitance between the gate and the source of the driver FETs 202, 204, 206 of the LNA 300 compensates for the difference between the input impedance in each of the different operational modes.

(21) FIG. 4 illustrates an LNA 400 having a bank of degeneration capacitors 402, 404, 406. Similar to the first bank of capacitors 302, 304, 306, the bank of degeneration capacitors 402, 404, 406 are switched in and out of the circuit in coordination with the selection of the gain mode of the LNA 400. In some embodiments, the switching is controlled by a gain control module 218 as disclosed above. By closing the associated switches 408, 410, 412 one or more of the capacitors 402, 404, 406 are placed in parallel with the degeneration inductor 414. By changing the amount of capacitance in parallel with the degeneration inductor 414 as the LNA 400 changes gain modes, the total input impedance that is seen looking into the input of the LNA 400 can be adjusted so that the input impedance remains essentially constant for each gain mode. Accordingly, the degeneration capacitors 402, 404, 406 are tuned to keep the input impedance the same in each of the possible gain modes. Note that a first of the three switches 408 is associated with the switches 214, 220 associated with the first branch 202, as well as with a first of the three switches 308. Therefore, when the first branch is turned on, switches 308, 408 are opened. Likewise, when the second branch 204 is turned on, the switches 310, 410 are opened. Finally, when the third branch 206 is turned on, the switches 312, 412 are opened.

(22) FIG. 5 is an illustration of yet another embodiment of an LNA 500 in which compensation is provided to ensure that the output impedance of the LNA 500 remains constant in each gain mode. The LNA 500 has a load inductor 514 coupled between a voltage supply VDD and the drains of the common-gate FETs 208. The compensation for changes that would otherwise occur in the output impedance is provided by a third bank of output impedance compensation (OIC) capacitors 502, 504, 506 that can each be placed in parallel with the load inductor 514 by closing an associated switch 508, 510, 512. That is, when a branch 202, 204, 206 of the LNA is turned off, the output impedance decreases. This results in an output impedance mismatch. By providing additional capacitor in parallel with the load impedance 514 when a branch is turned off, the mismatch can be improved. Accordingly, each of the three switches 508, 510, 512 are associated with one of the three branches 202, 204, 206. When a branch 202, 204, 206 is turned off, the associated switch 508, 510, 512 is closed. As was the case in the LNAs 400, 300 discussed above, a gain control module 218 (not shown in FIG. 5 to simplify the figure) can be provided to control and coordinate the operation of the branches 202, 204, 206 and the switches.

(23) FIG. 6 is an illustration of yet another embodiment of an LNA 600 having a bank of gain control resistors 602, 604, 606. Each of the gain control resistor 602, 604, 606 is associated with a gain control switch 608, 610, 612 that places the associated gain control resistor 602, 604, 606 in parallel with the load inductor 514. By closing the switch 608, 610, 612 associated with each of the gain control resistors 602, 604, 606, the gain of the LNA 600 can be reduced, providing additional control over the gain of the LNA 600. Unlike the switches 408, 410, 412, 508, 510, 512 that are each associated with one of the branches 202, 204, 206, the gain control switches 608, 610, 612 can be operated independently to provide additional gain modes. However, the same gain control module 218 used to turn the branches on and off can provide additional control outputs that open and close the switches 608, 610, 612. Adding additional gain control resistor in parallel with the load inductor 514 will change the output impedance of the LNA 600. Accordingly, in some embodiments, an additional degree of freedom to alter the output impedance is provided by a bank of gain control compensation capacitors 616, 618, 620, each associated with a switch 622, 624, 626 that can place the associated capacitor in parallel with an output capacitor 628. The gain control compensation capacitors 616, 618, 620 are tuned to have values that will mitigate changes to the output impedance that would otherwise occur for each combination of gain control switches being opened or closed. Providing the gain control compensation capacitors 616, 618, 620 makes it possible to keep the output impedance essentially the same when different combinations of gain control resistors 602, 604, 606 are placed to be in parallel with the load inductor 514.

(24) FIG. 7 is an illustration of one more embodiment of an LNA 700 in which a bank of variable capacitors 702, 704, 706 are selectively placed in parallel with the gate to source capacitance C.sub.GS of the three common source amplifiers, such as FETs 210. In some embodiments, the capacitors 702, 704, 706 are post fabrication variable. That is, the amount of capacitance can be adjusted after fabrication of the other components of the amplifier branch 202, 204, 206. By making the value of these capacitors 702, 704, 706 variable, variations during fabrication that can affect parameters of interest of the LNA 700 (such as the IIP3, noise figure, input second order intercept (IIP2), output impedance, input impedance, etc.) can be compensated for after fabrication is complete. In some embodiments, the capacitors 702, 704, 706 are each Metal-Insulator-Metal (MIM) caps that can be laser trimmed to the desired capacitance after the LNA 700 has been fabricated. Alternatively, additional capacitors and associated switches can be provided to increase the range of capacitance that can be varied after fabrication with selectively coupling the additional capacitors through the additional switches. The capacitors 702, 704, 706 are shown in FIG. 7 as three variable capacitors. However, in some embodiments, each capacitor 702, 704, 706 may comprise a fixed capacitor in parallel with (or in series with) a MIM capacitor that can be laser trimmed to yield the desired total capacitance for each capacitor 702, 704, 706 shown or several additional capacitors and associated switches. In addition, the bias voltages V.sub.bias1, V.sub.bias2 and V.sub.bias3 applied to the gate of each of the three common gate amplifiers (such as FETs 208) are each generated using variable voltage sources 708, 710, 712.

(25) Throughout this disclosure, the terms resistor, capacitor and inductor have been used in the general sense to indicate an element that imposes resistance, capacitance and inductance, respectively. It should be understood that these terms can be interpreted to mean any element, either lumped or distributed, that can impose resistance, capacitance and inductance, respectively Likewise, the term switch has been used through the disclosure to mean any circuit element that can selectively impose either a relatively high impedance in a first state and a relatively low impedance in a second state. In some embodiments, these switches are FETs. However, any other element capable of switching from a relatively high impedance to a relatively low impedance can be used where practical.

(26) FIG. 8 is a flowchart of a process used to make an LNA 700 having capacitors 702, 704, 706 tuned to values that account for variations in the parameters of components of the LNA during fabrication of the LNA 700. The process begins with the fabrication of LNAs 700 including capacitors 702, 704, 706 that can be adjusted, such as by laser trimming a MIM capacitor, after fabrication (STEP 802). Once the LNAs 700 have been fabricated, at least one of the LNAs 700 is selected. For the selected LNA 700, initial values are set for capacitance for the three capacitors 702, 704, 706 and for the common gate (CG) bias voltage V.sub.bias1, V.sub.bias2 and V.sub.bias3 applied to each of the common gate FETs 208 and for the common source (CS) bias voltage V.sub.bias4 applied to the common source FETs 210 (STEP 804).

(27) Next, at least one LNA parameter of interest, such as the IIP3, noise figure, input second order intercept (IIP2), output impedance, input impedance, etc., are measured at the initial values of CG bias and CS bias for a first gain mode in which the first branch 202 is turned on and each of the other branches 204, 206 are turned off (STEP 806). If measurements have not been made at all of the CG bias voltages for which measurements are to be made (STEP 808), then the CG bias voltage for the branch that is currently turned on is adjusted to the next value (STEP 810). The parameters of interest are measured for that CG bias voltage (STEP 806). STEPs 806, 808 and 810 are repeated until the answer to the decision block in STEP 808 is YES (i.e., parameter measurements for all of the bias voltage levels have been made).

(28) Upon making measurements of the parameters of interest at each CG bias voltage level, a decision is made as to whether parameter measurements have been made for all of the CS bias voltage values (STEP 812). If not, then the CS bias voltage is set to the next level at which parameter measurements are to be made (STEP 814). The next measurement is made (STEP 806) and the process again repeats STEP 806 through STEP 814 until the answer to the decision block in STEP 812 is YES.

(29) Once the answer to the decision block in STEP 812 is YES, a determination is made as to whether parameter measurements for all of the branches 202, 204, 206 have been completed. If not, then the next branch is turned on and each of the other branches is turned off (STEP 818). Once the answer to the decision block in STEP 816 is YES, the parameter measurements are analyzed to determine the CS bias voltage and CG bias voltage that results in desired operational parameters of the components of the LNA 700 (STEP 820).

(30) The process performed in STEPs 802 through 820 are repeated for other LNAs 700 from the same fabrication lot (i.e., that were fabricated together and thus have the same operational characteristics), but with different values of capacitance for the capacitors 702, 704, 706. This process is repeated until parameters of interest for LNAs 700 having all desired values of capacitance for the post fabrication variable capacitors 702, 704, 706 have been measured (STEP 822). The parameter measurements are then analyzed to determine the amount of capacitance (e.g., the size) of the variable capacitors 702, 704, 706 necessary to compensate for any variations from the ideal operational parameters of the LNA 700. The value of each of the variable capacitors 702, 704, 706 for the remaining LNAs of the lot are then set (STEP 824). In some embodiments, the capacitors 702, 704, 706 are MIM capacitors that can be laser trimmed, as noted above. Therefore, the values are set by laser trimming each capacitor to the appropriate size indicated by the parameter measurements made in STEP 806.

(31) In some embodiments, the process of FIG. 8 is performed on samples taken from a lot of LNAs that were fabricated together (i.e., LNAs for which the components all have the same performance parameters). The MIM capacitor of each of the samples can be trimmed to different values and the process of FIG. 8 performed on each sample to determine which sample has the most desirable parameters of interest. In some embodiments, the MIM capacitor 702, 704, 706 of a first sample can be trimmed to a size that provides values of 20% of the impedance resulting from C.sub.gs of the common source FET 210. Other samples can have the capacitors 702, 704, 706 trimmed to other values, such as 30%, 40% or 0% of C.sub.gs. Once the measurements of STEP 806 are all completed for each sample, the sample having the best operational characteristics can be used as a model for determining the size of the capacitors 702, 704, 706. In some embodiments, the MIM capacitors of the remaining LNAs 700 that were fabricated together with the samples that were measured are trimmed to the same value as the LNA 700 having the best measurements for the particular application for which the LNA 700 is to be used. Alternatively, a new LNA 700 can be designed based on the measurements made on the samples and the process repeated using the new design and taking samples from the resulting LNAs 700.

Fabrication Technologies and Options

(32) As should be readily apparent to one of ordinary skill in the art, various embodiments of the disclosed apparatus can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice and various embodiments of the claimed invention may be implemented in any suitable IC technology (including but not limited to MOSFET and IGFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaN HEMT, GaAs pHEMT, and MESFET technologies. However, in some cases, the concepts claimed may be particularly useful with an SOI-based fabrication process (including SOS), and with fabrication processes having similar characteristics.

(33) A number of embodiments of the claimed invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the claimed invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion. It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the claimed invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims.