Optimal write method for a ferroelectric memory

Abstract

A method for programming a memory cell to a predetermined programmed state includesL (a) preparing the memory cell for a write operation; (b) sending a train of programming pulses, each programming pulse being a pulse having a magnitude sufficient to program the memory cell to the predetermined programmed state; (c) preparing the memory cell for a read operation; and (d) reading the programmed state of the memory cell to ascertain whether or not the predetermined programmed state is in the memory cell. In one embodiment, the method repeats steps (a)-(d), when the programmed state of the memory cell is not the predetermined programmed state. In one embodiment, the number of times steps (a)-(d) is repeated is determined based on both a probability of successfully writing the memory cell using a single write pulse and a probability of chaotic switching.

Claims

1. A method for programming a memory cell to a predetermined programmed state, comprises: (a) preparing the memory cell for an initial access write operation, wherein the preparing for the initial access write operation includes a write setup step; (b) sending a train of contiguous programming pulses during the initial access write operation, each programming pulse having a magnitude sufficient to program the memory cell to the predetermined programmed state; (c) preparing the memory cell for a read operation; (d) reading the programmed state of the memory cell to ascertain whether or not the predetermined programmed state is in the memory cell.

2. The method of claim 1, wherein steps (e) is carried out up to a predetermined number of times.

3. The method of claim 2, further comprising determining the predetermined number of times based on a probability of successfully writing the memory cell using a single write pulse.

4. The method of claim 2, further comprising determining the predetermined number of times based on both a probability of successfully writing the memory cell using a single write pulse and a probability of chaotic switching per write pulse.

5. The method of claim 1, wherein the memory cell comprises a ferroelectric memory element.

6. The method of claim 1, wherein the number of programming pulses in the train of programming pulses is selected to achieve a target probability of successful write of the memory cell within a target write latency.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows one example in the prior art, in which a write operation in an advanced memory technology, is followed by a verify operation.

(2) FIG. 2 shows a method for writing ferroelectric memory cells/ according to according to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(3) The present inventors observe that the number of retry write-verify cycles that are required to reach the >3 goal increases write latency, with the most time being taken up by the read and write setup times between the write pulses and the sensing operations. Therefore, the inventors devised an optimal write method to decrease the number of retry write-verity cycles and to decrease write latency. This method may be used with ferroelectric memory cells, such as shown in FIG. 2.

(4) FIG. 2 shows a method for writing ferroelectric memory cells, according to one embodiment of the present invention. Typically, the ferroelectric memory cells are organized as a conventional memory array. As shown in FIG. 2, under this method, in each write-verify cycle, instead of sending a single write pulse to write each target memory cell after each write set-up interval, multiple write pulses are sent. These additional pulses are sent before the programmed state of each target memory cell is read back to verify a successful write operation; accordingly, the pulses are referred herein as the blind pulses. If even after this modified write-verify operation some target memory cells in the memory array are found not to have been successfully written, the modified write-verify cycle may be repeated on these memory cells. Each write-verify cycle takes (t.sub.WS+m*t.sub.WP+t.sub.RS+t.sub.SEN) amount of time, where t.sub.WS, t.sub.WP, t.sub.RS and t.sub.SEN are the write setup time, a write-pulse duration, the read setup time, and the sensing duration, respectively, and where m is the number of blind pulses sent in each write-verify cycle.

(5) Using this approach, the number of retry write-verify cycles that are required to meet the goal of a 99.7% or greater probability of a successful write is the smallest integer N that satisfies the inequality: .sub.i=0.sup.N(1W).sup.iW.sup.m0.997, where m is the number of blind pulses and W is the probability of success per write pulse. Using a 50% probability of success per write pulse, the method using two blind pulses reduces the required number of retries from 8 to 4 write-verify cycles. Using four blind pulse reduces the required number of retries to two write-verify cycles. Furthermore, at a 50% probability of success per write pulse, the write latency for writing with two blind pulses is reduced from 3.76 s to 1.96 s and, for writing with four blind pulses, the write latency is further reduced to 1.06 s.

(6) The above calculation does not take into account the effects of chaotic switching. As mentioned above, chaotic switching is the phenomenon in advanced memory cells in which a write pulse, instead of writing an intended programmed state into the memory cell, writes an unintended programmed state (i.e., write failure). Chaotic switching reduces the effective probability of success per write pulse by turning a successfully achieved programmed state to an unintended programmed state.

(7) The number of retry write-verify cycles that are required to reach the goal of a 99.7% or greater write success can be determined using empirically obtained probabilities of success per write pulse and probabilities of chaotic switching. For example, using an a 50% probability of success per write pulse, and a 25% chaotic probability per write pulse, writing with 2 blind pulses, writing with 3 blind pulses or writing with 4 blind pulses, the method of the present invention still achieves a reduction of required retries from 8 write-verify cycles to 5 write-verify cycles. At the same time, the write latencies for writing with 2 blind pulses, 3 blind pulses and 4 blind pulses are 2.45 s, 2.55 s and 2.65 s, respectively. (By comparison, the single write pulse prior art method results in a 3.76 s write latency at a 50% probability of success per write pulse).

(8) The above detailed description is provided to illustrate specific embodiments of the present invention and is not to be taken as limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.