Method and apparatus for phase current balancing in multi-phase constant on-time buck converter

Abstract

A multi-phase DC-to-DC buck converter for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC buck converter cells. The converter includes a plurality of current sense circuits for sensing current in a respective converter cell, each of the current sense circuits configured to generate a respective current sense signal, an averaging circuit for receiving each of the respective current sense signals and generating an average signal, a plurality of imbalance detector circuits for comparing a respective current sense signal with the average signal and generating a respective current imbalance signal, and a plurality of ON time generators for activating a converter cell for a predetermined time interval and altering the predetermined time interval in accordance with a time integral of a respective current imbalance signal.

Claims

1. A multi-phase DC-to-DC buck converter for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC buck converter cells, the converter comprising: a plurality of current sense circuits each configured to sense current in a respective one of the plurality of converter cells, each of the plurality of current sense circuits configured to generate a respective current sense signal; an averaging circuit configured to receive each of the respective current sense signals and generate an average signal; a plurality of imbalance detector circuits each configured to compare a respective current sense signal with the average signal and generate a respective current imbalance signal; and a plurality of ON time generators each configured to activate a respective one of the plurality of converter cells for a predetermined time interval and to alter the predetermined time interval in accordance with a time integral of a respective current imbalance signal.

2. The converter of claim 1, wherein each of the plurality of ON time generators comprises: a source of predetermined current; a timing capacitor configured to integrate a sum of the predetermined current and a respective current imbalance signal and generate a ramp voltage; and a comparator for terminating the altered predetermined time interval upon the ramp voltage exceeding a threshold.

3. The converter of claim 2, wherein the predetermined current is substantially proportional to the input voltage.

4. The converter of claim 2, wherein the threshold is substantially proportional to the output voltage.

5. The converter of claim 2, further comprising a plurality of transconductor circuits, wherein each of the plurality of transconductor circuits is configured to transform a respective current imbalance signal to current.

6. The converter of claim 1, further comprising: a plurality of multiplier-divider circuits, wherein each of the plurality of multiplier-divider circuits is configured to multiply a respective current imbalance signal by a ratio of the input voltage and the output voltage, and to generate a normalized current imbalance signal, wherein a respective one of the plurality of ON time generators alters the predetermined time interval in accordance with a time integral of a respective normalized current imbalance signal.

7. The converter of claim 1, further comprising: a plurality of multiplier circuits, wherein each of the plurality of multiplier circuits is configured to multiply a respective current imbalance signal by a duty cycle of a respective one of the plurality of DC-to-DC buck converter cells and to generate a normalized current imbalance signal, wherein a respective one of the plurality of ON time generators alters the predetermined time interval in accordance with a time integral of a respective normalized current imbalance signal.

8. The converter of claim 6, wherein each of the plurality of multiplier-divider circuits includes a corresponding transconductor circuit, wherein each corresponding transconductor circuit is configured to transform a respective current imbalance signal to current.

9. A method in a multi-phase DC-to-DC buck converter for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC buck converter cells, the method comprising: sensing current in a respective one of the plurality of converter cells and generating a respective current sense signal; receiving each of the respective current sense signals and generating an average signal; comparing a respective current sense signal with the average signal and generating a respective current imbalance signal; and activating a respective one of the plurality of converter cells for a predetermined time interval and altering the predetermined time interval in accordance with a time integral of a respective current imbalance signal.

10. The method of claim 9, further comprising: integrating a sum of a predetermined current and a respective current imbalance signal and generating a ramp voltage; and terminating the altered predetermined time interval upon the ramp voltage exceeding a threshold.

11. The method of claim 10, wherein the predetermined current is substantially proportional to the input voltage.

12. The method of claim 10, wherein the threshold is substantially proportional to the output voltage.

13. The method of claim 10, further comprising transforming a respective current imbalance signal to current.

14. The method of claim 9, further comprising: multiplying a respective current imbalance signal by a ratio of the input voltage and the output voltage to generate a normalized current imbalance signal; and altering the predetermined time interval in accordance with a time integral of a respective normalized current imbalance signal.

15. The method of claim 9, further comprising: multiplying a respective current imbalance signal by a duty cycle of a respective one of the plurality of DC-to-DC buck converter cells to generate a normalized current imbalance signal; and altering the predetermined time interval in accordance with a time integral of a respective normalized current imbalance signal.

16. A multi-phase DC-to-DC buck converter for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC buck converter cells, the converter comprising: a plurality of current sense circuits each configured to sense current in a respective one of the plurality of converter cells, each of the plurality of current sense circuits configured to generate a respective current sense signal; an averaging circuit configured to receive each of the respective current sense signals and generate an average signal; a plurality of imbalance detector circuits each configured to compare a respective current sense signal with the average signal and generate a respective current imbalance signal; a plurality of transconductor circuits, wherein each of the plurality of transconductor circuits is configured to transform a respective current imbalance signal to current; a plurality of multiplier-divider circuits, wherein each of the plurality of multiplier-divider circuits is configured to multiply a respective current imbalance signal by a ratio of the input voltage and the output voltage, and to generate a normalized current imbalance signal; and a plurality of ON time generators each configured to activate a respective one of the plurality of converter cells for a predetermined time interval and to alter the predetermined time interval in accordance with a time integral of a respective normalized current imbalance signal; each of the ON time generators comprising: a source of predetermined current; a timing capacitor configured to integrate a sum of the predetermined current and a respective current imbalance signal and generate a ramp voltage; and a comparator for terminating the altered predetermined time interval upon the ramp voltage exceeding a threshold.

17. A multi-phase DC-to-DC buck converter for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC buck converter cells, the converter comprising: a plurality of current sense circuits each configured to sense current in a respective one of the plurality of converter cells, each of the plurality of current sense circuits configured to generate a respective current sense signal; an averaging circuit configured to receive each of the respective current sense signals and generate an average signal; a plurality of imbalance detector circuits each configured to compare a respective current sense signal with the average signal and generate a respective current imbalance signal; a plurality of transconductor circuits, wherein each of the plurality of transconductor circuits is configured to transform a respective current imbalance signal to current; a plurality of multiplier circuits, wherein each of the plurality of multiplier circuits is configured to multiply a respective current imbalance signal by a duty cycle of a respective one of the plurality of DC-to-DC buck converter cells, and to generate a normalized current imbalance signal; and a plurality of ON time generators each configured to activate a respective one of the plurality of converter cells for a predetermined time interval and to alter the predetermined time interval in accordance with a time integral of a respective normalized current imbalance signal; each of the ON time generators comprising: a source of predetermined current; a timing capacitor configured to integrate a sum of the predetermined current and a respective current imbalance signal and generate a ramp voltage; and a comparator for terminating the altered predetermined time interval upon the ramp voltage exceeding a threshold.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) A more complete understanding of the present embodiments, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

(2) FIG. 1 is a circuit diagram of a prior art multi-phase DC-to-DC buck converter;

(3) FIG. 2 is a circuit diagram of a multi-phase DC-to-DC buck converter in accordance with the principles of the present disclosure;

(4) FIG. 3 is a COT controller of the present disclosure comprising a multiplier-divider circuit configured to normalize the current balancing loop gain of the multi-phase buck converter;

(5) FIG. 4 is an alternate embodiment of the multiplier-divider circuit of the present disclosure configured to normalize the current balancing loop gain of the multi-phase buck converter; and

(6) FIG. 5 is yet another embodiment of the present disclosure where a multiplier circuit is configured to normalize the current balancing loop gain of the multi-phase buck converter.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

(7) FIG. 2 illustrates an exemplary embodiment of the multi-phase DC-to-DC COT buck converter of the present disclosure. Buck converter of FIG. 2 is configured to receive an input voltage V.sub.IN and deliver an output voltage V.sub.O to a load 12 by splitting the load current between a plurality of DC-to-DC buck converter cells 11. In this embodiment, the buck converter includes a multi-phase COT controller 10. The COT controller 10 includes current sense circuits 101, each of which monitors the inductor current of each of N converter cells 11, IL.sub.1IL.sub.N. Each of the current sense circuits 101 is configured to generate a respective current sense signal, V.sub.CS1V.sub.CSN. The COT controller 10 further includes an averaging circuit 102 configured to receive the current sense signals V.sub.CS1V.sub.CSN and generate an average signal V.sub.CS(AV). The COT controller 10 further includes current imbalance detector circuits 105 each configured to compare a respective current sense signal V.sub.CS1V.sub.CSN with the average signal V.sub.CS(AV) and generate a respective current imbalance signal V.sub.CS1V.sub.CSN.

(8) The COT controller 10 also includes ON time generators 107, each configured to activate a respective one of converter cells 11 for a fixed ON time and to alter the fixed ON time in accordance with a time integral of a respective current imbalance signal V.sub.CS1V.sub.CSN. In one embodiment, each of the ON time generators 107 includes a source of fixed current, a timing capacitor C.sub.T configured to integrate a sum of the fixed current and a respective current imbalance signal V.sub.CS1V.sub.CSN and to generate a PWM ramp voltage, and a comparator 109 for terminating the altered fixed ON time upon the ramp voltage exceeding a given threshold voltage, e.g., V.sub.O(est). In one embodiment, the fixed current is substantially proportional to the input voltage V.sub.IN. In another embodiment, the threshold is substantially proportional to the output voltage V.sub.O.

(9) In one embodiment, as shown in FIG. 2, as an improvement to the prior art COT converter of FIG. 1, the current imbalance signal, V.sub.CS1V.sub.CSN, is converted to current, I.sub.err1I.sub.errN, using transconductor circuits 108, and summed with the fixed current of the ON time generator 107 at its timing capacitor C.sub.T. Advantageously, integration of current I.sub.err1I.sub.errN negates the effect of the ripple current component, and the filters 103 shown in the prior art converter of FIG. 1 can be eliminated, resulting in an improved load transient response.

(10) The current imbalance signal, V.sub.CS1V.sub.CSN, is integrated at the capacitor C.sub.T over the ON time interval only, rather than being integrated over the entire switching cycle. Therefore, in one embodiment, the current balancing loop of the converter shown in FIG. 2 may require normalization of the loop gain with respect to V.sub.IN and V.sub.O.

(11) FIG. 3 illustrates an exemplary embodiment of a COT controller 10 of the present disclosure in accordance with this requirement. The COT controller 10 shown in FIG. 3 additionally includes a multiplier-divider circuit 100 normalizing the current balancing loop gain of the multi-phase DC-DC COT buck converter. The resulting gain of the current balancing loop is invariant with respect to V.sub.IN and V.sub.O.

(12) Thus, in this embodiment, the COT controller 10 of the present disclosure may include multiplier-divider circuits 100, wherein each of the multiplier-divider circuits 100 is configured to multiply a respective current imbalance signal, i.e., V.sub.CS1V.sub.CSN by a ratio of the input voltage and the output voltage, and to generate a normalized current imbalance signal. Thus, each one of the ON time generators 107 alters the fixed ON time in accordance with a time integral of a respective normalized current imbalance signal.

(13) In FIG. 4, an alternate embodiment of the multiplier-divider circuit 100 of FIG. 3 is illustrated. In this embodiment, multiplier-divider circuit 100 and transconductor 108 are combined into one element, i.e. a variable-gain transconductor 110.

(14) In FIG. 5, in another embodiment, a multiplier circuit 120 is configured to multiply a respective current imbalance signal by a duty cycle d of a respective DC-to-DC buck converter cell 11 and to generate a normalized current imbalance signal. Thus, each ON time generator 107 alters the predetermined time interval in accordance with a time integral of a respective normalized current imbalance signal as generated by multiplier circuit 120. As in the embodiment shown in FIG. 4 with respect to multiplier-divider circuit 110, multiplier circuit 120 is a variable gain transconductor.

(15) Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, all embodiments can be combined in any way and/or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.

(16) It will be appreciated by persons skilled in the art that the embodiments described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings.