METHOD FOR PROGRAMMING AN ARRAY OF RESISTIVE MEMORY CELLS

Abstract

A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.

Claims

1. A method for programming at least one resistive memory cell of an array of resistive memory cells, said method comprising a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle comprising a set step and a reset step, each set step comprising application of a set technique chosen among a plurality of set techniques, wherein each resistive memory cell comprises a resistive memory element and a selection transistor connected in series with the resistive memory element and wherein the plurality of set techniques comprises: full reprogramming: said full reprogramming comprising applying at least on reprogramming cycles, each reprogramming cycle comprising a reset operation followed by a set operation followed by a read and verify operation; and verify Set V.sub.TE: said verify Set V.sub.TE comprises applying voltage pulses with increasing positive amplitudes on a top electrode of the resistive memory element; and verify Set V.sub.G: said verify Set V.sub.G comprises applying voltage pulses with increasing positive amplitudes on a gate of the selection transistor; said method comprising the following steps: acquiring a bit error ratio value corresponding to each programming cycle for each set technique of said plurality of set techniques; at each programming cycle, applying the set technique having a lowest bit error ratio value corresponding to said programming cycle.

2. The method according to claim 1, wherein the plurality of set techniques are algorithms comprising set operation, and reset operations, and read and verify operations.

3. The method according to claim 1, wherein the bit error ratio value corresponding to each programming cycle for each set technique is measured prior to the programming cycles by characterizing a reference array of resistive memory cells and a sequence of the set techniques to be applied during the programming cycles is then defined.

4. The method according to claim 1, wherein the bit error ratio value corresponding to each programming cycle for each set technique is acquired from a database.

5. The method according to claim 4, wherein the bit error ratio value corresponding to each programming cycle for each set technique is measured prior to the programming cycles by characterizing a reference array of resistive memory cells and then stored in the database.

6. An electronic circuit comprising an array of resistive memory cells and a system for implementing the programming method according to claim 1, wherein each resistive memory cell comprises a resistive memory element and a selection transistor connected in series with the resistive memory element, said system comprising: a power source configured to generate voltage pulses; an addressing circuit configured to apply the voltage pulses: to the top electrode of at least a memory resistive element of the array of resistive memory cells; and to the gate of the selection transistor; and a controller configured to send control signals to the power source so that it generates the voltage pulses corresponding to the set techniques having the lowest bit error rate.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0024] Other characteristics and benefits of the invention will become clear from the description that is given thereof below, by way of indication and in no way limiting, with reference to the appended figures, among which:

[0025] FIG. 1 represents the distribution of the resistance values for an array of resistive memory cells at different programming cycles;

[0026] FIG. 2 is a flowchart of a method for programming at least one resistive memory cell, according to an aspect of the invention;

[0027] FIG. 3 schematically represents a resistive memory cell switching between a high resistance state (HRS) and a low resistance state (LRS);

[0028] FIG. 4 is a timing diagram of a set technique comprising the application of voltage pulses of increasing amplitude;

[0029] FIG. 5 is an abacus representing the bit error ratio of a reference array as a function of the number of programming cycles of the reference array, for various set techniques used during the set step of the programming cycles;

[0030] FIG. 6 represents, as a function of the number of programming cycles of the reference array, the capability of correcting the hard fails for the same set techniques;

[0031] FIG. 7 represents the distribution of the LRS resistance values of the reference array, after hundred programming cycles and for the same set techniques used during the set step of the programming cycles.

[0032] For greater clarity, identical or similar elements are marked by identical reference signs in all of the figures.

DETAILED DESCRIPTION

[0033] FIG. 2 schematically represents a method 200 for programming an array of resistive memory cells. An array of resistive memory cells comprises a plurality of resistive memory cells arranged in lines and in columns.

[0034] As shown on FIG. 3, each resistive memory cell of the array comprises a resistive memory element 10 and a selection transistor 20 connected in series with the resistive memory element 10.

[0035] The resistive memory element 10 can switch in a reversible manner between a high resistance state called “HRS” (or OFF state) and a low resistance state called “LRS” (or ON state). These two resistance states make it possible to store an information bit in each memory cell.

[0036] The resistive memory element 10 comprises a dielectric material layer 11 arranged between two electrodes: [0037] a first electrode 12a referred to as “bottom electrode”, on which is arranged the dielectric material layer 11; and [0038] a second electrode 12b referred to as “top electrode” and arranged on the dielectric material layer 11.

[0039] The dielectric material layer 11 may also be called “resistive material layer” (since the dielectric material has a variable electrical resistance).

[0040] The resistive memory element 10 is desirably a filament-type memory element, that is a memory element wherein the change of resistance state is governed by the formation and the removal of a conductive filament 14 between the two electrodes 12a-12b.

[0041] The resistive memory element 10 may be an OxRAM (Oxide-based Random Access Memory) element. The resistive material is then an oxide, for example a transition metal oxide (e.g. HfO.sub.2, Ta.sub.2O.sub.5, TiO.sub.2 . . . ) or a silicon oxide (SiO.sub.x, with x comprised between 1 and 2). The electrodes 12a-12b are electrically conductive layers and may be formed from one or more conductive materials such as titanium, titanium nitride, doped silicon, tungsten, tungsten nitride, metal silicides and platinum.

[0042] Alternatively, the resistive memory element 10 may be a CBRAM (Conductive-Bridging Random Access Memory) element. The resistive material is then an ionic conductive and electrically insulating material. One of the electrodes (the cathode) is made of an inert material and the other electrode (the anode) is made of a soluble material.

[0043] The resistive memory element 10 may also be a PCRAM (Phase-Change Random Access Memory) or a FeRAM (Ferroelectric Random Access Memory) element.

[0044] The memory cells of the array may be subjected, individually or collectively, to programming operations. The programming operations consist in switching the resistive memory element 10 between the high resistive state (HRS) and the low resistive state (LRS). When the resistive memory element 10 changes from the HRS to the LRS, the corresponding programming operation is referred to as a writing or set operation. Conversely, when the resistive memory element 10 changes from the LRS to the HRS, the corresponding programming operation is referred to as an erasing or reset operation. A programming operation can therefore be either a set operation or a reset operation.

[0045] The resistive memory element 10 is placed in the HRS when its electrical resistance value is higher than a first resistance threshold R.sub.TH_HRS and in the LRS when its electrical resistance value is lower than a second resistance threshold R.sub.TH_LRS. The second resistance threshold R.sub.TH_LRS is lower than or equal to the first resistance threshold R.sub.TH_HRS. The ratio between the first and second resistance thresholds is called the “programming window” (PW) of the memory cell:

[00001]$\mathrm{PW}=\frac{R_{T{H}_{-}\mathrm{HRS}}}{R_{T{H}_{-}LRS}}$

[0046] It is desirable that the second resistance threshold R.sub.TH_LRS is strictly lower than the first resistance threshold R.sub.TH_HRS (in other words, one resistance threshold per state) in order to have well separated resistance states (for improved reliability).

[0047] A memory cell of the array may also be subjected to reading operations. A reading operation consists in measuring the electrical resistance of the resistive memory element 10 in order to determine its resistance state.

[0048] The selection transistor 20 serves to bias the resistive memory element 10 so as to program or read the memory cell, and also acts as a current limiter during the set operation so as not to degrade the resistive memory element 10. The drain of the selection transistor 20 is connected to the bottom electrode 12a of the resistive memory element 10.

[0049] To perform a set, a reset or a read operation, a first voltage V.sub.TE is applied to the top electrode 12b of the resistive memory element 10, a second voltage V.sub.G is applied to the gate of the selection transistor 20 and a third voltage V.sub.S is applied to the source of the selection transistor 20. Values of the top electrode voltage V.sub.TE, of the gate voltage V.sub.G and of the source voltage V.sub.S depend on the operation to be performed and on the resistive memory technology (type of the resistive memory element, materials and thicknesses of the dielectric layer and of the electrodes).

[0050] With reference to FIG. 2, the programming method 200 comprises applying a sequence of N programming cycle C.sub.j to one or more memory cells of the array, N being an integer greater than or equal to 2. An index j, ranging from 1 to N, is used to number the programming cycles of the sequence.

[0051] Each programming cycle comprises a step SET.sub.j of setting the memory cell(s) and a step RST of resetting the memory cell(s). The reset steps RST of the sequence may be a conventional reset operation, i.e. the application of one negative voltage pulse between the electrodes 12a-12b of the resistive memory element 10 (V.sub.TE−V.sub.S<0). The set steps SET.sub.j of the sequence are not performed by simply applying one positive voltage pulse between the electrodes 12a-12b. Each set step SET.sub.j of the sequence comprises the application of a particular set technique. The set steps SET.sub.j are thus optimized set operation.

[0052] The set technique applied at the set step SETj of each programming cycle C.sub.j is chosen among a plurality of set techniques. In an embodiment of the programming method 200, the plurality of set techniques comprises: [0053] Full reprogramming; [0054] Verify Set V.sub.TE: applying voltage pulses with increasing amplitudes on the top electrode 12b of the resistive memory element 10 (the gate voltage V.sub.G and the source voltage V.sub.S being the same at each pulse); and [0055] Verify Set V.sub.G: applying voltage pulses with increasing amplitudes on the gate of the selection transistor 20 (the top electrode voltage V.sub.TE and the source voltage V.sub.S being the same at each pulse), which is equivalent to increasing the compliance current of the memory cell.

[0056] These set techniques are algorithms comprising set operations, reset operations and read and verify (R&V) operations (such algorithms are referred to as R&V algorithms).

[0057] The full reprogramming set technique comprises applying one or more reprogramming cycles, each reprogramming cycle comprising a reset operation followed by a set operation and a R&V operation. During a R&V operation, the electrical resistance of the cell is measured and compared to the second resistance threshold R.sub.TH_LRS. If the electrical resistance of the cell is lower than the second resistance threshold R.sub.TH_LRS, the ongoing reprogramming cycle has succeeded, and the algorithm is ended. If the electrical resistance of the cell is higher than the second resistance threshold R.sub.TH_LRS, the ongoing reprogramming cycle has failed, and a new reprogramming cycle is performed. The algorithm continues so on until a maximum number of reprogramming cycles is reached (for example 5 reprogramming cycles).

[0058] Identical reset conditions are applied during the different reset operations of the reprogramming cycles and identical set conditions are applied during the different set operations of the reprogramming cycles reprogramming cycles. The set and reset conditions are the amplitude and the duration of the voltage pulses applied between the electrodes 12a-12b of the resistive memory element 10 and to the gate of the selection transistor 20. These set and reset conditions are, in an embodiment, standard. For example, for an OxRAM element 10 comprising a bottom electrode 12a made of TiN, a dielectric material layer 11 made of SiO.sub.x and a top electrode 12b made of Ti, the top electrode voltage V.sub.TE may be 0 V during each reset operation and 2.8 V during each set operation, the gate voltage V.sub.G may be 4.5 V during each reset operation and 2.5 V during each set operation, the source voltage V.sub.S may be 1.8 V during each reset operation and 0 V during each set operation. The duration of the voltage pulses applied between the electrodes and to the gate of the selection transistor 20 is 1 μs during the reset operations and 100 ns during the set operations.

[0059] FIG. 4 is a diagram showing an embodiment of the second set technique “Verify Set V.sub.TE” (R&V algorithm increasing the top electrode voltage V.sub.TE). This second R&V algorithm comprises a first set operation, wherein a first top electrode voltage V.sub.TE1 is applied to the memory cell(s) to be programmed, and a first R&V operation after the first set operation. If the electrical resistance of the cell is lower than the second resistance threshold R.sub.TH_LRS, the first set operation has succeeded, and the algorithm is ended. If the electrical resistance of the cell is higher than the second resistance threshold R.sub.TH_LRS, the first set operation has failed, and a reset operation and a new set operation are successively performed. A higher top electrode voltage V.sub.TE2 (V.sub.TE2>V.sub.TE1) is applied during the new set operation. Then, a new R&V operation is performed. The algorithm continues so on until a maximum top electrode voltage is reached or until a maximum number of set operations is performed.

[0060] In other words, the second set technique “Verify Set V.sub.TE” comprises a first set operation, a first R&V operation and at least one sequence of the reset, set and R&V operations.

[0061] The top electrode voltage V.sub.TE (during the set operations) is, in an embodiment, increased by steps, according to a staircase. The top electrode voltage V.sub.TE starts at a first nominal value and is increased by a first step voltage until it reaches a first end value. The first nominal value (or start value of the V.sub.TE staircase) may be comprised between 2.5 V and 2.9 V, the first end value (end value of the V.sub.TE staircase) may be comprised between 3.2 V and 3.5 V and the first step voltage may be comprised between 0.05 mV and 0.2 V.

[0062] The third set technique “Verify Set V.sub.G” may also be, in an embodiment, an algorithm comprising a first set operation, a first R&V operation and at least one sequence of the reset, set and R&V operations. This third algorithm is thus the same as shown on FIG. 4, except that the voltage to be increased during the set operations is the gate voltage V.sub.G.

[0063] The gate voltage V.sub.G is, in an embodiment, increased by steps, according to a staircase. The gate voltage V.sub.G starts at a second nominal value and is increased by a second step voltage until it reaches a second end value. The second nominal value (or start value of the V.sub.G staircase) may be comprised between 2.0 V and 2.5 V, the second end value (or end value of the V.sub.G staircase) may be comprised between 2.9 V and 3.2 V and the second step voltage may be comprised between 100 mV and 200 mV.

[0064] The maximum number of set operations in the second and third R&V algorithms may be comprised between 5 and 10.

[0065] The voltage pulse duration during the different set operations of the R&V algorithms is, in an embodiment, constant, for example equal to 100 ns. The voltage pulse amplitude and the voltage pulse duration during the different reset operations of the algorithms are also, in an embodiment, constant, for example respectively equal to 4.5 V and 1 μs.

[0066] When the set techniques described above are applied to several memory cells (for example a block of the array to be programmed), most of the cells will receive just one set pulse, because their electrical resistance is good after the first pulse they receive. Only a few cells with receive more than one set pulse (and one or more reset pulses).

[0067] The set technique to be used at each programming cycle C.sub.j is selected based on bit error ratio (BER) values corresponding to the programming cycle C.sub.j. The bit error ratio (BER) is the arithmetic mean of the number of memory cells not actually being placed in the LRS after a set operation and the number of memory cells not actually being placed in the HRS after a reset operation following or preceding the set operation.

[0068] A bit error ratio value corresponding to the programming cycle C.sub.j is thus acquired for each of the set techniques.

[0069] In an embodiment, the BER values may be acquired from a database by a controller coupled to the array of resistive memory cells. They are then compared and the set technique having the lowest BER value corresponding to the programming cycle C.sub.j is to applied.

[0070] FIG. 5 shows an example of BER values that may be stored in the database. This figure represents, as a function of the number of programming cycles, the relative BER of the three set techniques described previously. The relative BER of a given set technique is the BER of the technique normalized with respect to the BER obtained when a normal cycling of the cell is performed (standard set and reset operations, no optimized set operation). Thus, it can be seen the benefits in terms of error correction of the three set techniques with respect to a normal cycling.

[0071] In this example, the third set technique “Verify Set V.sub.G” (increasing the gate voltage V.sub.G) has the lowest (relative) BER values in the first cycles. It is then chosen as the set technique to be applied during the first programming cycles C.sub.j of the array (see for example SETT on FIG. 5). Then, after approximatively ten cycles, the second set technique “Verify Set V.sub.TE” (increasing the top electrode voltage V.sub.TE) become more effective. It is then chosen as the set technique to be applied during the following programming cycles Cj (see for example SET.sub.15). Then, between (approximatively) the 20.sup.th cycle and the 400.sup.th cycle, the full reprogramming technique has the lowest BER value and is selected (see for example SET.sub.100).

[0072] The different BER values for the different set techniques and at each programming cycle are measured during a preliminary characterizing step (prior to the programming cycles) and then stored in the database. A reference array of resistive memory cells (of the same resistive memory technology than the array to be programmed) is subjected to a high number of programming cycles (for example more than 10.sup.4), each programming cycles comprising a reset step and a set step according to the considered set technique, as indicated above. The BER is calculated at each programming cycle, by measuring and averaging the number of LRS fails (i.e. the number of memory cells of the reference array not actually being placed in the LRS after the set step) and the HRS fails (the number of memory cells not actually being placed in the HRS after the reset step).

[0073] In another embodiment, the different BER values for the different set techniques and at each programming cycle are measured prior to the programming cycles during the characterizing step, then the sequence of the set techniques to be applied during the programming cycles is defined (based on the lowest BER values). The sequence may be stored in the controller (coupled to the array of resistive memory cells) or in a database in communication with the controller.

[0074] FIG. 6 show the percentage of the memory cells of the reference array in a hard fail situation, as a function of the number of programming cycles. It is considered that a memory cell of the reference array is in a hard fail situation when its LRS resistance value (i.e. the electrical resistance after a set step) exceeds a threshold (much) higher than the second resistance threshold R.sub.TH_LRS, for example equal to 10*R.sub.TH_LRS.

[0075] This figure shows that the second set technique “Verify Set V.sub.TE” is the fastest method to correct the hard fails (for this reference array, almost all hard fails are corrected after ten programming cycles). The second set technique “Verify Set V.sub.TE” is then an effective method for setting memory cells that have been deeply reset (memory cells that have a wide conductive filament).

[0076] FIG. 7 show the effects of the different set techniques on the distribution of the LRS resistance values, after 100 programming cycles of the reference array. This figure shows that the third set technique “Verify Set V.sub.G” has a more pronounced effect of shifting the resistance distribution towards to low resistance values. Thanks to this technique, a significant amount of memory cells having a resistance slightly higher than the second resistance threshold R.sub.TH_LRS, here equal to 10.sup.4Ω, are corrected (at the 100.sup.th programming cycles). It can be also seen the effect of the second set technique “Verify Set V.sub.TE” on the high resistance tail of the LRS resistance distribution.

[0077] The programming method according to the invention optimally combine several set techniques having different effect on the behavior of the memory cells (in particular on the formation of the conductive filament) to improve the LRS resistance distribution and improve the bit error ratio of the array.

[0078] The plurality of set techniques may comprise other set techniques than those described above, for example applying pulses with increasing duration to the top electrode of the resistive memory element. The second and third set techniques (Verify Set V.sub.TE and Verify Set V.sub.G) may comprise another sequence of the set, reset and R&V operations. For example, a R&V operation may also follow each reset operation.

[0079] Another aspect of the invention relates to an electronic circuit comprising an array of resistive memory cells (OxRAM, CBRAM, PCRAM, FeRAM) and a system for implementing the programming method of FIG. 2. The system for implementing the programming may include one or more electronic circuits.

[0080] In an embodiment, the electronic circuit comprises: [0081] a power source configured to generate voltage pulses; [0082] an addressing circuit configured to apply the voltage pulses to the top electrode 12b of the memory resistive element, to the source of the selection transistor 20 and to the gate of the selection transistor 20; [0083] a non-volatile memory storing bit error ratio (BER) values corresponding to the different set techniques; and [0084] a controller configured (or programed) to retrieve from the memory the BER values corresponding to the different set techniques, to compare the bit error ratio values at each programming cycle, to determine the set techniques having the lowest BER and to send control signals to the power source so that it generates the voltage pulses corresponding to the set techniques having the lowest BER.

[0085] In an alternative embodiment, the electronic circuit comprises: [0086] a power source configured to generate voltage pulses; [0087] an addressing circuit configured to apply the voltage pulses to the top electrode 12b of the memory resistive element, to the source of the selection transistor 20 and to the gate of the selection transistor 20; [0088] a controller configured (or programed) to send control signals to the power source so that it generates the voltage pulses in accordance with a sequence of the set techniques.

[0089] The sequence of the set techniques may be stored in a non-volatile memory.

[0090] The power source may comprise one or more voltage generators, in an embodiment at least one variable voltage generator capable of generating pulses of increasing amplitude.

[0091] The addressing circuit may comprise multiplexers, bit lines (connected to top electrodes 12b of the resistive memory elements 10 of the array), word lines (connected to the gate of the selection transistors 20 of the array) and, in an embodiment, source lines (connected to the source of the selection transistors 20).

[0092] The non-volatile memory is for example a read-only memory (ROM) or a Flash memory. It may be internal or external to the controller.