VOLTAGE MULTIPLIER CIRCUIT

Abstract

In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.

Claims

1. A voltage multiplier circuit comprising: a first input node and a second input node configured to be coupled to a voltage source to receive an input voltage therebetween; a first output node and a second output node configured to be coupled to an output capacitor to produce an output voltage across the output capacitor; a first input control node configured to receive a first clock signal and a second input control node configured to receive a second clock signal, the second clock signal being in phase opposition to the first clock signal, wherein the voltage multiplier circuit switches between a first commutation state and a second commutation state as a function of the values of the first clock signal and the second clock signal; an ordered sequence of intermediate voltage nodes arranged between the first input node and the first output node, the ordered sequence comprising a first ordered sub-sequence of intermediate voltage nodes and a second ordered sub-sequence of intermediate voltage nodes; a respective capacitor coupled between each odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the first input control node, wherein a first intermediate voltage node in the first ordered sub-sequence is configured to be selectively couplable to the first input node; a respective capacitor coupled between each even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the second input control node; a respective capacitor coupled between each odd-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence; a respective capacitor coupled between each even-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence; and a first plurality of selectively conductive electronic components coupled to the intermediate voltage nodes of the ordered sequence, wherein: in the first commutation state of the voltage multiplier circuit, the first plurality of selectively conductive electronic components is configured to provide electrically-conductive paths between each of the even-numbered intermediate voltage nodes of the ordered sequence and a respective next odd-numbered intermediate voltage node of the ordered sequence, an electrically-conductive path between the first input node and the first intermediate voltage node of the ordered sequence, and an electrically-conductive path between a last intermediate voltage node of the ordered sequence and the first output node, and in the second commutation state of the voltage multiplier circuit, the first plurality of selectively conductive electronic components is configured to provide electrically-conductive paths between each of the odd-numbered intermediate voltage nodes of the ordered sequence and a respective next even-numbered intermediate voltage node of the ordered sequence.

2. The voltage multiplier circuit of claim 1, further comprising: a further ordered sequence of intermediate voltage nodes arranged between the first input node and the first output node, the further ordered sequence comprising a respective first ordered sub-sequence of intermediate voltage nodes and a respective second ordered sub-sequence of intermediate voltage nodes; a respective capacitor coupled between each odd-numbered intermediate voltage node in the first ordered sub-sequence of the further ordered sequence and the second input control node, wherein a first intermediate voltage node in the first ordered sub-sequence of the further ordered sequence is configured to be selectively couplable to the first input node; a respective capacitor coupled between each even-numbered intermediate voltage node in the first ordered sub-sequence of the further ordered sequence and the first input control node; a respective capacitor connected between each odd-numbered intermediate voltage node in the second ordered sub-sequence of the further ordered sequence and a corresponding odd-numbered intermediate voltage node in the first ordered sub-sequence of the further ordered sequence; and a respective capacitor coupled between each even-numbered intermediate voltage node in the second ordered sub-sequence of the further ordered sequence and a corresponding even-numbered intermediate voltage node in the first ordered sub-sequence of the further ordered sequence; and a further plurality of selectively conductive electronic components coupled to the intermediate voltage nodes of the further ordered sequence, wherein: in the first commutation state of the voltage multiplier circuit, the further plurality of selectively conductive electronic components is configured to provide electrically-conductive paths between each of the odd-numbered intermediate voltage nodes of the further ordered sequence and a respective next even-numbered intermediate voltage node of the further ordered sequence, and in the second commutation state of the voltage multiplier circuit, the further plurality of selectively conductive electronic components is configured to provide electrically-conductive paths between each of the even-numbered intermediate voltage nodes of the further ordered sequence and a respective next odd-numbered intermediate voltage node of the further ordered sequence, an electrically-conductive path between the first input node and the first intermediate voltage node of the further ordered sequence, and an electrically-conductive path between a last intermediate voltage node of the further ordered sequence and the first output node.

3. The voltage multiplier circuit of claim 2, wherein the first plurality of selectively conductive electronic components and the further plurality of selectively conductive electronic components include a string of latched charge pump cells arranged between the first input node and the first output node.

4. The voltage multiplier circuit of claim 2, wherein the first plurality of selectively conductive electronic components comprises a p-channel transistor and an n-channel transistor arranged in the current path between each pair of subsequent intermediate voltage nodes of the ordered sequence, and wherein the further plurality of selectively conductive electronic components comprises a further p-channel transistor and a further n-channel transistor arranged in the current path between each pair of subsequent further intermediate voltage nodes of the further ordered sequence.

5. The voltage multiplier circuit of claim 4, wherein: a control terminal of the p-channel transistor is coupled to an m.sup.th intermediate voltage node of the further ordered sequence of intermediate voltage nodes and a control terminal of the n-channel transistor is coupled to an (m+1).sup.th intermediate voltage node of the further ordered sequence of intermediate voltage nodes; and a control terminal of the further p-channel transistor is coupled to an .sup.mth intermediate voltage node of the ordered sequence of intermediate voltage nodes and a control terminal of the further n-channel transistor is coupled to an (m+1).sup.th intermediate voltage node of the ordered sequence of intermediate voltage nodes.

6. The voltage multiplier circuit of claim 4, wherein: a control terminal of the p-channel transistor is coupled to the (m+1).sup.th intermediate voltage node of the further ordered sequence of intermediate voltage nodes and a control terminal of the n-channel transistor is coupled to the m.sup.th intermediate voltage node of the further ordered sequence of intermediate voltage nodes; and a control terminal of the further p-channel transistor is coupled to the (m+1).sup.th intermediate voltage node of the ordered sequence of intermediate voltage nodes and a control terminal of the further n-channel transistor is coupled to the mth intermediate voltage node of the ordered sequence of intermediate voltage nodes.

7. The voltage multiplier circuit of claim 1, wherein the first plurality of selectively conductive electronic components comprises diodes arranged in a string between the first input node and the first output node, and wherein the intermediate voltage nodes are located between subsequent diodes of the string.

8. The voltage multiplier circuit of claim 7, wherein the diodes are arranged to be selectively conductive from the first input node towards the first output node.

9. The voltage multiplier circuit of claim 7, wherein the diodes are arranged to be selectively conductive from the first output node towards the first input node.

10. The voltage multiplier circuit of claim 1, wherein the first plurality of selectively conductive electronic components comprises transistors arranged in a string between the first input node and the first output node, and wherein the intermediate voltage nodes are located between subsequent transistors of the string.

11. The voltage multiplier circuit of claim 10, further comprising control circuitry configured to activate the transistors to be conductive from the first input node towards the first output node as a function of the values of the first clock signal and the second clock signal.

12. The voltage multiplier circuit of claim 10, comprising control circuitry configured to activate the transistors to be conductive from the first output node towards the first input node as a function of the values of the first clock signal and the second clock signal.

13. The voltage multiplier circuit of claim 1, wherein the ordered sequence of intermediate voltage nodes comprises at least one third ordered sub-sequence of intermediate voltage nodes, the voltage multiplier circuit further comprising: a respective capacitor coupled between each odd-numbered intermediate voltage node in the at least one third ordered sub-sequence of the ordered sequence and a corresponding odd-numbered intermediate voltage node in a preceding ordered sub-sequence of the ordered sequence; and a respective capacitor coupled between each even-numbered intermediate voltage node in the at least one third ordered sub-sequence of the ordered sequence and a corresponding even-numbered intermediate voltage node in the preceding ordered sub-sequence of the ordered sequence.

14. The voltage multiplier circuit of claim 1, further comprising: a first clock generator coupled to the first input control node, the first clock generator configured to produce the first clock signal; and a second clock generator coupled to the second input control node, the second clock generator configured to produce the second clock signal in phase opposition to the first clock signal.

15. The voltage multiplier circuit of claim 1, wherein the voltage multiplier circuit is implemented in a semiconductor chip, and wherein the capacitors are integrated in the semiconductor chip.

16. An integrated circuit comprising: an input node configured to receive an input voltage; an output node configured to be coupled to an output capacitor and configured to produce an output voltage higher than the input voltage; a first input control node configured to receive a first clock signal; a second input control node configured to receive a second clock signal, the second clock signal being in phase opposition to the first clock signal, wherein the integrated circuit switches between a first commutation state and a second commutation state as a function of the first and second clock signals; an ordered sequence of intermediate voltage nodes arranged between the input node and the output node, the ordered sequence comprising a first ordered sub-sequence of intermediate voltage nodes and a second ordered sub-sequence of intermediate voltage nodes; a respective capacitor coupled between each odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the first input control node, wherein a first intermediate voltage node in the first ordered sub-sequence is configured to be selectively couplable to the input node; a respective capacitor coupled between each even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the second input control node; a respective capacitor coupled between each odd-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence; a respective capacitor coupled between each even-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence; and a first plurality of selectively conductive electronic components coupled to the intermediate voltage nodes of the ordered sequence, wherein: in the first commutation state, the first plurality of selectively conductive electronic components is configured to provide electrically-conductive paths between each of the even-numbered intermediate voltage nodes of the ordered sequence and a respective next odd-numbered intermediate voltage node of the ordered sequence, an electrically-conductive path between the input node and the first intermediate voltage node of the ordered sequence, and an electrically-conductive path between a last intermediate voltage node of the ordered sequence and the output node, and in the second commutation state, the first plurality of selectively conductive electronic components is configured to provide electrically-conductive paths between each of the odd-numbered intermediate voltage nodes of the ordered sequence and a respective next even-numbered intermediate voltage node of the ordered sequence.

17. The integrated circuit of claim 16, wherein the first plurality of selectively conductive electronic components comprises a plurality of diodes arranged in a string between the input node and the output node.

18. The integrated circuit of claim 17, wherein each diode of the plurality of diodes is implemented with a transistor.

19. The integrated circuit of claim 16, wherein each of the first plurality of selectively conductive electronic components comprises: first, second, third, and fourth nodes; a first n-channel transistor having a current path coupled between the first and third nodes; a first p-channel transistor having a current path coupled between the third and second nodes; a second n-channel transistor having a current path coupled between the first and fourth nodes; and a second p-channel transistor having a current path coupled between the fourth and second nodes, wherein the third node is coupled to the second input control node, and wherein the fourth node is coupled to the first input control node.

20. A method comprising: receiving an input voltage at an input node; generating an output voltage at an output node that is coupled to an output capacitor, the output voltage being higher than the input voltage, wherein an ordered sequence of intermediate voltage nodes is arranged between the input node and the output node, the ordered sequence comprising a first ordered sub-sequence of intermediate voltage nodes and a second ordered sub-sequence of intermediate voltage nodes, wherein a respective capacitor is coupled between each odd-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence, wherein a respective capacitor is coupled between each even-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence, and wherein a first plurality of selectively conductive electronic components is coupled to the intermediate voltage nodes of the ordered sequence; receiving a first clock signal at a first input control node, wherein a respective capacitor is coupled between each odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the first input control node, wherein a first intermediate voltage node in the first ordered sub-sequence is selectively couplable to the input node; receiving a second clock signal at a second input control node, the second clock signal being in phase opposition to the first clock signal, wherein a respective capacitor is coupled between each even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the second input control node; switching between a first commutation state and a second commutation state based on the first and second clock signals; in the first commutation state, providing, using the first plurality of selectively conductive electronic components, electrically-conductive paths between each of the even-numbered intermediate voltage nodes of the ordered sequence and a respective next odd-numbered intermediate voltage node of the ordered sequence, an electrically-conductive path between the input node and the first intermediate voltage node of the ordered sequence, and an electrically-conductive path between a last intermediate voltage node of the ordered sequence and the output node; and in the second commutation state, providing, using the first plurality of selectively conductive electronic components, electrically-conductive paths between each of the odd-numbered intermediate voltage nodes of the ordered sequence and a respective next even-numbered intermediate voltage node of the ordered sequence.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

[0050] FIG. 1 is a circuit diagram exemplary of a conventional N-stage voltage multiplier circuit according to a Cockcroft-Walton architecture;

[0051] FIG. 2 is a circuit diagram exemplary of a conventional N-stage voltage multiplier according to a Dickson architecture;

[0052] FIG. 3 is a circuit diagram exemplary of an equivalent circuit of a voltage multiplier circuit;

[0053] FIG. 4 is a circuit diagram exemplary of a voltage multiplier circuit having a single branch architecture for generating positive voltages according to one or more embodiments of the present description,

[0054] FIGS. 5 and 6 are circuit diagrams exemplary of operation of a voltage multiplier circuit according to FIG. 4;

[0055] FIG. 7 is a circuit diagram exemplary of a voltage multiplier circuit having a dual branch architecture for generating positive voltages according to one or more embodiments of the present description;

[0056] FIG. 8 is a circuit diagram exemplary of a voltage multiplier circuit having a single branch architecture according to one or more embodiments of the present description;

[0057] FIGS. 9 and 10 are circuit diagrams exemplary of operation of a voltage multiplier circuit according to FIG. 8;

[0058] FIG. 11 is a circuit diagram exemplary of a voltage multiplier circuit having a dual branch architecture according to one or more embodiments of the present description;

[0059] FIG. 12 is a circuit diagram exemplary of a voltage multiplier circuit having a dual branch architecture for generating positive voltages according to one or more embodiments of the present description;

[0060] FIGS. 13 and 14 are circuit diagrams exemplary of implementation details of a voltage multiplier circuit according to FIG. 12;

[0061] FIG. 15 is a circuit diagram exemplary of a voltage multiplier circuit having a single branch architecture for generating negative voltages according to one or more embodiments of the present description;

[0062] FIG. 16 is a circuit diagram exemplary of a voltage multiplier circuit having a dual branch architecture for generating negative voltages according to one or more embodiments of the present description; and

[0063] FIG. 17 is a circuit diagram exemplary of a voltage multiplier circuit having a dual branch architecture for generating negative voltages according to one or more embodiments of the present description.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0064] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0065] Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0066] The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0067] Throughout the figures annexed herein, unless the context indicates otherwise, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for brevity.

[0068] By way of introduction to the detailed description of exemplary embodiments, reference may first be made to FIGS. 1, 2 and 3.

[0069] FIG. 1 is a circuit diagram exemplary of a conventional N-stage voltage multiplier 10 according to a Cockcroft-Walton architecture. The voltage multiplier circuit 10 comprises an input node 10a configured to receive an input voltage V.sub.IN from a voltage source 12, an output node 10b configured to produce an output voltage V.sub.OUT across a storage capacitor C.sub.OUT, and a chain (or string) comprising N+1 diodes D.sub.1, . . . , D.sub.N+1 coupled (e.g., in series) between the input node 10a and the output node 10b and conductive from the input node 10a towards the output node 10b. For instance, a first diode D.sub.1 has an anode terminal coupled to the input node 10a and a cathode terminal coupled to the anode terminal of a second diode D.sub.2, each of the intermediate diodes D.sub.2, . . . , D.sub.N has a respective anode terminal coupled to the cathode terminal of the preceding diode and a respective cathode terminal coupled to the anode terminal of the next (subsequent) diode, and a last diode D.sub.N+1 has an anode terminal coupled to the cathode terminal of a second-to-last diode D.sub.N and a cathode terminal coupled to the output node 10b. The voltage multiplier circuit 10 comprises a first drive input node 14a configured to receive a first driving clock signal v.sub.CK and a second drive input node 14b configured to receive a second driving clock signal v.sub.CK which is in phase opposition to the first driving clock signal v.sub.CK x(e.g., v.sub.CK and v.sub.CK may be two square-wave clock signals having a duty cycle of 50% and shifted by half clock period). The voltage multiplier circuit 10 comprises N pumping (or coupling) capacitors C.sub.P. A first pumping capacitor C.sub.P has a first terminal coupled to a node intermediate the first and second diodes of the diode chain (i.e., coupled to the cathode terminal of the first diode D.sub.1 of the chain), and a second terminal coupled to the first drive input node 14a. A second pumping capacitor C.sub.P has a first terminal coupled to a node intermediate the second and third diodes of the diode chain (i.e., coupled to the cathode terminal of the second diode D.sub.2 of the chain), and a second terminal coupled to the second drive input node 14b. As for the other pumping capacitors, a generic j.sup.th pumping capacitor has a respective first terminal coupled to the cathode terminal of the j.sup.th diode of the chain, and a respective second terminal coupled to the cathode terminal of the (j−2).sup.th diode of the chain.

[0070] FIG. 2 is a circuit diagram exemplary of a conventional N-stage voltage multiplier 20 according to a Dickson architecture. The voltage multiplier circuit 20 comprises an input node 20a configured to receive an input voltage V.sub.IN from a voltage source 22, an output node 10b configured to produce an output voltage V.sub.OUT across a storage capacitor C.sub.OUT, and a chain (or string) comprising N.sub.+1 diodes D.sub.1, . . . , D.sub.N+1 coupled (e.g., in series) between the input node 20a and the output node 20b and conductive from the input node 20a towards the output node 20b, substantially in the same way as illustrated in FIG. 1. The voltage multiplier circuit 20 comprises a first drive input node 24a configured to receive a first driving clock signal v.sub.CK and a second drive input node 24b configured to receive a second driving clock signal v.sub.CK which is in phase opposition to the first driving clock signal v.sub.CK (e.g., v.sub.CK and v.sub.CK may be two square-wave clock signals having a duty cycle of 50% and shifted by half clock period). The voltage multiplier circuit 20 comprises N pumping (or coupling) capacitors C.sub.P. Each pumping capacitor C.sub.P has a first terminal coupled to a node intermediate two diodes of the diode chain, and a second terminal coupled to the first drive input node 24a or the second drive input node 24b. In particular, two pumping capacitors having their first terminals coupled to a same diode of the diode chain (i.e., one to the anode and the other to the cathode of the diode) have their second terminals coupled to two different drive input nodes, so that the anode and the cathode of each diode in the diode chain are driven at different voltage levels during operation of the voltage multiplier circuit 20. In other terms, the pumping capacitors having their first terminal coupled to the cathode of odd-numbered diodes of the diode chain have their second terminal coupled to the first drive input node 24a, and the pumping capacitors having their first terminal coupled to the cathode of even-numbered diodes of the diode chain have their second terminal coupled to the second drive input node 24b.

[0071] In both circuits as exemplified in FIGS. 1 and 2, the storage capacitor C.sub.OUT is configured to store charges and provide a stable output voltage V.sub.OUT, the N pumping capacitors C.sub.P are configured to pump the charges, and the diodes are configured to transfer the charges in only one direction from the input node towards the output node. Operation of the multiplier circuits as exemplified in FIGS. 1 and 2 is known to the person skilled in the art: the pumping capacitors C.sub.P, driven by two clock signals in phase opposition with voltage amplitude V.sub.CK, are alternatively charged and discharged during each half period of the clock signals, so that charge “packets” are pumped along the diode chain pulling up the output voltage V.sub.OUT.

[0072] FIG. 3 is a circuit diagram exemplary of an equivalent circuit of the voltage multiplier circuits 10 and 20, where V.sub.O is the voltage generated by the multiplier circuit in open load condition, and R.sub.OUT is the equivalent output resistance. From the equivalent circuit exemplified in FIG. 3, the output voltage V.sub.OUT a can be computed according to equation (1) below:

V.sub.OUT=V.sub.O−R.sub.OUT.Math.I.sub.OUT (1)

[0073] The open load voltage V.sub.O and the output resistance R.sub.OUT of the voltage multiplier circuits 10 and 20 are reported in document [Dickson], taking the stray capacitances into account. The equations which define the output resistance R.sub.OUT are valid if the clock period is much longer than the time constant R.sub.DC.sub.P, where R.sub.D is the diodes resistance. The results are resumed in equations (2) to (4) below, with equation (2) valid for both multipliers, equation (3) valid for the Dickson multiplier 20, and equation (4) valid for the Cockcroft-Walton multiplier 10:

[00001] $\begin{matrix} V_{O} = V_{IN} - (N + 1) .Math. V_{D} + N .Math. V_{C K} & (2) \end{matrix}$ $\begin{matrix} R_{O U T} = \frac{1}{f .Math. C_{P}} .Math. N & (3) \end{matrix}$ $\begin{matrix} R_{O U T} = {\begin{matrix} \frac{1}{f .Math. C_{P}} .Math. 2 {.Math.}_{i = 1}^{\frac{N}{2}} i^{2} & if N even \\ \frac{1}{f .Math. C_{P}} .Math. [{.Math.}_{i = 1}^{\frac{N + 1}{2}} i^{2} + {.Math.}_{i = 1}^{\frac{N + 1}{2}} i^{2}] & if N odd \end{matrix} & (4) \end{matrix}$

[0074] where V.sub.IN is the input voltage of the multiplier circuit, V.sub.CK is the swing voltage of the clock signals, V.sub.D is the forward voltage drop of the diodes, and f is the clock frequency.

[0075] It is noted that that the Cockcroft-Walton multiplier 10 has two main limitations: efficient voltage multiplication can occur only if the pumping capacitors are much greater than the stray capacitors, and the output impedance increases rapidly with the number of multiplying stages. Another limitation of the Cockcroft-Walton multiplier 10, when implemented in a monolithic integrated circuit, is that the silicon size increases rapidly with the number of multiplying stages compared to the Dickson multiplier 20, if both circuits are designed to have the same output impedance.

[0076] On the other hand, a Dickson multiplier implemented in a monolithic integrated circuit cannot reach high output voltage due to the voltage limitation of on-chip capacitors.

[0077] For instance, in the case of a voltage multiplier circuit producing an output voltage V.sub.OUT=70 V starting from an input voltage V.sub.IN=3.3 V, using pumping capacitors which have an operating voltage of 12 V, a Dickson multiplier would not be suitable due to the voltage limitation of the capacitors, while a Cockcroft-Walton multiplier with the same output impedance would have a much bigger size, according to equation (5) below obtained comparing the values of R.sub.OUT given by equations (3) and (4a):

[00002] $\begin{matrix} S i z e_{C ockcroft - Walton} = \frac{{.Math.}_{i = 1}^{N / 2} i^{2}}{N / 2} .Math. {Size}_{D i c k s o n} & (5) \end{matrix}$

[0078] Therefore, there is a need in the art to provide improved voltage multiplier circuits relying on the maximum voltage capability of on-chip capacitors while reducing the silicon area occupation.

[0079] One or more embodiments may thus relate to a voltage multiplier circuit 40 as exemplified in FIG. 4. FIG. 4 is a circuit diagram exemplary of a voltage multiplier circuit 40 having a single branch architecture for generating positive voltages.

[0080] As exemplified in FIG. 4, a voltage multiplier circuit 40 comprises a chain of diodes D.sub.1, . . . , D.sub.N+1 arranged between an input node 40a configured to receive an input voltage V.sub.IN from a voltage source 42 and an output node 40b configured to produce an output voltage V.sub.OUT, substantially as discussed with reference to FIGS. 1 and 2. The chain of diodes provides an ordered sequence of intermediate voltage nodes A.sub.1, . . . , A.sub.N between the input node 40a and the output node 40b (e.g., with generic node A.sub.x corresponding to the cathode terminal of generic diode D.sub.x).

[0081] The voltage multiplier circuit 40 comprises a first drive input node 44a configured to receive a first driving clock signal v.sub.CK and a second drive input node 44b configured to receive a second driving clock signal v.sub.CK which is in phase opposition to the first driving clock signal v.sub.CK. The voltage multiplier circuit 40 comprises N pumping (or coupling) capacitors C.sub.P. As exemplified in FIG. 4, the N pumping capacitors C.sub.P are arranged in a number K=N/M of groups (e.g., clusters), each group comprising M capacitors.

[0082] The first group of pumping capacitors comprises M pumping capacitors C.sub.P which have a first terminal coupled to the odd-numbered intermediate voltage nodes A.sub.1, A.sub.3, . . . , A.sub.2M-1 (e.g., a first node and a third node) in a first sub-sequence of 2M intermediate voltage nodes numbered from 1 to 2M (i.e., A.sub.1, . . . , A.sub.2M), and a second terminal coupled to the first drive input node 44a to receive the first driving clock signal v.sub.CK. The second group of pumping capacitors comprises M pumping capacitors C.sub.P which have a first terminal coupled to the even-numbered intermediate voltage nodes A.sub.2, A.sub.4, . . . , A.sub.2M (e.g., a second node and a fourth node) in the first sub-sequence of 2M intermediate voltage nodes, and a second terminal coupled to the second drive input node 44b to receive the second driving clock signal v.sub.CK. Therefore, the pumping capacitors in the first and second groups are arranged substantially as in a Dickson architecture.

[0083] The third group of pumping capacitors comprises M pumping capacitors C.sub.P which have a first terminal coupled to the odd-numbered intermediate voltage nodes A.sub.2M+1, A.sub.2M+3, . . . , A.sub.4M−1 (e.g., a first node and a third node) in a second sub-sequence of 2M intermediate voltage nodes numbered from 2M+1 to 4M (not visible in FIG. 4), and a second terminal coupled to the corresponding odd-numbered intermediate voltage nodes A.sub.1, A.sub.3, . . . , A.sub.2M−1 (e.g., a first node and a third node) in the first sub-sequence of 2M intermediate voltage nodes numbered from 1 to 2M. In other terms, the pumping capacitors of the third group are stacked to the pumping capacitors of the first group, similarly to a Cockcroft-Walton architecture. The fourth group of pumping capacitors comprises M pumping capacitors C.sub.P which have a first terminal coupled to even-numbered intermediate voltage nodes A.sub.2M+2, A.sub.2M+4, . . . , A.sub.4M (e.g., a second node and a fourth node) in the second sub-sequence of 2M intermediate voltage nodes numbered from 2M+1 to 4M (not visible in FIG. 4), and a second terminal coupled to the corresponding even-numbered intermediate voltage nodes A.sub.2, A.sub.4, . . . , A.sub.2M (e.g., a second node and a fourth node) in the first sub-sequence of 2M intermediate voltage nodes numbered from 1 to 2M. In other terms, the pumping capacitors of the fourth group are stacked to the pumping capacitors of the second group, similarly to a Cockcroft-Walton architecture.

[0084] In the present description, two intermediate voltage nodes of two different sub-sequences are referred to as “corresponding” when they occupy the same position (e.g., 1st position, 2nd position, etc.) in the respective ordered sub-sequences.

[0085] The number of groups of pumping capacitors depends on the number N of stages of the voltage multiplier and the number M of capacitors in each group. Generally, a second-to-last group of pumping capacitors comprises M pumping capacitors C.sub.P which have a first terminal coupled to the odd-numbered intermediate voltage nodes A.sub.N−2M+1, A.sub.N−2M+3, . . . , A.sub.N−1 in a last sub-sequence of 2M intermediate voltage nodes numbered from N−2M+1 to N, and a second terminal coupled to the corresponding odd-numbered intermediate voltage nodes A.sub.N−4M+1, A.sub.N−4M+3, . . . , A.sub.N−2M−1 in a second-to-last sub-sequence of intermediate voltage nodes numbered from N−4M+1 to N−2M (not visible in FIG. 4). In other terms, the pumping capacitors of the second-to-last group are stacked to the pumping capacitors of a fourth-to-last group, similarly to a Cockcroft-Walton architecture. The last group of pumping capacitors comprises M pumping capacitors C.sub.P which have a first terminal coupled to even-numbered intermediate voltage nodes A.sub.N−2M+2, A.sub.N−2M+4, . . . , A.sub.N in the last sub-sequence of 2M intermediate voltage nodes numbered from N−2M+1 to N, and a second terminal coupled to the corresponding even-numbered intermediate voltage nodes A.sub.N−4M+2, A.sub.N−4M+4, . . . , A.sub.N−2M in the second-to-last sub-sequence of intermediate voltage nodes numbered from N−4M+1 to N−2M (not visible in FIG. 4). In other terms, the pumping capacitors of the last group are stacked to the pumping capacitors of a third-to-last group, similarly to a Cockcroft-Walton architecture.

[0086] Therefore, in a voltage multiplier circuit 40 as exemplified in FIG. 4, the first two groups of pumping capacitors C.sub.P are arranged substantially as in a Dickson architecture, and the remaining (intermediate and last) groups of pumping capacitors C.sub.P are stacked to the previous ones, similarly to a Cockcroft-Walton multiplier (e.g., they have the lower terminals connected to the higher terminals of the capacitors in the previous two groups of capacitors and the higher terminals connected to the diode chain, progressively towards the output). In brief, the pumping capacitors belonging to a same group are arranged “in parallel” like in a Dickson charge pump, while different groups of pumping capacitors are stacked one to another similarly to a Cockcroft-Walton charge pump.

[0087] Operation of a voltage multiplier circuit 40 as exemplified in FIG. 4 is explained with reference to FIGS. 5 and 6. FIG. 5 is exemplary of charge transfer in the circuit 40 during a first half period of the clock signals v.sub.CK and v.sub.CK, in particular when v.sub.CK=0 (low value) and v.sub.CK=V.sub.CK (high value). FIG. 6 is exemplary of charge transfer in the circuit 40 during a second half period of the clock signals v.sub.CK and v.sub.CK, in particular when v.sub.CK=V.sub.CK (high value) and v.sub.CK=0 (low value).

[0088] In the first half clock period, when v.sub.CK is low and v.sub.CK is high, the pumping capacitors driven by signal v.sub.CK (i.e., coupled to the odd-numbered intermediate voltage nodes) are charged at a (more) positive voltage. They receive the charge “packets” through the odd diodes from the pumping capacitors driven by signal v.sub.CK (i.e., those coupled to the even-numbered intermediate voltage nodes) which are contextually discharged. In this phase, the first pumping capacitor is directly charged by the input voltage V.sub.IN. In the second half clock period, when v.sub.CK is high and v.sub.CK is low, the pumping capacitors driven by signal v.sub.CK are discharged. They provide the charge packets through the even diodes to the pumping capacitors driven by signal v.sub.CK, which are contextually charged at a more positive voltage.

[0089] In the first group of M pumping capacitors, driven by signal v.sub.CK, the first pumping capacitor (coupled between node 44a and node A.sub.1) is charged at V.sub.IN−V.sub.D, the third pumping capacitor (coupled between node 44a and node A.sub.3) is charged at V.sub.IN+2V.sub.CK−3V.sub.D, the fifth pumping capacitor (coupled between node 44a and node A.sub.5) is charged at V.sub.IN+4V.sub.CK−5V.sub.D, and so on, up to the (2M−1).sup.th pumping capacitor (coupled between node 44a and node A.sub.2M−1) that is charged at V.sub.IN+(2M−2).Math.V.sub.CK−(2M−1).Math.V.sub.D. In the second group of pumping capacitors, driven by v.sub.CK, the second pumping capacitor (coupled between node 44b and node A.sub.2) is charged at V.sub.IN+V.sub.CK−2V.sub.D, the fourth pumping capacitor (coupled between node 44b and node A.sub.4) is charged at V.sub.IN+3V.sub.CK−4V.sub.D, the sixth pumping capacitor (coupled between node 44b and node A.sub.6) is charged at V.sub.IN+5V.sub.CK−6V.sub.D, and so on, up to the 2M.sup.th pumping capacitor (coupled between node 44b and node A.sub.2M) that is charged at V.sub.IN+(2M−1).Math.V.sub.CK−2M.Math.V.sub.D. The pumping capacitors from 2M+1 to N (i.e., those in the third and subsequent groups) are all charged at 2M.Math.(V.sub.CK−V.sub.D); this is the voltage across the two terminals of the capacitors. The output capacitor is charged at V.sub.IN+N.Math.V.sub.CK−(N+1).Math.V.sub.D, as reported in equation (2) for the known multipliers.

[0090] It is noted that the equivalent output resistance of a voltage multiplier circuit 40 can be computed as a combination of a 2M-stage Dickson multiplier and a N/2M-stage Cockcroft-Walton multiplier, according to equation (6) below, provided that the clock period is much longer than the time constant R.sub.DC.sub.P, where R.sub.D is the diodes resistance:

[00003] $\begin{matrix} R_{O U T} = \frac{1}{f .Math. C_{P}} .Math. 2 M {.Math.}_{i = 1}^{\frac{N}{2 M}} i^{2} & (6) \end{matrix}$

[0091] Concerning the silicon size, comparing equations (3) and (6) for the computation of R.sub.OUT, it is noted that the size of an architecture as in FIG. 4 (also referred to as “hybrid” architecture hereinafter) can be expressed as:

[00004] $\begin{matrix} {Size}_{Hybrid} = \frac{{.Math.}_{i = 1}^{N / 2 M} i^{2}}{N / 2 M} .Math. {Size}_{D i ckson} & (7) \end{matrix}$

[0092] One or more embodiments may relate to a voltage multiplier circuit 70 as exemplified in FIG. 7. FIG. 7 is a circuit diagram exemplary of a voltage multiplier circuit 70 having a dual branch architecture for generating positive voltages, based on the same concept discussed with reference to FIGS. 4, 5 and 6.

[0093] As exemplified in FIG. 7, a voltage multiplier circuit 70 comprises a first chain of N+1 diodes arranged between the input node 40a and the output node 40b defining intermediate nodes A.sub.1, . . . , A.sub.N substantially as discussed with reference to FIG. 4, and a second chain of N+1 diodes arranged between the input node 40a and the output node 40b, again substantially as discussed with reference to FIG. 4, which define a further set of intermediate voltage nodes B.sub.1, . . . , B.sub.N. The voltage multiplier circuit 70 comprises 2N pumping (or coupling) capacitors C.sub.P/2. As exemplified in FIG. 7, the 2N pumping capacitors C.sub.P/2 are arranged in two subsets, each subset comprising a number K=N/M of groups (e.g., clusters), each group comprising M capacitors. The first subset includes the pumping capacitors driven by the clock signal v.sub.CK (e.g., coupled to node 44a) and the second subset includes the pumping capacitors driven by the clock signal v.sub.CK (e.g., coupled to node 44b).

[0094] The first group of the first subset of pumping capacitors comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to odd-numbered intermediate voltage nodes A.sub.1, A.sub.3, . . . , A.sub.M−1 (e.g., a first node and a third node) in a first sub-sequence of M intermediate voltage nodes numbered from 1 to M of the first set of voltage nodes A.sub.1, . . . , A.sub.N, and a second terminal coupled to the first drive input node 44a to receive the first driving clock signal v.sub.CK. The first group of the first subset of pumping capacitors also comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to the even-numbered intermediate voltage nodes B.sub.2, B.sub.4, . . . , B.sub.M (e.g., a second node and a fourth node) in a first sub-sequence of M intermediate voltage nodes numbered from 1 to M of the second set of voltage nodes B.sub.1, . . . , B.sub.N, and a second terminal coupled to the first drive input node 44a to receive the first driving clock signal v.sub.CK.

[0095] The first group of the second subset of pumping capacitors comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to the even-numbered intermediate voltage nodes A.sub.2, A.sub.4, . . . , A.sub.M (e.g., a second node and a fourth node) in the first sub-sequence of M intermediate voltage nodes numbered from 1 to M of the first set of voltage nodes A.sub.1, . . . , A.sub.N, and a second terminal coupled to the second drive input node 44b to receive the second driving clock signal v.sub.CK. The first group of the second subset of pumping capacitors also comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to odd-numbered intermediate voltage nodes B.sub.1, B.sub.3, . . . , B.sub.M−1 (e.g., a first node and a third node) in the first sub-sequence of M intermediate voltage nodes numbered from 1 to M of the second set of voltage nodes B.sub.1, . . . , B.sub.N, and a second terminal coupled to the second drive input node 44b to receive the second driving clock signal v.sub.CK.

[0096] The second group of the first subset of pumping capacitors comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to the odd-numbered intermediate voltage nodes A.sub.M+1, A.sub.M+3, . . . , A.sub.2M−1 (e.g., a first node and a third node) in a second sub-sequence of M intermediate voltage nodes numbered from M+1 to 2M of the first set of voltage nodes A.sub.1, . . . , A.sub.N, and a second terminal coupled to the corresponding odd-numbered intermediate voltage nodes A.sub.1, A.sub.3, . . . , A.sub.M−1 (e.g., a first node and a third node) in the first sub-sequence of M intermediate voltage nodes numbered from 1 to M of the first set of voltage nodes A.sub.1, . . . , A.sub.N. The second group of the first subset of pumping capacitors also comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to the even-numbered intermediate voltage nodes B.sub.M+2, B.sub.M+4, . . . , B.sub.M (e.g., a second node and a fourth node) in a second sub-sequence of M intermediate voltage nodes numbered from M+1 to 2M of the second set of voltage nodes B.sub.1, . . . , B.sub.N, and a second terminal coupled to the corresponding even-numbered intermediate voltage nodes B.sub.2, B.sub.4, . . . , B.sub.M (e.g., a second node and a fourth node) in the first sub-sequence of M intermediate voltage nodes numbered from 1 to M of the second set of voltage nodes B.sub.1, . . . , B.sub.N.

[0097] The second group of the second subset of pumping capacitors comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to the even-numbered intermediate voltage nodes A.sub.M+2, A.sub.M+4, . . . , A.sub.2M 1 (e.g., a second node and a fourth node) in the second sub-sequence of M intermediate voltage nodes numbered from M+1 to 2M of the first set of voltage nodes A.sub.1, . . . , A.sub.N, and a second terminal coupled to the corresponding even-numbered intermediate voltage nodes A.sub.2, A.sub.4, . . . , A.sub.M (e.g., a second node and a fourth node) in the first sub-sequence of M intermediate voltage nodes numbered from 1 to M of the first set of voltage nodes A.sub.1, . . . , A.sub.N. The second group of the second subset of pumping capacitors also comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to the odd-numbered intermediate voltage nodes B.sub.M+1, B.sub.M+3, . . . , B.sub.M−1 (e.g., a first node and a third node) in the second sub-sequence of M intermediate voltage nodes numbered from M+1 to 2M of the second set of voltage nodes B.sub.1, . . . , B.sub.N, and a second terminal coupled to the corresponding odd-numbered intermediate voltage nodes B.sub.1, B.sub.3, . . . , B.sub.M−1 (e.g., a first node and a third node) in the first sub-sequence of M intermediate voltage nodes numbered from 1 to M of the second set of voltage nodes B.sub.1, . . . , B.sub.N.

[0098] Generally, a last group of the first subset of pumping capacitors comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to the odd-numbered intermediate voltage nodes A.sub.N−M+1, A.sub.N−M+3, . . . , A.sub.N−1 (e.g., a first node and a third node) in a last sub-sequence of M intermediate voltage nodes numbered from N−M+1 to N of the first set of voltage nodes A.sub.1, . . . , A.sub.N, and a second terminal coupled to the corresponding odd-numbered intermediate voltage nodes A.sub.N−2M+1, A.sub.N−2M+3, . . . , A.sub.N−M−1 (e.g., a first node and a third node) in a second-to-last sub-sequence of M intermediate voltage nodes numbered from N−2M+1 to N−M of the first set of voltage nodes A.sub.1, . . . , A.sub.N. The last group of the first subset of pumping capacitors also comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to the even-numbered intermediate voltage nodes B.sub.N−M+2, B.sub.N−M+4, . . . , B.sub.N (e.g., a second node and a fourth node) in the last sub-sequence of M intermediate voltage nodes numbered from N−M+1 to N of the second set of voltage nodes B.sub.1, . . . , B.sub.N, and a second terminal coupled to the corresponding even-numbered intermediate voltage nodes B.sub.N−M+2, B.sub.N−M+4, . . . , B.sub.N (e.g., a second node and a fourth node) in the second-to-last sub-sequence of M intermediate voltage nodes numbered from N−2M+1 to N−M of the second set of voltage nodes B.sub.1, . . . , B.sub.N.

[0099] Generally, a last group of the second subset of pumping capacitors comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to the even-numbered intermediate voltage nodes A.sub.N−M+2, A.sub.N−M+4, . . . , A.sub.N (e.g., a second node and a fourth node) in the last sub-sequence of M intermediate voltage nodes numbered from N−M+1 to N of the first set of voltage nodes A.sub.1, . . . , A.sub.N, and a second terminal coupled to the corresponding even-numbered intermediate voltage nodes A.sub.N−2M+2, A.sub.N−M+4, . . . , A.sub.N−M (e.g., a second node and a fourth node) in the second-to-last sub-sequence of M intermediate voltage nodes numbered from N−2M+1 to N−M of the first set of voltage nodes A.sub.1, . . . , A.sub.N. The last group of the second subset of pumping capacitors also comprises the pumping capacitors C.sub.P/2 which have a first terminal coupled to the odd-numbered intermediate voltage nodes BN.sub.N−M+1, B.sub.N−M+3, . . . , B.sub.N−1 (e.g., a first node and a third node) in the last sub-sequence of M intermediate voltage nodes numbered from N−M+1 to N of the second set of voltage nodes B.sub.1, . . . , B.sub.N, and a second terminal coupled to the corresponding odd-numbered intermediate voltage nodes B.sub.N−2M+1, B.sub.N−2M+3, . . . , B.sub.N−M−1 (e.g., a first node and a third node) in a second-to-last sub-sequence of M intermediate voltage nodes numbered from N−2M+1 to N−M of the second set of voltage nodes B.sub.1, . . . , B.sub.N.

[0100] It is noted that, while the architecture of FIG. 7 has been described with specific reference to a first, a second and a last group of pumping capacitors in each subset, the number of groups (i.e., the number K=N/M) of pumping capacitors may be varied according to design specification, with each group being “stacked” onto a previous one (see, for instance, the intermediate groups of capacitors coupled to nodes A.sub.i+1, B.sub.i+2, A.sub.i+3, B.sub.i+M and B.sub.i+1, A.sub.i+2, B.sub.i+3, A.sub.i+M in FIG. 7).

[0101] The open load voltage V.sub.O of a voltage multiplier circuit 70 is the same as reported in equation (2) if each pumping capacitor C.sub.P/2 has a capacitance value which is half of the capacitance value of the pumping capacitors C.sub.P of a single branch architecture. The total amount of capacitance does not change between a single branch and dual branch architecture, insofar as the dual branch architecture comprises 2N*C.sub.P/2 capacitors, while the single branch architecture comprises N*C.sub.P capacitors. A dual branch architecture as exemplified in FIG. 7 may be advantageous insofar as the voltage ripple on the multiplier output, as well as the current peaks in the capacitors and diodes, are halved with respect to a single branch architecture.

[0102] Operation of a dual branch voltage multiplier 70 is similar to operation of a single branch architecture, with the voltages across the pumping capacitors that are halved, insofar as the architecture of FIG. 7 is symmetrical and, for a given N-stage multiplier, the number of pumping capacitors is double.

[0103] In the first group of pumping capacitors of the first subset (directly connected to node 44a and driven by signal v.sub.CK) and in the first group of pumping capacitors of second subset (directly connected to node 44b and driven by signal v.sub.CK), the first two pumping capacitors (coupled between nodes 44a and A.sub.1, and between nodes 44b and B.sub.1, respectively) are charged at V.sub.IN−V.sub.D, the second pumping capacitors (coupled between nodes 44a and B.sub.2, and between nodes 44b and A.sub.2, respectively) are charged at V.sub.IN+V.sub.CK−2V.sub.D, the third pumping capacitors (coupled between nodes 44a and A.sub.3, and between nodes 44b and B.sub.3, respectively) are charged at V.sub.IN+2V.sub.CK−3V.sub.D, and so on, until the M.sup.th pumping capacitors (coupled between nodes 44a and B.sub.M, and between nodes 44b and A.sub.M, respectively, in case M is even; coupled between nodes 44a and A.sub.M, and between nodes 44b and B.sub.M, respectively, in case M is odd) that are charged at V.sub.IN+(M−1).Math.V.sub.CK−M.Math.V.sub.D. The pumping capacitors of the other groups, coupled to the intermediate voltage nodes numbered from M+1 to N, are all charged at M.Math.(V.sub.CK−V.sub.D). The output capacitor is charged at V.sub.IN+N.Math.V.sub.CK−(N+1).Math.V.sub.D, as reported in equation (2) for the known multipliers and for the single branch architecture.

[0104] It is noted that the equivalent output resistance of a voltage multiplier circuit 70 can be computed as a combination of an M-stage Dickson multiplier and an N/M-stage Cockcroft-Walton multiplier, according to equation (8) below, provided that the clock period is much longer than the time constant R.sub.DC.sub.P, where R.sub.D is the diodes resistance:

[00005] $\begin{matrix} R_{O U T} = \frac{1}{f .Math. C_{P}} .Math. M {.Math.}_{i = 1}^{\frac{N}{M}} i^{2} & (8) \end{matrix}$

[0105] Concerning the silicon size, comparing equations (3) and (8) for the computation of R.sub.OUT, it is noted that the size of an architecture as in FIG. 7 (also referred to as “hybrid dual” architecture hereinafter) can be expressed as:

[00006] $\begin{matrix} {Size}_{Hybrid} = \frac{{.Math.}_{i = 1}^{N / M} i^{2}}{N / M} .Math. {Size}_{D i c k s o n} & (9) \end{matrix}$

[0106] In one or more embodiments (e.g., in an on-chip implementation), diodes D.sub.1, . . . , D.sub.N+1 may be replaced by MOS transistors as exemplified in FIG. 8. It will be noted that the voltage multiplier circuit 80 of FIG. 8 substantially corresponds to the architecture of FIG. 4, with diodes D.sub.1, . . . , D.sub.N+1 replaced by MOS transistors M.sub.1, . . . , M.sub.N+1. The MOS transistors can be n-channel and/or p-channel, as long as they are properly driven to be conductive from the input node towards the output node according to the current values of the clock signals v.sub.CK and v.sub.CK.

[0107] Operation of a voltage multiplier circuit 80 as exemplified in FIG. 8 is explained with reference to FIGS. 9 and 10. FIG. 9 is exemplary of charge transfer in the circuit 80 during a first half period of the clock signals v.sub.CK and v.sub.CK, in particular when v.sub.CK=0 (low value) and v.sub.CK=V.sub.CK (high value). FIG. 10 is exemplary of charge transfer in the circuit 80 during a second half period of the clock signals v.sub.CK and v.sub.CK, in particular when v.sub.CK=V.sub.CK (high value) and v.sub.CK=0 (low value).

[0108] In the first half clock period, when v.sub.CK is low and v.sub.CK is high, the pumping capacitors driven by signal v.sub.CK are charged at a (more) positive voltage by the pumping capacitors driven by signal v.sub.CK, which are contextually discharged. The pumping capacitors driven by v.sub.CK receive the charge “packets” through the odd switches (MOS transistors), which are in a conductive state (turned on) in this phase, while the even switches (MOS transistors) are in a non-conductive state (turned off). In this phase, the first pumping capacitor is directly charged by the input voltage V.sub.IN. In the second half clock period, when v.sub.CK is high and v.sub.CK is low, the pumping capacitors driven by signal v.sub.CK are discharged by the pumping capacitors driven by signal v.sub.CK, which are contextually charged at a more positive voltage. The pumping capacitors driven by signal v.sub.CK provide the charge packets through the even switches (MOS transistors), which are in a conductive state (turned on) in this phase, while the odd switches (MOS transistors) are in a non-conductive state (turned off).

[0109] In the first group of pumping capacitors, directly connected to node 44a and driven by signal v.sub.CK, the first pumping capacitor (coupled between node 44a and node A.sub.1) is charged at V.sub.IN, the third pumping capacitor (coupled between node 44a and node A.sub.3) is charged at V.sub.IN+2V.sub.CK, the fifth pumping capacitor (coupled between node 44a and node A.sub.5) is charged at V.sub.IN+4V.sub.CK, and so on, until the (2M−1).sup.th pumping capacitor (coupled between node 44a and node A.sub.2M−1) that is charged at V.sub.IN+(2M−2).Math.V.sub.CK. In the second group of pumping capacitors, directly connected to node 44b and driven by signal v.sub.CK, the second pumping capacitor (coupled between node 44b and node A.sub.2) is charged at V.sub.IN+V.sub.CK, the fourth pumping capacitor (coupled between node 44b and node A.sub.4) is charged at V.sub.IN+3V.sub.CK, the sixth pumping capacitor (coupled between node 44b and node A.sub.6) is charged at V.sub.IN+5V.sub.CK, and so on, until the 2M.sup.th pumping capacitor (coupled between node 44b and node A.sub.2) that is charged at V.sub.IN+(2M−1).Math.V.sub.CK. The pumping capacitors from 2M+1 to N are all charged at 2M.Math.V.sub.CK; this is the voltage across the two terminals of the capacitors. The open load output voltage V.sub.O is reported in equation (10) below:

V.sub.O=V.sub.IN+N.Math.V.sub.CK (10)

[0110] It is noted that the equivalent output resistance of a voltage multiplier circuit 80 as exemplified in FIG. 8 is the same as defined in equation (6), provided that the clock period is much longer than the time constant R.sub.MC.sub.P, where R.sub.M is the MOS transistor resistance.

[0111] In one or more embodiments, MOS transistors may be used to replace the diodes also in a dual branch architecture, as exemplified in FIG. 11. It will be noted that the voltage multiplier circuit 110 of FIG. 11 substantially corresponds to the architecture of FIG. 7, with diodes replaced by MOS transistors. The MOS transistors can be n-channel and/or p-channel, as long as they are properly driven (e.g., according to the driving scheme discussed with reference to FIGS. 9 and 10, if a positive output voltage is to be generated).

[0112] It is noted that the equivalent output resistance of a voltage multiplier circuit no as exemplified in FIG. 11 is the same as defined in equation (8), provided that the clock period is much longer than the time constant R.sub.MC.sub.P, where R.sub.M is the MOS transistor resistance. Also, the open load voltage V.sub.O of a voltage multiplier circuit no as exemplified in FIG. 11 is the same as defined in equation (10). A dual branch MOS architecture as exemplified in FIG. 11 may be advantageous insofar as the voltage ripple on the multiplier output, as well as the current peaks in the capacitors and MOS transistors, are halved with respect to a single branch MOS architecture.

[0113] Generally, a dual branch voltage multiplier circuit for generating positive voltages may be implemented as exemplified by the circuit diagram of FIG. 12.

[0114] As exemplified in FIG. 12, a voltage multiplier circuit 120 comprises a chain of N charge transfer circuit blocks 130 arranged between the input node 40a and the output node 40b. Each charge transfer circuit block 130 has an input terminal V.sub.d, an output terminal V.sub.u, a first control terminal and a second control terminal, as exemplified in FIG. 13. The charge transfer circuit block 130 comprises electronic components (e.g., diodes and/or transistors) arranged so that charge is transferred from the input terminal V.sub.d to the output terminal V.sub.u when two switching signals in phase opposition are applied to the first and second control terminals. In particular, depending on the values of the control signals received at the two control terminals, the circuit block 130 may operate in two distinct commutation states: in a first state, the input terminal V.sub.d is coupled to the first control terminal and the output terminal V.sub.u is coupled to the second control terminal; in a second state, the input terminal V.sub.d is coupled to the second control terminal and the output terminal V.sub.u is coupled to the first control terminal.

[0115] As exemplified in FIG. 12, the first control terminal and the second control terminal of each charge transfer circuit block 130 are configured to receive complementary control signals (e.g., v.sub.CK and v.sub.CK) via respective pumping capacitors C.sub.P/2. As exemplified in FIG. 12, the N charge transfer circuit blocks 130 are arranged in a number K=N/M of sub-chains, each sub-chain comprising a string of M blocks 130.

[0116] In the first sub-chain of blocks 130, the first control terminal of each block 130 is coupled via a respective pumping capacitor C.sub.P/2 to the first drive input node 44a, and the second control terminal of each block 130 is coupled via a respective pumping capacitor C.sub.P/2 to the second drive input node 44b. In the second sub-chain of blocks 130, the first control terminal of each block 130 is coupled via a respective pumping capacitor C.sub.P/2 to the first control terminal of a corresponding block 130 in the first sub-chain, and the second control terminal of each block 130 is coupled via a respective pumping capacitor C.sub.P/2 to the second control terminal of a corresponding block 130 in the first sub-chain. In other terms, the pumping capacitors coupled to the blocks 130 in the second sub-chain are stacked to the pumping capacitors coupled to the blocks 130 in the first sub-chain.

[0117] The number K of sub-chains depends on the number N of stages and on the number M of blocks in each sub-chain. Generally, in the j.sup.th sub-chain of blocks 130, the first control terminal of each block 130 is coupled via a respective pumping capacitor C.sub.P/2 to the first control terminal of a corresponding block 130 in the (j−1).sup.th sub-chain, and the second control terminal of each block 130 is coupled via a respective pumping capacitor C.sub.P/2 to the second control terminal of a corresponding block 130 in the (j−1)th sub-chain.

[0118] For instance, in one or more embodiments each charge transfer circuit block 130 may comprise an arrangement as exemplified in FIG. 14. The arrangement comprises a first re-channel transistor N.sub.1 having a current path between the input terminal V.sub.d and the first control terminal, a second n-channel transistor N.sub.2 having a current path between the input terminal V.sub.d and the second control terminal, a first p-channel transistor P.sub.1 having a current path between the output terminal V.sub.u and the first control terminal, and a second p-channel transistor P.sub.2 having a current path between the output terminal V.sub.u and the second control terminal. The gate terminals of the first n-channel transistor N.sub.1 and first p-channel transistor P.sub.1 are coupled to the second control terminal, and the gate terminals of the second n-channel transistor N.sub.2 and second p-channel transistor P.sub.2 are coupled to the first control terminal.

[0119] Operation of such an arrangement is disclosed in documents [Pulvirenti] and [Gariboldi 96] for use in a latched charge pump, and therefore will not be repeated herein for the sake of brevity.

[0120] One or more embodiments may be used to generate negative voltages. This can be obtained, for instance, inverting the polarity of the diodes in the architectures of FIGS. 4 and 7, as exemplified respectively in the circuit diagrams of FIGS. 15 and 16, or inverting the polarity of the activation signals of the MOS transistors in the architectures of FIGS. 8 and 11, or inverting the direction of (e.g., flipping) the charge transfer circuit blocks 130 in the architecture of FIG. 12 (e.g., swapping the terminals V.sub.u and V.sub.d), as exemplified in the circuit diagram of FIG. 17.

[0121] Operation of a single branch, negative voltage multiplier circuit 150 as exemplified in FIG. 15 is similar to the operation of a single branch, positive voltage multiplier circuit 40 as exemplified in FIG. 4, and is therefore discussed in the following merely by way of example. In the first half clock period, when v.sub.CK is low and v.sub.CK is high, the pumping capacitors driven by signal v.sub.CK (i.e., coupled to odd-numbered intermediate voltage nodes A.sub.1, . . . , A.sub.N−1) are charged. They receive the charge “packets” through the even diodes from the pumping capacitors driven by signal v.sub.CK (i.e., coupled to even-numbered intermediate voltage nodes A.sub.2, . . . , A.sub.N) which are contextually discharged at a more negative voltage. In the second half clock period, when v.sub.CK is high and v.sub.CK is low, the pumping capacitors driven by signal v.sub.CK are discharged at a more negative voltage. They provide the charge packets through the odd diodes to the pumping capacitors driven by signal v.sub.CK, which are contextually charged. In this phase, the first pumping capacitor is directly discharged to the input voltage V.sub.IN.

[0122] The first pumping capacitor (coupled between node 44a and node A.sub.1) is charged at V.sub.IN−V.sub.CK+V.sub.D, the second pumping capacitor (coupled between node 44b and node A.sub.2) is charged at V.sub.IN−2V.sub.CK+2V.sub.D, the third pumping capacitor (coupled between node 44a and node A.sub.3) is charged at V.sub.IN−3V.sub.CK+3V.sub.D, and so on. In the single branch architecture, the pumping capacitors from 2M to N are all charged at −2M.Math.(V.sub.CK−V.sub.D); in the dual branch architecture, the pumping capacitors from M to N are all charged at −M.Math.(V.sub.CK−V.sub.D). The open load output voltage V.sub.O is reported in equation (11) below:

V.sub.O=V.sub.IN−N.Math.V.sub.CK+(N+1).Math.V.sub.D (11)

[0123] It is noted that the equivalent output resistance of a voltage multiplier circuit 150 is the same as reported in equation (6).

[0124] It is also noted that connecting the first diode to ground rather than to V.sub.IN, the output voltage becomes more negative.

[0125] Operation of a dual branch negative voltage multiplier 160 as exemplified in FIG. 16 is similar to operation of a single branch negative architecture, with the voltages across the pumping capacitors that are halved, and will not be further described herein for the sake of brevity.

[0126] Operation of a negative voltage multiplier circuit based on a MOS transistor architecture as exemplified in FIG. 8 may be obtained by inverting the operation previously explained with reference to FIGS. 9 and 10, i.e., inverting the activation phases of the MOS transistors with respect to the two semi-periods of the clock signals. In that case, in the first half clock period, when v.sub.CK is low and v.sub.CK is high, the pumping capacitors driven by signal v.sub.CK are charged by the pumping capacitors driven by signal v.sub.CK, which are contextually discharged at a more negative voltage. The pumping capacitors driven by v.sub.CK receive the charge “packets” through the even switches (MOS transistors), which are in a conductive state (turned on) in this phase, while the odd switches (MOS transistors) are in a non-conductive state (turned off). In the second half clock period, when v.sub.CK is high and v.sub.CK is low, the pumping capacitors driven by signal v.sub.CK are discharged at a more negative voltage by the pumping capacitors driven by signal v.sub.CK, which are contextually charged. The pumping capacitors driven by signal v.sub.CK provide the charge packets through the odd switches (MOS transistors), which are in a conductive state (turned on) in this phase, while the even switches (MOS transistors) are in a non-conductive state (turned off). In this phase, the first pumping capacitor is directly discharged to the input voltage V.sub.IN.

[0127] The first pumping capacitor (coupled between node 44a and node A.sub.1) is charged at V.sub.IN−V.sub.CK, the second pumping capacitor (coupled between node 44b and node A.sub.2) is charged at V.sub.IN−2V.sub.CK, the third pumping capacitor (coupled between node 44a and node A.sub.3) is charged at V.sub.IN−3V.sub.CK, and so on. In the single branch architecture, the pumping capacitors from 2M to N are all charged at −2M.Math.V.sub.CK; in the dual branch architecture, the pumping capacitors from M to N are all charged at −M.Math.V.sub.CK. The open load output voltage V.sub.O is reported in equation (12) below:

V.sub.O=V.sub.IN−N.Math.V.sub.CK (12)

[0128] The equivalent output resistance is the same as defined in equation (6).

[0129] The operation of a dual branch negative voltage multiplier with MOS transistors is similar to the operation of the single branch one, and will thus not be further described for the sake of brevity.

[0130] Tables I and II provided at the end of the description summarize the formulas of the open load voltage V.sub.O, the output resistance R.sub.OUT and the total capacitance amount C.sub.TOT of the voltage multipliers circuits discussed herein.

[0131] One or more embodiments may be applied, purely by way of example, to a monolithic octal driver for MEMS (Micro Electro Mechanical Systems) switches, where a supply rail V.sub.OUT=70 V for the drivers is generated starting from a power supply V.sub.DD=3.3 V. For instance, one or more embodiments may be implemented using a silicon-on-insulator (SOI) technology, such as SOI-BCD6s technology, with pumping capacitors having 12 V operative voltage. Considering a regulated power supply of 3.0 V, such an exemplary multiplier may have almost N=24 stages. Moreover, assuming V.sub.IN=V.sub.CK=3.0 V, M can be selected dividing the operating voltage of the pumping capacitors (e.g., 12 V) by the regulated power supply (e.g., 3.0 V). So far, M can be equal to 4, as the maximum voltage on the pumping capacitors would not exceed the operating value of 12 V. From equation (9) with M=1, a 24 N-Stage Cockcroft-Walton multiplier would be 204 times bigger than a Dickson one, while from equation (9) with M=4, a multiplier according to one or more embodiments having 24 N-Stage and 4 M-Stage would be 15.2 times bigger than a Dickson one and 13.4 times smaller than a Cockcroft-Walton one.

[0132] One or more embodiments may thus provide an integrated voltage multiplier circuit with reduced silicon area occupation.

[0133] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

[0134] The extent of protection is determined by the annexed claims.

TABLE-US-00001 TABLE I Multiplier Multiplier with type Multiplier with diodes MOS transistors Positive V.sub.O = V.sub.IN + N .Math. V.sub.CK − (N + 1) .Math. V.sub.D V.sub.O = V.sub.IN + N .Math. V.sub.CK voltage Negative V.sub.O = V.sub.IN − N .Math. V.sub.CK + (N + 1) .Math. V.sub.D V.sub.O = V.sub.IN − N .Math. V.sub.CK voltage

TABLE-US-00002 TABLE II Multiplier type Output resistance Total capacitance amount Dickson [00007] $R_{OUT} = \frac{1}{f .Math. C_{P}} .Math. N$ [00008] $C_{TOT} = \frac{1}{f .Math. R_{OUT}} .Math. N^{2}$ Cockcroft- Walton dual branch [00009] $R_{OUT} = \frac{1}{f .Math. C_{P}} .Math. {.Math.}_{i = 1}^{N} i^{2}$ [00010] $C_{TOT} = \frac{1}{f .Math. R_{OUT}} .Math. N .Math. {.Math.}_{i = 1}^{N} i^{2}$ Hybrid dual branch [00011] $R_{OUT} = \frac{1}{f .Math. C_{P}} .Math. M .Math. {.Math.}_{i = 1}^{N / M} i^{2}$ [00012] $C_{TOT} = \frac{1}{f .Math. R_{OUT}} .Math. N .Math. M .Math. {.Math.}_{i = 1}^{N / M} i^{2}$

VOLTAGE MULTIPLIER CIRCUIT

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Cpc classification

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H02M3/076

ELECTRICITY

Classification Explorer

H02M3/07

ELECTRICITY

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H02M7/103

ELECTRICITY

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H02M1/0095

ELECTRICITY

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H02M3/073

ELECTRICITY

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H02M1/0043

ELECTRICITY

International classification

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H02M3/07

ELECTRICITY

Abstract

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Description