Abstract
A method for manufacturing a capacitor structure for quantum integrated circuits, in particular superconducting quantum integrated circuits, comprising: providing a first wafer structure comprising a first substrate; providing a second wafer structure comprising a second substrate; a heterostructure on the second substrate, the heterostructure comprising a buried etch stop layer, a dielectric layer on the etch stop layer, and a second metal film deposited on the etch stop layer of the heterostructure; bonding the first wafer structure and the second wafer structure together using the second metal film as bonding medium, thereby forming a bonded layer stack sandwiched between the first and the second substrate, the bonded layer stack comprising the buried etch stop layer, the dielectric layer and the second metal film; stripping the second substrate from the second wafer structure, stopping on the buried etch stop layer; selectively removing the buried etch stop layer from the bonded layer stack, thereby exposing the dielectric layer of the second wafer; forming a top electrode layer on the exposed dielectric layer of the second wafer; patterning a plurality of parallel trenches into the second metal film; wherein the step of patterning is performed either before the bonding step or else after the forming of the top electrode layer, wherein the parallel trenches extend through the top electrode layer and the bonded layer stack.
Claims
1. A method for manufacturing a capacitor structure for quantum integrated circuits, in particular superconducting quantum integrated circuits, comprising: providing a first wafer structure comprising a first substrate; providing a second wafer structure comprising a second substrate; a heterostructure on the second substrate, the heterostructure comprising a buried etch stop layer, a dielectric layer on the etch stop layer, and a second metal film deposited on the dielectric layer of the heterostructure; bonding the first wafer structure and the second wafer structure together using the second metal film as bonding medium, thereby forming a bonded layer stack sandwiched between the first and the second substrate, the bonded layer stack comprising the buried etch stop layer, the dielectric layer and the second metal film; stripping the second substrate from the second wafer structure, stopping on the buried etch stop layer; selectively removing the buried etch stop layer from the bonded layer stack, thereby exposing the dielectric layer of the second wafer; forming a top electrode layer on the exposed dielectric layer of the second wafer; patterning a plurality of parallel trenches into the second metal film; and wherein the step of patterning is performed either before the bonding step or else after the formation of the top electrode layer, wherein the parallel trenches extend through the top electrode layer and the bonded layer stack.
2. The method according to claim 1, wherein the second metal film comprises Al, or a similar superconducting material.
3. The method according to claim 1, wherein the step of providing a first wafer structure further comprises depositing a first metal film on the first substrate, in particular wherein the first metal film and the second metal film comprise the same material.
4. The method according to claim 2, wherein the step of providing a first wafer structure further comprises depositing a first metal film on the first substrate, in particular wherein the first metal film and the second metal film comprise the same material.
5. The method according to claim 3, wherein the step of patterning further includes patterning a plurality of further parallel trenches into the first metal film, the further parallel trenches corresponding in size to the parallel trenches in the second metal film, wherein if the step of patterning is performed before the bonding step, the bonding step further comprises aligning the first wafer structure and the second wafer structure such that the parallel trenches in the second metal film match the further parallel trenches in the first metal film.
6. The method according to claim 1, wherein the first substrate comprises Si and/or GaAs and/or sapphire.
7. The method according to claim 2, wherein the first substrate comprises Si and/or GaAs and/or sapphire.
8. The method according to claim 3, wherein the first substrate comprises Si and/or GaAs and/or sapphire.
9. The method according to claim 5, wherein the first substrate comprises Si and/or GaAs and/or sapphire.
10. The method according to claim 1, wherein the second substrate of the second wafer is a Si handle wafer, the buried etch stop layer is a buried oxide layer, and the dielectric layer is a single-crystal Si device layer, thereby the second wafer is a Silicon on Insulator, SOI, wafer.
11. The method according to claim 1, wherein the second substrate of the second wafer comprises a GaAs host substrate, the buried etch stop layer is an AlGaAs etch stop layer preferably comprising a high-Al content, Al.sub.xGa.sub.1-xAs alloy, with x>40%, and the dielectric layer is a single-crystal GaAs layer.
12. The method according to claim 11, wherein the AlGaAs etch stop layer and the GaAs layer are epitaxially grown on the GaAs host substrate.
13. The method according to claim 3, wherein the bonding step further comprises removing surface oxide layers from the first and/or second metal films by mechanical or chemical means, such as ion milling or chemical etching.
14. The method according to claim 1, wherein the bonding step is performed in a high or ultrahigh vacuum environment with a pressure <10.sup.7 mbar.
15. The method according to claim 1, wherein the step of removing the second substrate from the second wafer comprises stripping the second substrate by lapping and/or selective dry or wet etching.
16. The method according to claim 1, wherein the top electrode layer comprises Al or an alternative superconducting material.
17. A capacitor structure comprising: a first substrate; at least one capacitor formed on the first substrate, each of the at least one capacitors comprising: a first electrode layer, the first electrode layer provided on the first substrate; a second electrode layer, the second electrode layer facing away from the first substrate; and a single-crystal semiconductor layer or multilayer heterostructure sandwiched between the first electrode layer and the second electrode layer.
18. The capacitor structure according to claim 17, wherein the multilayer heterostructure comprises a buried oxide layer and a Si device layer on the buried oxide layer, or wherein the heterostructure comprises an AlGaAs etch stop layer, preferably comprising a high-Al content, Al.sub.xGa.sub.1-xAs alloy, with x>40%, and a GaAs layer on the AlGaAs etch stop layer.
19. The capacitor structure according to claim 17, wherein the first electrode layer and the second electrode layer comprise the same material, preferably wherein the first and second metal film comprise Al.
20. The capacitor structure according to claim 18, wherein the first electrode layer and the second electrode layer comprise the same material, preferably wherein the first and second metal film comprise Al.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0036] FIG. 1A schematically illustrates a view of a process flow step according to an embodiment of the present disclosure.
[0037] FIG. 1B schematically illustrates a variation of a process flow step according to the embodiment of FIG. 1A.
[0038] FIG. 2 schematically illustrates a further step of the process flow including bonding together of a first and second wafer structure.
[0039] FIGS. 3A and 3B illustrate a further step of the process flow including stripping of the handle substrate and removal of the etch stop layer.
[0040] FIGS. 4A and 4B illustrate a further step of the process flow including patterning trenches into the structure shown in FIG. 3B.
[0041] FIG. 5A schematically illustrates a view of a process flow step according to a further embodiment of the present disclosure.
[0042] FIG. 5B schematically illustrates a variation of a process flow step according to the embodiment of FIG. 5A.
[0043] FIG. 6 schematically illustrates a further step of the process flow including bonding together of a first and second wafer structure of the further embodiment of the present disclosure.
[0044] FIGS. 7A and 7B illustrate a further step of the process flow including stripping of the handle substrate.
[0045] FIGS. 8A and 8B illustrate a further step of the process flow including patterning trenches into the structure shown in FIG. 7B.
[0046] FIG. 9 illustrates a capacitor structure according to the present disclosure comprising a plurality of capacitors according to the first or the second embodiment.
[0047] FIGS. 10A and 10B illustrate a variation of process flow steps shown in FIGS. 1A, 1B, and 2 according to an embodiment of the present disclosure.
[0048] FIGS. 11 and 11B illustrate a variation of process flow steps shown in FIGS. 5A, 5B, and 6, according to an embodiment of the present disclosure.
DETAILED DESCRIPTION
[0049] FIG. 1A illustrates a first embodiment according to the present disclosure. In FIG. 1A, a first wafer/base wafer structure A is provided. The first wafer structure A comprises a first substrate 11. A first metal film 9 is shown in FIG. 1A as being deposited directly on the first substrate 11. However, as contrasted to FIG. 1A, in FIG. 1B it is indicated that the metal film 9 is optional. Thus, the first wafer structure A may also comprise just a first substrate 11. The first metal film 9 may be an Al film. FIGS. 1A and 1B also disclose a second wafer structure B1 comprising a second wafer S. The second wafer S comprises a second substrate 7 and a heterostructure H1 directly deposited on the second substrate 7. The second substrate 7 may comprise silicon, Si, in particular it may be a Si handle wafer. The heterostructure H1 may comprise at least one, typically more than one layers. In FIGS. 1A and 1B, the heterostructure H1 comprises two layers. The first layer of the heterostructure H1 disclosed in FIGS. 1A and 1B is layer 5. Layer 5 is a buried oxide layer which also serves as an etch stop layer. The buried oxide layer 5 is typically formed directly on the surface of the second substrate 7. The second layer of the heterostructure H1 disclosed in FIG. 1A is a dielectric layer 3. The dielectric layer 3 may be a single-crystal silicon, Si, device layer. The dielectric layer 3 is formed directly on the buried oxide layer 5. The second substrate 7, buried oxide layer 5 and dielectric layer 3 together form a Silicon on Insulator, SOI, wafer S. The second wafer structure B1 further comprises a second metal film 1. The second metal film 1 is formed directly on the SOI wafer S. In other words, the second metal film 1 is formed directly on the single-crystal Si device layer 3. Thus, as shown in this embodiment of FIGS. 1A and 1B, respectively, the heterostructure H1 of the second wafer structure B1 comprises two layers, 5 and 3, and is formed on the second substrate 7. The second substrate 7, buried oxide layer 5 and dielectric layer 3, in that order, form the SOI wafer S. The second metal film 1 is formed on the heterostructure H1 of the SOI wafer S.
[0050] FIG. 2 discloses a further processing step of the process flow. The elements introduced in FIGS. 1A and 1B are denoted by the same reference signs. FIG. 2 discloses flipping one of the two wafer structures, i.e. the first wafer structure A and the second wafer structure B1 so that the first metal film 9 of the first wafer structure A and the second metal film 1 of the second wafer structure B1 face each other and are brought into contact for bonding together the two wafer structures A and B1. Thus, the metal films 9 and 1 form a common bonding medium. It should be understood that if the first metal film 9 is omitted, i.e. as shown in FIG. 1B, the second metal film 1 directly contacts the substrate 11 of the first wafer structure A.
[0051] Typically, a pre-bonding step will also be conducted including removing possible surface oxide layers from the first 9 and/or second metal films 1 by mechanical or chemical means, such as ion milling or chemical etching. The pre-bonding step will thus ensure high quality and intimate bonding of the first 9 and second 1 metal films.
[0052] The bonding step as shown in FIG. 2 will then provide the sequence of layers comprised of the buried oxide layer 5, the dielectric layer 3, the second metal film 1 and optionally the first metal film 9, as forming a bonded layer stack BLS1. The bonded layer stack BLS1 is sandwiched directly between the first substrate 11 and the second substrate 7.
[0053] FIGS. 3A and 3B disclose further processing step of the process flow after the bonding step which was disclosed with respect to FIG. 2. As indicated in FIG. 3A, the second substrate 7 of the second wafer structure is removed or stripped. The removing may be performed by well understood removing or stripping methods such as mechanical lapping followed by wet or dry chemical etching. The removal process is stopped on the buried etch stop layer 5 which serves as an etch stop layer. Thus, the buried etch stop layer 5 is exposed in this step. Thereby the bonded layer stack BLS1 is transferred, now only residing on the first substrate 11. Subsequently, as indicated in FIG. 3B, the buried etch stop layer 5 is also removed by a selective removal process. The selective removal process may include dry etching or wet etching. Eventually a single-crystal Si layer 3, i.e. the Si device layer is left behind. The Si device layer 3 is located on the common bonding medium formed by the metal films 1 and 9, if present, respectively. The dielectric layer 3 and the metal films 1, and if present, 9, form a reduced or thinned bonded layer stack BLS1.
[0054] FIGS. 4A and 4B disclose further processing steps of the process flow after the removal or stripping of layer 5 as discussed with respect to FIGS. 3A and 3B. FIG. 4A discloses that top electrode layer 13 is formed directly on the Si device layer 3 of the reduced bonded layer stack BLS1, after the Si device layer 3 has been exposed in the previous step, cf. FIGS. 3A and 3B. The top electrode layer 13 is typically formed directly on the surface of the Si layer 3. Here, the surface of the Si layer 3 should be understood as being that surface of the Si layer 3 facing away from the bonded metal films 9 and 1, respectively, as well as facing away from the first substrate 11.
[0055] FIG. 4B illustrates forming or patterning a plurality of parallel trenches 13T1, 13T2 into the electrode layer 13 and the bonded layer stack underneath the electrode layer. Here, the etching/forming of the trenches 13T1, 13T2 either stops just below the Al layer or continues into the base substrate. It should be understood that for the purpose of illustrating only two trenches 13T1, 13T2 are shown but that the number of trenches may be one or more than two. The trenches 13T1, 13T2 are typically oriented vertically, i.e. perpendicular to the surface of the substrate 11 which faces the metal films. The width of the trenches 13T1, 13T2, is denoted as W1, W2, respectively. It should be understood that W1 may be equal to W2 but it may be different from W2, as well such that the trenches may have different widths. Thereby, different two-dimensional structures may be patterned into the top electrodes 13. The trenches stop on the surface of the substrate 11, though they may also propagate into the base substrate. By forming/patterning the trenches 13T1, 13T2, a plurality of top electrodes 13 are formed directly on the dielectric layer 3 and at the same time a plurality of discrete capacitor structures 13.1, 13.2 and 13.3 are formed, each comprising a top electrode 13 directly above the dielectric layer 3 and a metal film directly below the dielectric film, cf. FIG. 9. It should be understood that for illustrational purposes only, FIG. 4B only shows three discrete capacitor structures 13.1, 13.2, and 13.3. However, the number of discrete capacitor structures may be different from three. In particular it may ben, where n is an integer number and n is larger than or equal to 1. Here, the parallel trenches 13T1, 13T2 extend through the top electrode layer 13 and the bonded layer stack.
[0056] FIGS. 5A, 5B-8 illustrates a second embodiment according to the present disclosure. Here, common elements with regard to FIGS. 1A, 1B-4 are denoted by the same reference signs.
[0057] FIGS. 5A and 5B may be compared to FIGS. 1A and 1B, respectively. FIGS. 5A and 5B illustrate a further embodiment according to the present disclosure. In FIG. 5, similar as in FIG. 1A and 1B, a first wafer/base wafer structure A is provided. The first wafer structure A comprises a first substrate 11. A first metal film 9 is shown in FIG. 5A as being deposited directly on the first substrate 11. However, as contrasted to FIG. 5A, in FIG. 5B it is indicated that the first metal film 9 is optional. Thus, the first wafer structure A may also comprise just a first substrate 11. The first metal film 9 may be an Al film. FIGS. 5A and 5B also disclose a second wafer structure E comprising a second substrate 27 and a second heterostructure H2 directly deposited on the second substrate 27. The second substrate 27 may comprise GaAs, in particular it may be a GaAs host wafer. The heterostructure H2 may comprise at least one, typically more than one layers. In FIGS. 5A and 5B, the heterostructure H2 comprises two layers. The first layer of the heterostructure H2 disclosed in FIGS. 5A and 5B is layer 25. Layer 25 is an AlGaAs etch stop layer. Typically, the AlGaAs etch stop layer 25 may comprise a high-Al content, Al.sub.xGa.sub.1-xAs layer, with x>40%. The AlGaAs etch stop layer 25 is typically formed directly on the surface of the second substrate 27. A second layer of the heterostructure H2 in FIG. 5 is dielectric layer 23. Dielectric layer 23 may be a GaAs layer. Dielectric layer 23 may be formed directly on layer 25. These layers 23 and 25 may be epitaxially grown on the second substrate. The second substrate 27, layer 25 and layer 23 together form a GaAs/AlGaAs heterostructure wafer. This GaAs/AlGaAs heterostructure wafer will serve as a second half of a base superconducting electrode. A second metal film 21 is formed directly on the GaAs/AlGaAs heterostructure wafer, i.e. the second metal film 1 is formed directly on the dielectric layer 23. In other words, the heterostructure H2 comprising the dielectric layer 23 and the AlGaAs etch stop layer 25 is formed on the second substrate 27. The second substrate 27, layer 25 and layer 23, in that order, form the GaAs/AlGaAs heterostructure wafer. The second metal film 21 is formed on the heterostructure H2 of the GaAs/AlGaAs heterostructure wafer.
[0058] Similar as in FIG. 2, FIG. 6 discloses a further processing step of the process flow. The elements introduced in FIGS. 5A and 5B are denoted by the same reference signs. FIG. 6 discloses flipping one of the two wafer structures, i.e. the first wafer structure A and the second wafer structure B2 so that the first metal film 9 of the first wafer structure A and the second metal film 21 of the second wafer structure B2 face each other and are brought into contact for bonding together the two wafer structures A and B2. Thus, the metal films 9 and 21 form a common bonding medium in FIG. 6. It should be understood that if the first metal film 9 is omitted, i.e. as shown in FIG. 5B, the second metal film 21 directly contacts the substrate 11 of the first wafer structure A. Thereby, it forms the common bonding medium.
[0059] The bonding step as shown in FIG. 6 will then provide the sequence of layers comprised of the AlGasAs etch stop layer 25, the dielectric layer 23, the second metal film 21 and optionally the first metal film 9, as forming a bonded layer stack BLS2. The bonded layer stack BLS2 is sandwiched directly between the first substrate 11 and the second substrate 27.
[0060] FIGS. 7A and 7B disclose, similar to FIGS. 3A and 3B, a further processing step of the process flow. This step follows the bonding step which was disclosed with respect to FIG. 6. As indicated in FIG. 7A, the second substrate 27 of the second wafer structure is removed or stripped. The removal process may be performed using well understood removing or stripping methods such as mechanical lapping followed by wet or dry chemical etching. The removal process is stopped on the AlGaAs etch stop layer 25. Thus, the AlGaAs etch stop layer 25 is exposed in this step. Thereby the bonded layer stack BLS2 is freed, only residing on the first substrate 11. Subsequently, as indicated in FIG. 7B, also the AlGaAs etch stop layer 25 is removed by a selective removal process. The selective removal process may include dry etching or wet etching. Eventually a single-crystal GaAs layer is left behind. The dielectric layer 23 is located on the common bonding medium formed by the metal films 9 and 21, respectively. The dielectric layer 23 and the metal films 21, and if present, 9, may form a reduced or thinned bonded layer stack BLS2.
[0061] FIGS. 8A and 8B disclose a further processing step of the process flow. These steps are similar to the steps discussed with respect to FIGS. 4A and 4B. After the removal or stripping of layers 23 and 25, respectively, as discussed with respect to FIGS. 7A and 7B, the process flow continues by forming a top electrode layer 29 directly on the dielectric layer 23 of the reduced bonded layer stack BLS2, after that layer has been exposed in the previous step, cf. FIGS. 7A and 7B. The top electrode layer 29 is typically formed directly on the surface of the GaAs layer 23. The top electrode layer 29 may be substantially the same as top electrode layer 13 shown in FIGS. 4A and 4B. Here, the surface of the GaAs layer 23 should be understood as being that surface of the GaAs layer 23 facing away from the bonded metal films 9 and 21, respectively, as well as facing away from the first substrate 11.
[0062] FIG. 8B illustrates forming or patterning a plurality of parallel trenches 29T1, 29T2 etc. into the electrode layer 29 and the bonded layer stack underneath the electrode layer. It should be understood that for the purpose of illustrating only two trenches are shown but that one or more than two trenches are also possible. The trenches 29T1 and 29T2 are typically oriented vertically, i.e. perpendicular to the surface of the substrate 11 which faces the metal films. The width of the trenches 29T1 and 29T2 is denoted as W3, W4, respectively. It should be understood that W3 may be equal to W4 but it may be different from W4 as well, such that the trenches may have different widths. Thereby, different two-dimensional structures may be patterned into the top electrodes 29. The trenches 29T1, 29T2 stop on the surface of the substrate 11, though they may also propagate into the base substrate. By forming/patterning the trenches, a plurality of top electrodes 29 are formed directly on the dielectric layer 23 and at the same time a plurality of discrete capacitor structures 29.1, 29.2, 29.3 are formed, each comprising a top electrode 29 directly above the dielectric layer 23 and a metal film directly below the dielectric film, cf. FIG. 9. It should be understood that for illustrational purposes only, FIG. 8B only shows three discrete capacitor structures 29.1, 29.2, and 29.3. However, the number of discrete capacitor structures may be different from three. In particular, it may be n, where n is an integer number and n is larger than or equal to 1. Here, the parallel trenches 29T1, 29T2 extend through the top electrode layer 29 and the bonded layer stack.
[0063] FIG. 9 discloses a further result of the processing steps discussed with respect to the other Figures. In FIG. 9 a capacitor structure 100 is illustrated. The capacitor structure 100 comprises at least one capacitor. In FIG. 9, a plurality of capacitors 100.1, 100.2, . . . , 100.6 are shown which are arranged in an array. The number of capacitors may differ from the number shown in FIG. 9. The manufacturing of the capacitor structure 100 may be performed according to the methods as described with respect to FIGS. 1A-8B, 10A-11B. The capacitors 100.1, 100.2, . . . , 100.6 shown in FIG. 9. They are arranged on a first substrate 33 which is also called a base substrate or a handle substrate. Typically, these are discrete or interconnected capacitors 100.1, 100.2, . . . , 100.6, i.e. each of the capacitors 100.1, 100.2, . . . , 100.6 is substantially similar or the same as the other capacitors of the array. In other words, FIG. 9 illustrates the capacitor structure 100 having the capacitors 100.1, 100.2, . . . , 100.6 being parallel plate capacitors arranged on the first substrate 33. The capacitors 100.1, 100.2, . . . , 100.6 comprise a dielectric structure 35 which is sandwiched between two parallel Al films 43 and 45, respectively, so as to form the parallel-plate capacitors. The dielectric structure 35 may be a single-crystal semiconductor layer or multilayer heterostructure as discussed with respect to FIGS. 1A-8B, 10A-11B, said single-crystal semiconductor layer or multilayer heterostructure being sandwiched between the first electrode layer 43 and the second electrode layer 45. The Al films 43 and 45 may be similar or the same as Al films 13, 9, and 1 in FIGS. 1-4, or Al films 29, 21 and 1 in FIGS. 5-8, respectively. FIG. 9 also shows distances d1, d2, . . . , d5 between each of the capacitors 100.1, 100.2, . . . , 100.6 of the array. Whereas FIG. 9 only depicts a one-dimensional array of capacitors, i.e. the capacitors lined up in a single direction, it should be understood that the capacitors may be arranged two-dimensionally (not shown). The distances d1, d2, . . . d5 may be substantially the same so as to indicate a constant pitch in the direction shown in FIG. 9. However, in principle one or more of the distances d1, d2, . . . , d5 may differ with respect to the other distances between the capacitors.
[0064] FIGS. 10A and 10B illustrate a further embodiment of the present disclosure. FIGS. 10A and 10B disclose elements which were already disclosed in FIGS. 1A, 1B, 2, 3, 4A and 4B, respectively and similar elements are denoted by similar reference signs. However, unlike FIGS. 1A and 2, FIGS. 10A and 10B disclose a patterning step already prior to the bonding step. This patterning step, which may be conceived as pre-patterning comprises patterning one or more trenches into the second metal film 1 and the first metal film 9. FIG. 10 A illustrates that two trenches 47.1 and 47.2 are formed or patterned into the second metal film 1. It should be understood that the number of trenches may be different from two, e.g. the number of trenches may be m where m is an integer greater than or equal to one. Correspondingly, FIG. 10A illustrates a plurality of trenches, here trenches 49.1 and 49.2 formed or patterned into the first metal film 9. Typically, the number of trenches formed in the second and first metal films 1 and 9, respectively, match. Also, the lateral or area size of the trenches formed in the first and second metal films 1 and 9 match.
[0065] FIG. 10B then illustrates a bonding step similar to the bonding step disclosed in FIG. 2. However, in FIG. 10B, the trenches 47.1 and 47.2 of the second metal film 1 should be aligned so as to match the trenches 49.1 and 49.2 of the first metal film 9. Thereby, by the bonding and aligning step, combined cavities 51.1 and 51.2 are formed, as illustrated in FIG. 10B. Thus, similar as in FIG. 2, FIG. 10B discloses flipping one of the two wafer structures, i.e. the first wafer structure A and the second wafer structure B1 so that the first metal film 9 of the first wafer structure A and the second metal film 1 of the second wafer structure B1 face each other and are brought into contact for bonding together the two wafer structures A and B1. This step however, as explained also requires alignment of the trenches in the metal films. Then, the metal films 9 and 1 form a common bonding medium. It should be understood that if the first metal film 9 is omitted, i.e. as shown in FIG. 1B, the second metal film 1 directly contacts the substrate 11 of the first wafer structure A. In such a case, an alignment step may be omitted.
[0066] Typically, a pre-bonding step will also be performed including removing possible surface oxide layers from the first 9 and/or second metal films 1 by mechanical or chemical means, such as ion milling or chemical etching. The pre-bonding will thus ensure the realization of a near-ideal bond interface between first 9 and second 1 metal films.
[0067] The bonding step as shown in FIGS. 10A and 10B will then provide the sequence of layers comprised of the buried oxide layer 5, the dielectric layer 3, the second metal film 1 and optionally the first metal film 9, as forming a bonded layer stack BLS1. The bonded layer stack BLS 1 is sandwiched directly between the first substrate 11 and the second substrate 7.
[0068] The process flow of the embodiment disclosed in FIGS. 10A and 10B may then proceed as disclosed in FIGS. 3A, 3B, and 4A and 4B. The only difference being that the steps discussed with respect to FIG. 4B will open the cavities 51.1 and 51.2, thereby providing the trenches. and a further patterning step may not be needed. Thus, effectively, by opening the cavities 51.1, 51.2, the trenches extend through the top electrode layer 13 and the bonded layer stack.
[0069] FIGS. 11A and 11B illustrate a further embodiment of the present disclosure. FIGS. 11A and 11B disclose elements which were already disclosed in FIGS. 5A, 5B, 6, 7, 8A and 8B, respectively and similar elements are denoted by similar reference signs. However, unlike FIGS. 5A and 6, however similar to FIGS. 10A and 10B, FIGS. 11A and 11B disclose a patterning step already prior to the bonding step. This patterning step, which may be conceived as pre-patterning comprises patterning of one or more trenches into the second metal film 21 and the first metal film 9. FIG. 11 A illustrates that two trenches 57.1 and 57.2 are formed or patterned into the second metal film 21. It should be understood that the number of trenches may be different from two, e.g. the number of trenches may be k where k is an integer greater than or equal to one. Correspondingly, FIG. 11A illustrates a plurality of trenches, here trenches 59.1 and 59.2 formed or patterned into the first metal film 9. Typically, the number of trenches formed in the second and first metal films 21 and 9, respectively, match. Also, the lateral or area size of the trenches formed in the first and second metal films 21 and 9 match.
[0070] FIG. 11B then illustrates a bonding step similar to the bonding step disclosed in FIG. 6. However, in FIG. 11B, the trenches 57.1 and 57.2 of the second metal film 21 should be aligned so as to match the trenches 59.1 and 59.2 of the first metal film 9. Thereby, by the bonding and aligning step, combined cavities 61.1 and 61.2 are formed, as illustrated in FIG. 11B. Thus, similar as in FIG. 6, FIG. 11B discloses flipping one of the two wafer structures, i.e. the first wafer structure A and the second wafer structure B2 so that the first metal film 9 of the first wafer structure A and the second metal film 21 of the second wafer structure B2 face each other and are brought into contact for bonding the two wafer structures A and B2. This step however, as explained also requires alignment of the trenches in the metal films. Then, the metal films 9 and 21 form a common bonding medium. It should be understood that if the first metal film 9 is omitted, i.e. as shown in FIG. 1B, the second metal film 21 directly contacts the substrate 11 of the first wafer structure A. In such a case, an alignment step may be omitted.
[0071] The bonding step as shown in FIGS. 11A and 11B will then provide the sequence of layers comprised of the AlGasAs etch stop layer 25, the dielectric layer 23, the second metal film 21 and optionally the first metal film 9, as forming a bonded layer stack BLS2. The bonded layer stack BLS2 is sandwiched directly between the first substrate 11 and the second substrate 27.
[0072] The process flow of the embodiment disclosed in FIGS. 11A and 11B may then proceed as disclosed in FIGS. 7A, 7B and 8A, 8B. The only difference being that the steps discussed with respect to FIG. 8B will open the cavities 61.1 and 61.2, thereby providing the trenches, and a further patterning step may not be needed. Thus, also here, effectively, by opening the cavities 61.1, 61.2, the trenches extend through the top electrode layer 29 and the bonded layer stack.
[0073] A further modification of the embodiments disclosed above is the following. The bonding process resulting in the structures as illustrated in FIGS. 4A and 4B, as well as FIGS. 8A and 8B, may be repeated by stacking one or more additional crystalline layers on top of the metal layer deposited on the transferred dielectric layer. Stacking means that the additional crystalline layer may be deposited directly onto the top electrode layer. In principle it is also possible to stack more than one crystalline layer on top of each other. The additional crystalline layers may be substantially similar to the dielectric layers 3 and 23 disclosed with respect to the embodiments of FIGS. 4A and 4B, as well as FIGS. 8A and 8B, respectively. The metal layer is the top electrode layer 9, 29 as disclosed above. In this respect, it is also possible to add further electrode layers between these additional crystalline layers. For example, one additional crystalline layer provided directly on the top electrode layer 9, 29 as disclosed above may then have a further electrode layer directly on this additional layer (not shown). This stacking of dielectric layers and electrode layers may be repeated further. Similar to the embodiments disclosed above, the patterning of trenches so as to arrive at structures corresponding to those shown in FIGS. 4B and 8B, respectively may be performed either at the end of the stacking process or before. In essence, providing additional crystalline layers stacked onto the electrode layers 9, 29 will then provide the possibility for multi-layer wiring for in-plane or three dimensions capacitor arrays.
[0074] The crystalline capacitor technology as disclosed herein will have a secondary benefit of enabling multi-layer wiring. Currently, the best performance is achieved with devices fabricated using a single metal layer. This configuration greatly restricts signal routing. For high density integrated systems or integrated circuits, in particular superconducting quantum integrated circuits, multiple wiring layers are needed to allow signals to cross and enable arbitrary connections between discrete elements of a qubit array. Conventional multi-layer nanofabrication operates by depositing alternating layers of metal and dielectric thin films such as SiO.sub.2. Unfortunately, SiO.sub.2 thin films have a rather large loss tangent of >10.sup.3, and thus cannot be used near qubits or other on-chip structures such as coupling resonators that require the lowest possible intrinsic losses. Transitioning from a 1-dimensional chain of qubits to a 2-dimensional array requires the ability to have signal lines that cross each other near the qubit structures. As SiO.sub.2 crossovers are very lossy they may not be usable in such an architecture. A low-loss crystalline dielectric layer, with a loss angle or loss tangent below 10.sup.6, enables more complex multi-layer connectivity which will be important for scaling to larger qubit arrays.
