Digital Signal Processor and Method

Abstract

A digital signal processor according to an embodiment comprises a processing stage. The processing stage is configured to receive Cartesian coordinates of a vector in a floating point format and to output polar coordinates of the vector in a floating point format. The processing stage comprises a first electronic circuit configured to iteratively implement, timed by a clock signal, a CORDIC algorithm in a floating point format.

Claims

1. A digital signal processor comprising: a processing stage configured to receive Cartesian coordinates of a vector in a floating point format and to output polar coordinates of the vector in a floating point format, the processing stage comprising a first electronic circuit configured to iteratively implement, timed by a clock signal, a CORDIC algorithm in a floating point format.

2. The digital signal processor according to claim 1, wherein the processing stage is configured to, during the implementation of the CORDIC algorithm, perform divisions by integer powers of 2, of data expressed in a floating point format, by subtracting for each division, the integer power corresponding to an exponent of the data.

3. The digital signal processor according to claim 1, wherein the processing stage is configured to implement one iteration of the CORDIC algorithm per clock signal cycle.

4. The digital signal processor according to claim 1, wherein the processing stage further comprises a counter configured to deliver a current value i, wherein the current value i corresponds to a rank of a current iteration of the CORDIC algorithm, and wherein the first electronic circuit comprises: a first circuit input, a second circuit input, and a third circuit input; a first divider module comprising an input connected to the second circuit input and a first subtractor configured to subtract the current value i of the counter from an exponent of a data item present at the second circuit input, an output of the first subtractor delivering the data item present at the second circuit input divided by 2i; a second divider module comprising an input connected to the first circuit input and a second subtractor configured to subtract the current value i of the counter from an exponent of a data item present at the first circuit input, an output of the second subtractor delivering the data item present at the first circuit input divided by 2i; a first adder/subtractor comprising a first input connected to the first circuit input and a second input connected to the output of the first subtractor; a second adder/subtractor comprising a first input connected to the second circuit input and a second input connected to the output of the second subtractor; and a third adder/subtractor comprising a first input connected to the third circuit input and a second input for receiving an angular pitch value associated with the current value i of the counter, wherein a configuration of each of the first, second, and third adder/subtractor as an adder or as a subtractor is defined by a sign of the data item present at the second circuit input.

5. The digital signal processor according to claim 4, wherein the processing stage further comprises a controller configured to: at the beginning of a first iteration of the CORDIC algorithm, deliver an initial abscissa data item representative of the abscissa of the vector on the first circuit input, an initial ordinate data item representative of the ordinate of the vector on the second circuit input, and an initial angular value on the third circuit input; increment the counter at each subsequent new iteration of the CORDIC algorithm; and deliver on the second input of the third adder/subtractor, the angular pitch value associated with the current value i of the counter.

6. The digital signal processor according to claim 5, wherein the controller is further configured to deliver, at the end of a current iteration of the CORDIC algorithm, an output value of the first adder/subtractor on the first circuit input, an output value of the second adder/subtractor on the second circuit input, and an output value of the third adder/subtractor on the third circuit input.

7. The digital signal processor according to claim 1, wherein the processing stage is configured to implement two iterations of the CORDIC algorithm per clock signal cycle.

8. The digital signal processor according to claim 7, wherein the processing stage further comprises a second electronic circuit having a structure similar to that of the first electronic circuit, the second electronic circuit connected downstream of the first electronic circuit, the first electronic circuit being configured to implement during a clock cycle, a current iteration of the CORDIC algorithm, the second electronic circuit being configured to implement during the clock cycle, a next iteration of the CORDIC algorithm.

9. The digital signal processor according to claim 8, wherein the first electronic circuit is configured to implement iterations of even ranks of the CORDIC algorithm, and wherein the second electronic circuit is configured to implement iterations of odd ranks of the CORDIC algorithm.

10. The digital signal processor according to claim 8, wherein the processing stage further comprises a counter configured to deliver a current value i, wherein the current value i corresponds to half of a rank of a current iteration of an even rank of the CORDIC algorithm, and wherein the first electronic circuit comprises: a first circuit input, a second circuit input, a third circuit input; a first divider module comprising an input connected to the second circuit input and a first subtractor configured to subtract a value 2i from an exponent of a data item present at the second circuit input, an output of the first subtractor delivering the data item present at the second circuit input divided by 2.sup.2i; a second divider module comprising an input connected to the first circuit input and a second subtractor configured to subtract the value 2i from an exponent of a data item present at the first circuit input, an output of the second subtractor delivering the data item present at the first circuit input divided by 2.sup.2i; a first adder/subtractor comprising a first input connected to the first circuit input and a second input connected to the output of the first subtractor; a second adder/subtractor comprising a first input connected to the second circuit input and a second input connected to the output of the second subtractor; and a third adder/subtractor comprising a first input connected to the third circuit input and a second input to receive an angular pitch value associated with the value 2i, wherein a configuration of each of the first, second, and third adder/subtractor as an adder or as a subtractor is defined by a sign of the data item present at the second circuit input.

11. The digital signal processor according to claim 10, wherein: the first input of the first adder/subtractor of the second circuit is connected to an output of the first adder/subtractor of the first circuit; the first input of the second adder/subtractor of the second circuit is connected to an output of the second adder/subtractor of the first circuit; the first input of the third adder/subtractor of the second circuit is connected to an output of the third adder/subtractor of the first circuit; the input of the first divider module of the second circuit is connected to the output of the second adder/subtractor of the first circuit, and the first subtractor of the first divider module of the second circuit is configured to subtract a value 2i+1 from an exponent of a data item present at the output of the second adder/subtractor of the first circuit of circuit, the output of the first divider module of the second circuit delivering the data item present at the output of the second adder/subtractor of the first circuit divided by 2.sup.2i+1; the input of the second divider module of the second circuit is connected to the output of the first adder/subtractor of the first circuit, and the second subtractor of the second divider module of the second circuit is configured to subtract the value 2i+1 an the exponent of a data item present at the output of the first adder/subtractor of the first circuit of circuit, the output of the second divider module of the second circuit delivering the data item present at the output of the first adder/subtractor of the first circuit of circuit divided by 2.sup.2i+1; the second input of the third adder/subtractor of the second circuit is configured to receive an angular pitch value associated with the value 2i+1; and wherein a configuration of each of the first, second, and third adder/subtractor of the second circuit as an adder or as a subtractor is defined by a sign of the data item present at the output of the second adder/subtractor of the first circuit.

12. The digital signal processor according to claim 11, wherein the processing stage further comprises a controller configured to: at the beginning of a first iteration of the CORDIC algorithm, deliver an initial abscissa data item representative of the abscissa of the vector on the first circuit input, an initial ordinate data item representative of the ordinate of the vector on the second circuit input, and an initial angular value on the third circuit input; increment the counter at each subsequent new iteration of the CORDIC algorithm; deliver on the second input of the third adder/subtractor of the first circuit, an angular pitch value associated with the value 2i; deliver on the second input of the third adder/subtractor of the second circuit, an angular pitch value associated with the value 2i+1; and deliver, at the end of the iteration of an odd rank following an iteration of an even rank of the CORDIC algorithm, an output value of the first adder/subtractor of the second circuit on the first circuit input, an output value of the second adder/subtractor of the second circuit on the second circuit input, and an output value of the third adder/subtractor of the second circuit on the third circuit input.

13. The digital signal processor according to claim 12, wherein the processing stage further comprises an initialization electronic circuit, controlled by the controller, and configured to deliver the initial abscissa data item, the initial ordinate data item, and the initial angular value from the abscissa and the ordinate of the vector.

14. The digital signal processor according to claim 13, wherein the initialization circuit is configured to deliver, as the initial abscissa data item, the initial ordinate data item, and the initial angular value, respectively: the abscissa of the vector, the ordinate of the vector, and a zero angular value, in response to the abscissa of the vector being positive; the opposite of the ordinate of the vector, the abscissa of the vector, and an angular value equal to −π/2, in response to the abscissa and the ordinate of the vector being negative; and the ordinate of the vector, the opposite of the abscissa of the vector and an angular value equal to +π/2, in response to the abscissa of the vector being negative and the ordinate of the vector being positive.

15. A servo system comprising: a servo loop integrating the digital signal processor according to claim 1; and an electric motor connected to the servo-control loop.

16. A digital signal processor comprising: an initialization circuit configured to receive Cartesian coordinates of a vector in a floating point format, and to deliver an initial value of polar coordinates of the vector in a floating point format; a first electronic circuit configured to receive the initial value of the polar coordinates of the vector, to implement a first iteration of a first even rank of a CORDIC algorithm in a floating point format, and to output a first approximation of the polar coordinates of the vector in a floating point format; and a second electronic circuit configured to receive the first approximation of the polar coordinates of the vector, to implement an iteration of an odd rank of the CORDIC algorithm in a floating point format, and to output a second approximation of the polar coordinates of the vector in a floating point format.

17. The digital signal processor of claim 16, wherein the first electronic circuit has a similar structure as the second electronic circuit.

18. The digital signal processor of claim 16, wherein the first electronic circuit is further configured to receive the second approximation of the polar coordinates of the vector, to implement a second iteration of a second even rank of the CORDIC algorithm in a floating point format, and to output a third approximation of the polar coordinates of the vector in a floating point format.

19. A method comprising: receiving Cartesian coordinates of a vector in a floating point format; and iteratively implementing a CORDIC algorithm in the floating point format to generate polar coordinates of the vector in the floating point format, the iterative implementation being performed synchronously with a clock signal; and outputting the polar coordinates of the vector in the floating point format.

20. The method according to claim 19, further comprising using the polar coordinates of the vector in the floating point format to implement a servo-control of an electric motor.

21. The method according to claim 19, wherein implementing the CORDIC algorithm comprises performing divisions by integer powers of 2 of data expressed in a floating point format by subtracting for each division, the integer power corresponding to an exponent of the data.

22. The method according to claim 19, wherein implementing the CORDIC algorithm comprises implementing two iterations of the CORDIC algorithm per clock signal cycle.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Other advantages and features will appear on examining the detailed description of embodiments and implementations, which are in no way limiting, and of the appended drawings in which:

[0057] FIG. 1 schematically illustrates an example of a digital signal processor, in accordance with some embodiments;

[0058] FIG. 2 schematically illustrates a processing stage of a digital signal processor, in accordance with some embodiments;

[0059] FIG. 3 illustrates a divider module of a processing stage, in accordance with some embodiments;

[0060] FIG. 4 schematically illustrates a processing stage of a digital signal processor, in accordance with some other embodiments;

[0061] FIG. 5 schematically illustrates an initialization circuit of a digital signal processor, in accordance with some other embodiments; and

[0062] FIG. 6 schematically illustrates a system integrating a digital signal processor, in accordance with some embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0063] FIG. 1 schematically illustrates an example of a digital signal processor DSP adapted to implement iterations of a CORDIC algorithm on floating point data.

[0064] In particular, the digital signal processor DSP allows performing changes in reference frames by transforming Cartesian coordinates into polar coordinates by the CORDIC algorithm.

[0065] To this end, the digital signal processor DSP comprises a processing stage ET_float dedicated to the implementation of the CORDIC algorithm and configured to process floating point data, and a clock generator GEN_CLK for generating a clock signal CLK intended to clock the processing stage ET_float.

[0066] By convention, the Cartesian coordinates comprise an abscissa ABS and an ordinate ORD, and the polar coordinates comprise a modulus MOD and an angle value ANG measured relative to the origin.

[0067] The processing stage ET_float is configured to receive the Cartesian coordinates ABS, ORD of a vector in a floating point format and to process successive iterations of the algorithm so as to deliver the polar coordinates MOD, ANG of the vector in a floating point format.

[0068] For this, the processing stage ET_float stage includes at least one first electronic circuit C1 capable of processing data in a floating point format.

[0069] The circuit C1 is configured to implement, one by one, timed by a clock signal CLK, the iterations of the CORDIC algorithm.

[0070] Generally, each iteration of the algorithm comprises divisions by integer powers of 2.

[0071] Advantageously, as will be seen in more detail below, the processing stage ET_float, and in particular the first circuit C1, is configured to perform divisions by integer powers of 2 by not using conventional dividers, but by simply subtracting the exponent of the floating point data item to be divided by the value of the corresponding power of 2.

[0072] FIG. 2 schematically illustrates an example of the processing stage ET_float comprising herein the first circuit C1.

[0073] The processing stage ET_float further comprises a controller MC to monitor and manage each iteration, a counter CPT to indicate the ranks of the successive iterations of the algorithm and an initialization electronic circuit CE_init to provide the first circuit with initial data to be processed during the first iteration.

[0074] The counter CPT is intended for example to be incremented timed by the clock signal CLK, and to deliver a current value i corresponding to the rank of the iteration during processing in the first circuit C1.

[0075] The processing stage ET_float comprises a memory MM adapted to store a set of angular pitch values al characteristic of the CORDIC algorithm. The angular pitch values al are calculated in advance and stored in the memory MM. Alternatively, it is possible for the memory MM to be located outside the processing stage ET_float.

[0076] The first circuit C1 is configured to implement a single iteration of the CORDIC algorithm per clock signal cycle CLK.

[0077] For this purpose, the first electronic circuit C1 comprises three blocks, a first block to process a data item X and deliver a data item X′, a second block to process the data item Y and deliver the data item Y′ and a third block to process the data item α and deliver the data item α′.

[0078] The first electronic circuit C1 comprises, in the first block, a first divider module MD1_C1 and a first adder/subtractor A1_C1, in the second block, a second divider module MD2_C1 and a second adder/subtractor A2_C1, and in the third block, a third adder/subtractor A3_C1.

[0079] The first circuit C1 is configured so that after a predetermined number of iterations, the data item X′ is substantially equal to the modulus of the vector in a polar reference frame and the data item α is an approximation of the angle of the vector with the origin in the polar reference frame.

[0080] This number of iterations can be at most equal to 24 to obtain a maximum accuracy, but can be reduced to ten to obtain a lower accuracy.

[0081] Concerning the inputs of the first circuit C1, they include a first circuit input E1_C1 intended to receive the data item X, a second circuit input E2_C1 intended to receive the data item Y, a third circuit input E3_C1 intended to receive the data item α, and a fourth circuit input E4_C1 intended to receive the angular pitch α.sub.i.

[0082] Concerning the outputs of the first circuit C1, they include a first circuit output S1_C1 intended to deliver the data item X′, a second circuit output S2_C1 intended to deliver the data item Y′, and a third circuit output S3_C1 intended to deliver the data item α′.

[0083] Concerning the divider modules of the first circuit C1, the first divider module MD1_C1 is configured to subtract the current value i of the counter from the exponent of the data item Y, so as to deliver the value Y/2.sup.i.

[0084] The first divider module MD1_C1 has an input E1MD1_C1 connected to the second circuit input E2_C1 and intended to receive the data item Y, an input E2MD1_C1 connected to the counter CPT and intended to receive the value i of the current iteration, and an output SMD1_C1 connected to a second input E2A1_C1 of the first adder/subtractor A1_C1 and intended to deliver the data item Y divided by 2.sup.i.

[0085] FIG. 3 illustrates in more detail the first divider module MD1_C1 which comprises a first subtractor S10_C1.

[0086] The data item Y conventionally comprises in floating point format, bits forming an exponent Y_exp and bits forming a mantissa Y_mant.

[0087] The first divider module comprises a data bus to circulate the bits of the data item Y.

[0088] The bus is separated into two branches, a first branch configured to circulate the bits of the mantissa Y_mant of the data item Y between the first input E1MD1_C1 and the output SMD1_C1 of the first divider module MD1_C1, and a second branch configured to circulate the bits from the exponent Y_exp of the data item Y to the first subtractor S10-C1.

[0089] In this regard, the first subtractor S10_C1 comprises a first input connected to the first input E1MD1_C1 of the first divider module MD1_C1 to receive the exponent Y_exp of the data item Y.

[0090] The first subtractor S10_C1 also comprises a second input connected to the second input E2MD1 of the first divider module MD1_C1 intended to receive the value of rank i of the current iteration in the first circuit C1.

[0091] The first subtractor S10_C1 is configured to subtract from the exponent of data item Y, the value of the rank i of the current iteration.

[0092] This subtraction in the first subtractor S10_C1, is as illustrated in FIG. 3, implemented by isolating the exponent and through carrying out an unsigned subtraction of the quantity i of the bits constituting the exponent.

[0093] The first subtractor S1_C1 further comprises an output connected to the output SMD1_C1 of the first divider module MD1_C1 to deliver the result Y_exp-i of the subtraction.

[0094] The output SMD1_C1 of the first divider module MD1_C1 therefore delivers the data item Y/2.sup.i having as exponent Y_exp-i and as mantissa Y_mant.

[0095] The second divider module MD2_C1 is configured to subtract the current value i of the counter from the exponent of the data item X, so as to deliver the data item X/2.sup.i.

[0096] Referring back to FIG. 1, second divider module MD2_C1 has an input E1MD2_C1 connected to the first circuit input E1_C1 and intended to receive the data item X, an input E2MD2_C1 connected to the counter CPT and intended to receive the value i of the current iteration, and an output SMD2_C1 connected to a second input E2A2_C1 of the second adder/subtractor A2_C1 and intended to deliver the data item X divided by 2′.

[0097] The structure and operation of the second divider module MD2_C1, which comprises in particular a second subtractor, are similar to those of the first divider module MD1_C1 described in relation to FIG. 3.

[0098] The first adder/subtractor A1_C1 has a first input E1A1_C1 connected to the first circuit input E1_C1, a second input E2A1_C1 connected to the output of the first divider module MD1_C1, and a third input E3A1_C1 intended to receive the most significant bit MSB_Y of the data item Y.

[0099] The first adder/subtractor A1_C1 also has an output SA1_C1 connected to the first circuit output S1_C1 and intended to deliver the data item X′, which is the output value of the second block for the current iteration.

[0100] The second adder/subtractor A2_C1 has a first input E1A2_C1 connected to the second circuit input E2_C1, a second input E2A2_C1 connected to the output of the second divider module MD2_C1, which also happens to be the output of the second subtractor, and a third input E3A2_C1 intended to receive the most significant bit MSB_Y of the data item Y.

[0101] The second adder/subtractor A2_C1 also has an output SA2_C1 connected to the second circuit output S2_C1 and intended to deliver the data item Y′, which is the output value of the second block for the current iteration.

[0102] The third adder/subtractor A3_C1 has a first input E1A3_C1 connected to the third circuit input E3_C1, a second input E2A3_C1 connected to the fourth circuit input E4_C1 intended to receive the angular pitch value α.sub.i associated with the current value of the counter CPT, and a third input E3A3_C1 intended to receive the most significant bit MSB_Y of the data item Y.

[0103] The third adder/subtractor A3_C1 also has an output SA3_C1 connected to the third circuit output S3_C1 and intended to deliver the data item α′, which is the output value of the third block for the current iteration.

[0104] The configuration of each adder/subtractor as an adder or as a subtractor depends on the most significant bit MSB_Y representing the sign of the data item Y.

[0105] For example, if the most significant bit MSB_Y of the data item Y is equal to 1, the corresponding adder/subtractor performs a subtraction and if the most significant bit MSB_Y of the data item Y is equal to 0 then this adder/subtractor performs an addition.

[0106] Thus the first adder/subtractor C1 is configured to add the data item Y to the data item X divided by 2.sup.i if the sign of the data Y is positive, or to subtract the data item Y from the data item X divided by 2.sup.i if the sign of the data Y is negative.

[0107] The second adder/subtractor A2_C1 is configured to subtract the data item X divided by 2.sup.i from the data item Y if the sign of the data item Y is positive, or to add the data item Y to the data item X divided by 2.sup.i if the sign of the data Y is negative.

[0108] The third adder/subtractor A3_C1 is configured to add the angular pitch value α.sub.i of the current iteration to the data item α if the sign of the data item Y is positive, or to subtract the angular pitch value α.sub.i of the current iteration from the data item α if the sign of the data item Y is negative.

[0109] The controller MC is configured to control an initialization circuit CE_init so as to deliver to the first circuit C1 an initial data triplet at the beginning of the first iteration of the algorithm.

[0110] The initial data triplet comprises an initial abscissa X_init, representative of the abscissa of the vector, delivered on the first circuit input E1_C1, an initial ordinate data item Y_init representative of the ordinate of the vector, delivered on the second circuit input E2_C1, and an initial angular value α_init delivered on the third circuit input E3_C1.

[0111] In the description relating to FIG. 5, the initialization circuit CE_init and the obtaining of the initial data triplet X_init, Y_init, α_init will be discussed in more detail.

[0112] The controller MC is also configured to control the incrementation of the counter CPT at each new iteration of the CORDIC algorithm.

[0113] The controller MC is further configured to control the reading in the memory MM of the angular pitch value α.sub.i associated with the current value of the counter CPT and deliver this value to the second input E2A3_C1 of the third adder/subtractor A3_C1.

[0114] The controller MC is configured to control a loopback of the values obtained at the output of each block to the respective inputs thereof at the end of each cycle of the clock signal (except the last), that is to say in an embodiment, after each iteration (except the last) of the CORDIC algorithm.

[0115] In particular, the controller MC is configured to loop back, at the end of a current iteration, the output value X′ of the first adder/subtractor A1_C1 on the first circuit input E1_C1, the output value Y′ of the second adder/subtractor A2_C1 on the second circuit input E2_C1, and the output value α′ of the third adder/subtractor A3_C3 on the third circuit input E3_C1.

[0116] At the end of the last iteration: the data item X′ is representative of the module of the vector (provided that the obtained magnitude is the modulus of the initial vector multiplied by a constant K that depends on the number of iterations), the data a′ is representative of the angle thereof, and the data Y′ is zero or almost zero.

[0117] More specifically K is equal to 1.646760255 for 24 iterations, and more generally K is equal to the product (1+2.sup.−0).sup.1/2.Math.(1+2.sup.−2).sup.1/2 . . . (1+2.sup.−(n-2)).sup.1/2.

[0118] FIG. 4 schematically illustrates an embodiment in which the processing stage ET_float is configured to process two iterations of the CORDIC algorithm per clock signal cycle CLK.

[0119] This is possible by the presence of the divider modules which allow performing the divisions by integer powers of 2 without using dividers, which reduces the length of the critical path of the processing stage.

[0120] This particularly advantageous embodiment allows determining the modulus and the angle of the vector more quickly.

[0121] For example, the frequency of the clock signal CLK may be in the range of 250 MHz in a 40 nm CMOS technology.

[0122] Thus, the processing stage ET_float comprises the first circuit C1 as described in relation to the preceding figures and a second circuit C2, of a structure similar to the first electronic circuit C1, connected downstream of the first circuit C1. As shown in FIG. 4, in this context, circuits have similar structures when they include the same elements connected in the same manner.

[0123] During a cycle of the clock signal CLK, the first electronic circuit C1 is intended to implement a current iteration of even rank of the CORDIC algorithm and the second electronic circuit C2 is intended to implement the next iteration of odd rank, always during the same clock signal cycle CLK.

[0124] More specifically, the counter CPT is again incremented, timed by the clock signal CLK, by the controller MC, but its current value i corresponds to half of the rank 2i of a current iteration of even rank of the algorithm.

[0125] Thus the counter CPT ultimately only counts half of the requested number of iterations.

[0126] The first iteration is the even iteration of rank 0.

[0127] The first circuit C1 implements the current iteration of rank 2i in the manner described in relation to FIGS. 2 and 3, with the difference that the first circuit comprises herein a module MDD1 receiving the value i from the counter CPT and delivering the value 2i at the inputs E2MD1_C1 and E2MD2_C1.

[0128] Thus the modules MD1_C1 and MD2_C1 perform the divisions by 2.sup.2i of the data respectively present at the input of these two modules.

[0129] A particularly simple manner to implement the multiplication by 2 performed in the module MDD1, can consist in delivering the number i using an initial word of I bits on a bus of I bits, for example 5 bits, and to connect between the output of the module MDD1 and the inputs E2MD1_C1 and E2MD2_C1, a bus of I+1 bits, for example 6 bits, so as to present to these inputs a word of I+1 bits whose least significant bit is forced to 0 and whose I other bits correspond to the I bits of the initial word representing the number i.

[0130] Moreover, the controller MC is configured to control the reading in the memory MM of the angular pitch value α.sub.2i associated with the value 2i and deliver this value on the second input E2A3_C1 of the third adder/subtractor A3_C1.

[0131] The second circuit C2 implements the next iteration of rank 2i+1 in the same manner as the first circuit implements the iteration of rank 2i, with the difference that divisions by 2.sup.2i+1 are this time performed by the second circuit C2 instead of the divisions by 2.sup.2i performed by the first circuit C1.

[0132] The majority of the elements of the second circuit C2 are similar to the elements of the first circuit C1, in particular from the point of view of their structure and their operation.

[0133] Thus, for the sake of brevity, the references associated with the elements of the second circuit C2 are similar to the references associated with the elements of the first circuit C1.

[0134] The distinction between the references of the first and second circuits lies in the mention “_C1” to refer to the first circuit and in the mention “_C2” to refer to the second circuit.

[0135] Structurally, as indicated above, the second circuit C2 is connected downstream of the first electronic circuit C1.

[0136] In particular, the first circuit input E1_C2 of the second circuit C2 is connected to the first circuit output S1_C1 of the first circuit C1 delivering the data item X′.

[0137] The second circuit input E2_C2 of the second circuit C2 is connected to the second output S2_C1 of the first circuit C1 delivering the data item Y′.

[0138] The third circuit input of circuit E3_C2 of the second circuit C2 is connected to the third circuit output S3_C1 of the first circuit C1 delivering the data α′.

[0139] Unlike the first circuit C1, the second circuit comprises herein a module MDD2 receiving the value i from the counter CPT and delivering the value 2i+1 to the inputs E2MD1_C2 and E2MD2_C2.

[0140] Thus the modules MD1_C2 and MD2_C2 perform the divisions by 2.sup.2i+1 of the data respectively present at the input of these two modules.

[0141] A particularly simple manner for implementing the multiplication by 2 increased by 1, performed in the module MDD2, can consist in delivering the number i using the initial word of I bits on the bus of I bits, for example 5 bits, and connecting between the output of the module MDD2 and the inputs E2MD1_C2 and E2MD2_C2, a bus of I+1 bits, for example 6 bits, so as to present to these inputs a word of I+1 bits whose least significant bit is forced to 1 and whose I other bits correspond to the I bits of the initial word representing the number i.

[0142] Thus, in the first block of the second circuit C2, the first divider module MD1_C2 is configured to subtract the value 2i+1, from the exponent of the data item Y′.

[0143] Consequently, the output of the first divider module MD1_C2 of this second circuit delivers the data item Y′ divided by 2.sup.2i+1.

[0144] Then, the output of the first adder/subtractor A1_C2 of the second circuit C2 delivers the data X″ which is the output value of the first block of the second circuit C2 at the iteration of rank 2i+1.

[0145] In parallel, concerning the second block of the second circuit C2, the second divider module MD2_C2 is configured to subtract the value 2i+1, from the exponent of the data item X′.

[0146] Consequently, the output of the second divider module MD2_C2 of this second circuit delivers the data item X′ divided by 2.sup.2i+1.

[0147] Then, the output of the second adder/subtractor A2_C2 of the second circuit C2 delivers the data item Y″ which is the output value of the second block of the second circuit C2 at the iteration of rank 2i+1.

[0148] Concerning the third block of the second circuit C2, the second input of the third adder/subtractor A3_C2 is intended to receive an angular pitch value α.sub.2i+1 associated with the value 2i+1.

[0149] Consequently, the output of the third adder A3_C2 of the second circuit C2 delivers the data α″ which is the output value of the third block of the second circuit C2 at the iteration of rank 2i+1.

[0150] In this embodiment, the controller MC is configured to control the reading of the angular pitch value α.sub.2i+1 associated with the iteration of rank 2i+1, with a view to its delivery on the fourth circuit input of the second circuit C2.

[0151] Moreover, the controller MC is then configured to loop back outputs of the blocks of the second circuit C2 on respective inputs of the blocks of the first circuit C1.

[0152] In particular, the controller MC is configured to deliver at the end of the iteration of rank 2i+1, the output value X″ of the second block of the second circuit C2 on the first circuit input E1_C1, the output value Y″ of the second block of the second circuit C2 on the second circuit input E2_C1, and the output value α″ of the third block of the second circuit on the third circuit input E3_C1.

[0153] At the end of the last iteration, the data X″ is representative of the module of the vector (within the constant K), the data α″ is representative of the angle thereof and the data Y″ is zero or almost zero.

[0154] FIG. 5 schematically illustrates the initialization electronic circuit CE_init, mentioned above in relation to FIGS. 2 and 4.

[0155] The initialization circuit is configured to generate, from the abscissa ABS and the ordinate ORD of the vector, an initial data triplet comprising, on the one hand, an initial vector formed of the initial abscissa data item X_init and of the initial ordinate data item Y_init and on the other hand, the initial angular value α_init.

[0156] The generation of the data triplet by the initialization electronic circuit CE_init is controlled by the controller MC (see FIGS. 2 and 4).

[0157] Concerning the initial vector, the initialization circuit CE_init is configured to perform a rotation if the Cartesian vector whereon it is intended to change the reference frame is located in the half-plane of the negative abscissas.

[0158] Typically, for Cartesian vectors located in this half-plane, the CORDIC algorithm does not converge and it is therefore advantageous to generate an initial vector located in the plane of the positive abscissas, obtained by a rotation of

[00004]$-\frac{\pi }{2}$

or of

[00005]$\frac{\pi }{2}$

of the Cartesian vector depending on whether the sign of the ordinate ORD is negative or positive.

[0159] The initial angular value α_init then takes respectively either the value

[00006]$-\frac{\pi }{2}$

or the value

[00007]$\frac{\pi }{2},$

always according to the sign of the ordinate ORD, which allows taking into account this initial rotation of the Cartesian vector.

[0160] If, on the contrary, the Cartesian vector is located in the half-plane of the positive abscissas, then the initial vector is equal to the Cartesian vector and the initial angular value α_init is set to zero.

[0161] FIG. 6 schematically illustrates a servo system SYS integrating a monitoring unit UC, for example a microcontroller such as that marketed by the company STMicroelectronics under the reference STM32, connected to an electric motor M.

[0162] The monitoring unit UC comprises a processing unit CPU and a digital signal processor DSP described above to implement a servo-control of the electric motor M.

[0163] For the servo-control of the motor M, it may for example be advantageous to perform changes in reference frame to transform vector Cartesian coordinates into polar coordinates.

[0164] In particular, these changes in reference frame are all the more advantageous if they are implemented quickly, for example if they concern the rotation of the motor, and even more so if the speed of rotation of the motor is significant.

[0165] Thus, it is advantageous for the servo loop to implement the digital signal processor DSP as described above, such as in the embodiments of FIG. 2 or 4, in order to quickly implement iterations of the CORDIC algorithm.