Non-uniform sampling implementation

Abstract

This application discloses an implementation of a novel non-uniform sampling technique for a burst type signal. A simple circuit is developed that implements an analog computation of a complex digital calculation to skip the unnecessary samples and choose the optimum next sample. Then the optimum samples are selected for further processing which results in overall cost and power consumption reduction.

Claims

1. An analog circuit to perform a non-uniform sampling by eliminating a redundant sample comprising: a first sample and hold circuit that continuously takes a sample from an analog signal; a second sample and hold circuit that continuously takes said sample from said analog signal with a clock delay; a third sample and hold circuit that holds a sample that is not eliminated for further processing; a sample elimination circuit comprising: a first analog comparator to subtract a value of said sample from said first sample and hold circuit from a value of the sample from said second sample and hold circuit and produce a first output; a second analog comparator to subtract the value of said sample from said third sample and hold circuit from the value of the sample from the second sample and hold circuit and produce a second output; an eliminate sample counter that counts an eliminated sample and is incremented when one of said samples is eliminated; an analog scaling circuit to divide the second output of said second analog comparator by a number of said eliminated samples provided by said eliminate sample counter and produce a third output; a third analog comparator to subtract the first output from said third output to produce a fourth output; an absolute value amplifier to amplify the fourth output and produce a fifth output; a forth comparator to compare said fifth output with a reference threshold value to decide if the sample from said second sample and hold circuit can be eliminated or kept and sent to said third sample and hold circuit.

2. The analog circuit explained in claim 1, wherein said first analog comparator and the second analog comparator are voltage to current converters.

3. The analog circuit explained in claim 1, wherein said analog scaling circuit is a current splitter which scales down said second output proportional to the number of said eliminated samples and is represented by an array of transistors.

4. The analog circuit explained in claim 3, wherein said analog scaling circuit that divides said second output by the number of said eliminated samples uses said eliminate sample counter's bits at gates of said array of transistors and the drains of said array of transistors are biased at a reference voltage.

5. The analog circuit explained in claim 1, wherein said fourth comparator is a slope change detector circuit that uses said reference threshold value as a first input and the fifth output as a second input and indicates if the sample needs to be eliminated or kept and sent to said third sample and hold circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrate Nyquist sampling

(2) FIG. 2 shows low IF sampling

(3) FIG. 3 shows sub-harmonic IF sampling

(4) FIG. 4 illustrate detail of sampling frequency for sub-harmonic IF sampling

(5) FIG. 5 shows the effect of aliasing due to under sampling

(6) FIG. 6 shows the spectrum of a burst type analog signal

(7) FIG. 7 illustrates a sampled sinusoidal signal

(8) FIG. 8 depicts an over sampled bust type signal

(9) FIG. 9 shows the required samples for a burst type signal

(10) FIG. 10 illustrate derivative of consecutive samples

(11) FIG. 11 depicts how to reduce the number of uniform samples

(12) FIG. 12 shows the case when the slop of consecutive samples has minimum change

(13) FIG. 13 illustrate scenario I of a sampled analog signal

(14) FIG. 14 illustrate scenario II of a sampled analog signal

(15) FIG. 15 shows an implementation of 3 sample/hold scheme

(16) FIG. 16 depicts block diagram of the decision circuit

(17) FIG. 17 depicts non-uniform sampling circuit diagram

(18) The drawings referred to in this description should be understood as not being drawn to scale except if specifically noted.

DESCRIPTION OF EMBODIMENTS

(19) Reference will now be made in detail to embodiments of the present technology, examples of which are illustrated in the accompanying drawings. While the technology will be described in conjunction with various embodiment(s), it will be understood that they are not intended to limit the present technology to these embodiments. On the contrary, the present technology is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the various embodiments as defined by the appended claims.

(20) Furthermore, in the following description of embodiments, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, the present technology may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present embodiments.

(21) FIG. 7 depicts an over sampled signal 100. A sinusoidal signal 101 is over sampled and represented by samples 102. According to Nyquist theorem for sinusoidal signal 101 only two samples per period is requires. Therefore circled samples 103 for sinusoidal signal 101 are redundant.

(22) In one embodiment of over sampled signal 100, the redundant samples 103 can be identified and removed without loss of signal fidelity.

(23) FIG. 8 illustrate a sampled burst signal 200. The burst signal comprises of periodic bursts 201. The burst signal 200 is sampled based on Nyquist theorem and represented by samples 202. It is clear from periodic burst signal 201 that there are considerable redundant samples 202 during one period of the burst both in the flat part of the period and during the burst.

(24) FIG. 9 illustrate a sampled burst signal 300. The burst 301 does not require multiple samples for most of its period except during the time it burst. There are three sample points 302, 303, and 304 in burst 301 that carry the required information for continued processing.

(25) In one embodiment of burst signal 300, sample 304 at the start of burst 301, sample 302 at the peak of the burst 301, and sample 303 at the end of the burst 301 are sufficient for further processing of a burst signal.

(26) FIG. 10 depicts consecutive sample pairs derivative 400. Derivative of two samples 401 and 402 results in slop 404 and derivative of two samples 402 and 403 results in slop 405. If the difference between these two derivative 406 is zero or negligible then sample 402 can be eliminated.

(27) In one embodiment of consecutive sample pair derivative 400, consecutive sample pair derivatives is used to determine which sample of an analog signal can be eliminated without loss of signal fidelity.

(28) FIG. 11 illustrate a non-uniform sampling technique 500. In general non-uniform sampling 500 facilitates elimination of samples in an over sampled analog signal using derivatives of consecutive sample pairs. The samples 501, 502, 503, 504, and 505 of an over sampled analog signal are used to find slops 506, 507, 508, and 509, determine estimated values 510, 511 and 512 for samples 503, 504 and 505, and calculate differences 513, 514, and 515 between estimated values 510, 511 and 512 and the real values 503, 504, and 505 respectively. Derivative of sample pair 501 and 502 results in slop 506, derivative of sample pair 502 and 503 results in slop 507, derivative of sample pair 503 and 504 produces slop 508, and derivative of sample pair 504 and 505 results in slop 509. Slop 506 is used to find estimated value 510 for sample 503. If 513 the difference between real value of sample 503 and the estimated value 510 is smaller than a specified threshold, it allows sample 502 to be eliminated. Since sample 502 is eliminated slop 506 represents the derivative of sample pair 501 and 503 and is used to find an estimated value 511 for sample 504. The difference 514 between real value of sample 504 and its estimated value is higher than a specified threshold and therefore, sample 503 is not eliminated. Slop 508 representing derivative of sample pair 503 and 504 is used to find an estimated value 512 for sample 505. Since the difference 515 between real value of sample 505 and its estimated value 512 is higher than a specified threshold sample 505 is kept and the process continues for following samples.

(29) In one embodiment of non-uniform sampling technique 500, a derivative of a pair of consecutive samples is used to calculate the slop of the line connecting the two samples

(30) In one embodiment of non-uniform sampling technique 500, the slop of the line connecting a pair of consecutive samples is used to find an estimated value for the sample followed the pair of consecutive samples.

(31) In another embodiment of non-uniform sampling technique 500, the difference between the estimated value and real value of the sample followed the pair of consecutive samples is used to decide whether the second sample in the pair of consecutive samples can be eliminated.

(32) In one embodiment of non-uniform sampling technique 500, a threshold for the difference of the estimated and the real value of the sample followed the pair of consecutive samples is used to decide if the second sample in the pair of consecutive samples can be eliminated.

(33) FIG. 12 shows sample elimination criteria 600. In general sample elimination criteria is based on a threshold which depends on type of analog signal and the amount of over sampling. Samples 601, 602, 603, 604, 605, and 606 represent a time window of an over sampled analog signal. The difference between derivative of consecutive sample pair 601, and 602 and the consecutive sample pair 602, and 603 is below a predefined threshold and results in elimination of sample 602. The difference between derivative of consecutive sample pair 601, and 603 and the consecutive sample pair 603, and 604 is also below a predefined threshold and results in elimination of sample 603. If this process is continued samples 602, 603, 604 and 605 are eliminated. However, the number of samples in a row that can be eliminated depends on the fidelity and integrity of over sampled analog signal and need to be limited to an acceptable number.

(34) In one embodiment of sample elimination criteria 600, the number of samples in a row that can be eliminated needs to be limited to a figure that the fidelity and integrity of over sampled analog signal is maintained.

(35) FIG. 13 shows scenario I of an analog signal (AS) with 3 samples S1, S2, and S3. AB which is proportional to slope change of the line connecting S1 and S2 and the line connecting S2 and S3 is represented by equation 1 (Eq. 1)
|(S.sub.2S.sub.1/tS.sub.3S.sub.2/t)|t(Eq. 1)
Where t is sampling time interval. In this scenario AB is large and no sample can be eliminated.

(36) FIG. 14 shows scenario II of an analog signal (AS) with 6 samples S1, S2, S3, S4, S5 and S6. AB which is proportional to slope change of the line connecting S1, S2, S3, S4, S5, and the line connecting S5 and S6 is represented by equation 2 (Eq. 2)
|(S.sub.5S.sub.1/4tS.sub.6S.sub.5/t)|t(Eq. 2)
Where t is sampling time interval. And from this calculation it is decided that samples S.sub.2, S.sub.3 and S.sub.4 can be eliminated.

(37) Using a strictly digital methodology all samples S.sub.1 thorough S.sub.6 must be digitized and equations similar to Eq. 1 and Eq. 2 iteratively computed and compared against a threshold parameter which decides if a sample is to be eliminated. A means of digital counting of the samples is needed which in the case of FIG. 14 will indicate that 4 consecutive samples can be eliminated.

(38) This digital computation-based analysis requires multi sample/hold circuits, ND converters and possibly a floating point processor for addition, subtraction, multiplication and division.

(39) FIG. 15 depicts block diagram of a simple analog sampling 700. The analog sampling 700 implementation uses 3 sample/hold (S/H) blocks 702, 703, and 704 for analog signal shown in FIG. 14. The chain of multiple S/H circuits eliminates the need for multiple ND converters.

(40) In one embodiment sample and hold S/H 702 continuously samples the input analog signal 701 and produces samples S1 to S7. Sample S1 is transferred to S/H 703 and then S/H 704. Sample S2 to S6 are transferred to S/H 703

(41) In another embodiment the data from S/H 703 is only transmitted to S/H 704 when the length of |AB|> as shown in FIG. 14.

(42) FIG. 16 shows a general block diagram of the decision circuit 800. Decision circuit 800 is aimed for FIG. 14, samples S1, S2, S3, S4, S5, S6, etc and Eq. 2. The voltages V1, V2, and V3 represents the value of one of the samples S1, S2, S3, S4, S5, S6 etc.

(43) Decision circuit 800 among other things includes, subtract blocks 801, 802, and 805, scaling block 803, eliminated sample counter 804, absolute value amplifier 806, and comparator 807.

(44) In one embodiment of decision circuit 800, voltages V2 and V3 used by subtract 802 can come from non-consecutive samples due to number of eliminated samples between them.

(45) In one embodiment of decision circuit 800, voltages V1 and V2 used by subtract 801 can be from consecutive samples.

(46) In another embodiment of decision circuit 800 the output of subtract block 803 is divided (scaled) back based on the number of eliminated samples stored in eliminated sample counter 804. This is done in the scaling block 803 which receives the number of eliminated samples from the eliminated sample counter 804.

(47) In one embodiment of decision circuit 800, the outputs of the subtract block 801 and the scaling block 803 are subtracted in subtract block 805 and the output goes to an absolute value amplifier 806. The output of the absolute value amplifier 806 goes to a comparator 807 that compares the data with the reference threshold .

(48) In another embodiment of decision circuit 800, if the comparator 807 output is high the sample from S/H 702 in FIG. 15 is kept and in case it is low the sample from S/H 702 is discarded and replaced by data from the S/H 701.

(49) FIG. 17 depict implementation 900 as one possible implementation of decision circuit 800. The implementation 900 among others include subtract 110 and 111, counter 114, current splitter 112 and 113, current to voltage converter 115, absolute value amplifier 116 and comparator 117.

(50) In one embodiment of implementation 900 the subtract 110 and 111 are voltage to current convertors and take V1, V2, and V2, V3 as their input and produce G(V2V1) and G(V2V3) at their outputs respectively.

(51) In another embodiment of implementation 900 the counter 114 counts the number of deleted samples.

(52) In one embodiment of implementation 900 the circuit 112 and 113 are current splitter which scales the output current of subtract 111 down proportional to the number of deleted samples and produce G(V2V3)/n(number of discarded samples).

(53) In one embodiment of implementation 900 the currents G(V2V1) and G(V2V3)/n add and produce G((V2V3)/n+V2V1).

(54) In another embodiment of implementation 900 the resulting subtracted current G((V2V3)/n+V2V1) is converted back to voltage in the circuit 115.

(55) In one embodiment of implementation 900 the output voltage of circuit 115 is applied to absolute amplifier 116 to produce the absolute of AB of FIG. 14.

(56) In another embodiment of implementation 900 the amplified absolute value at the output of circuit 116 is compared with threshold in the comparator 117 and if the result is low the sample is discarded and the deleted sample counter is increased.

(57) In one embodiment of implementation 900, the current splitter 112 and 113 is a new precise analog means to divide the incoming current by n which is the number of eliminated samples. In this example implementation, the drain of all the transistors are biased at Vref (a reference voltage) and their gates are connected to the delete sample counter 114 bits. The multiple transistors in 112 are binary scaled with the LSB of the counter coming to the gate of minimal sized transistor and the MSB goes to the gate of a device which is binary weighted in size.

(58) In another embodiment of implementation 900, the voltage of the drain of scaling transistors 112 are all connected to Vref and the reference input of amplifier 115 is also connected to Vref. This forces the drain of transistor 113 to be also sitting at Vref. This design forces the current scaling to be quite perfect and not be affected by device nonlinearities.

(59) Various embodiments are thus described. While particular embodiments have been described, it should be appreciated that the embodiments should not be construed as limited by such description, but rather construed according to the following claims.