APPARATUS AND METHOD FOR APPLYING DYNAMIC COMPENSATION TO FEEDBACK SIGNAL GENERATED FROM LOADLINE OF VOLTAGE REGULATOR

Abstract

A feedback loop circuit of a voltage regulator includes a loadline and a compensation circuit. The loadline generates a feedback signal according to a sensed current signal that provides information of an inductor current of the voltage regulator, and outputs the feedback signal to a controller circuit of the voltage regulator for regulating an output voltage of the voltage regulator. The compensation circuit generates a compensation signal to compensate for a deviation of the output voltage, wherein the feedback signal generated from the loadline is affected by the compensation signal.

Claims

1. A feedback loop circuit of a voltage regulator comprising: a loadline, arranged to generate a feedback signal according to a sensed current signal that provides information of an inductor current of the voltage regulator, and output the feedback signal to a controller circuit of the voltage regulator for regulating an output voltage of the voltage regulator; and a compensation circuit, arranged to generate a compensation signal to compensate for a deviation of the output voltage, wherein the feedback signal generated from the loadline is affected by the compensation signal.

2. The feedback loop circuit of claim 1, wherein the compensation circuit is arranged to inject the compensation signal to the feedback signal.

3. The feedback loop circuit of claim 2, wherein the compensation circuit comprises: a compensation current generator circuit, arranged to generate a compensation current; and a filter circuit, arranged to apply filtering to the compensation current to generate the compensation signal.

4. The feedback loop circuit of claim 1, wherein the compensation circuit is arranged to generate the compensation signal in response to a specific event that leads to the deviation of the output voltage.

5. The feedback loop circuit of claim 4, wherein the compensation circuit is arranged to generate the compensation signal during a period in which a load current supplied from the voltage regulator to a load is unchanged.

6. The feedback loop circuit of claim 4, wherein the specific event is a dynamic voltage identification (DVID) event.

7. The feedback loop circuit of claim 6, wherein the DVID event changes the output voltage from a first voltage setting to a second voltage setting, and the compensation circuit is arranged to determine the compensation signal according to capacitance of an output capacitor of the voltage regulator and a slew rate of changing the output voltage from the first voltage setting to the second voltage setting.

8. The feedback loop circuit of claim 4, wherein the voltage regulator is a multi-phase voltage regulator, and the specific event is a phase number change event.

9. The feedback loop circuit of claim 8, wherein the phase number change event changes a number of phases enabled in the voltage regulator from a first phase number to a second phase number, and the compensation circuit is arranged to set the compensation signal according to a difference between the first phase number and the second phase number.

10. The feedback loop circuit of claim 8, wherein the compensation circuit is arranged to control timing of generating the compensation signal according to triggering of pulse-width modulation (PWM) pulse since the phase number change event.

11. The feedback loop circuit of claim 4, wherein the specific event is an operation mode transition event.

12. The feedback loop circuit of claim 11, wherein the operation mode transition event comprises transition between a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM).

13. The feedback loop circuit of claim 11, wherein the compensation circuit is arranged to control timing of generating the compensation signal according to triggering of pulse-width modulation (PWM) pulse since the operation mode transition event.

14. A compensation method employed by a voltage regulator comprising: according to a sensed current signal that provides information of an inductor current of the voltage regulator, generating a feedback signal through a loadline; generating a compensation signal to compensate for a deviation of an output voltage of the voltage regulation, wherein the feedback signal is affected by the compensation signal; and outputting the feedback signal to a controller circuit of the voltage regulator for regulating the output voltage.

15. The compensation method of claim 14, wherein the compensation signal is injected to the feedback signal.

16. The compensation method of claim 14, wherein generating the compensation signal to compensate for the deviation of the output voltage comprises: generating the compensation signal in response to a specific event that leads to the deviation of the output voltage.

17. The compensation method of claim 16, wherein the specific event is a dynamic voltage identification (DVID) event.

18. The compensation method of claim 16, wherein the voltage regulator is a multi-phase voltage regulator, and the specific event is a phase number change event.

19. The compensation method of claim 16, wherein the specific event is an operation mode transition event.

20. The compensation method of claim 19, wherein the operation mode transition event comprises transition between a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a diagram illustrating a first voltage regulator according to an embodiment of the present invention.

[0009] FIG. 2 is a diagram illustrating a deviation of the output voltage resulting from a dynamic voltage identification (DVID) up event that happens under a condition that the proposed compensation circuit is not enabled.

[0010] FIG. 3 is a diagram illustrating a deviation of the output voltage resulting from a DVID down event that happens under a condition that the proposed compensation circuit is not enabled.

[0011] FIG. 4 is a diagram illustrating a second voltage regulator according to an embodiment of the present invention.

[0012] FIG. 5 is a diagram illustrating dynamic current compensation during a DVID up event and a DVID down event according to an embodiment of the present invention.

[0013] FIG. 6 is a diagram illustrating a third voltage regulator according to an embodiment of the present invention.

[0014] FIG. 7 is a diagram illustrating a fourth voltage regulator according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0015] Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

[0016] FIG. 1 is a diagram illustrating a first voltage regulator according to an embodiment of the present invention. The voltage regulator 100 may be a switching voltage regulator with adaptive voltage positioning (AVP). The voltage regulator 100 is capable of regulating the output voltage V.sub.o delivered to the load 101. For example, the load 101 may be a microprocessor. It should be noted that the load current I.sub.o supplied to the load 101 may vary in response to different load conditions of the load 101. Hence, when the load condition of the load 101 remains unchanged, the load current I.sub.o is unchanged. As shown in FIG. 1, the voltage regulator 100 may include a controller circuit 102, a power stage circuit (labeled as “PS”) 104, an inductor L.sub.N, an output capacitor C.sub.o, and a feedback loop circuit 106. The feedback loop circuit 106 includes a loadline 108 and a compensation circuit 110. The controller circuit 102 may act as a pulse-width modulation (PWM) controller, and may include a filter circuit (labeled as “A.sub.c(s)”) 112 and a PWM signal generator circuit (labeled by “PWM”) 114. The controller circuit 102 is a part of an output voltage feedback loop. In this embodiment, the controller circuit 102 operates in response to an error voltage V.sub.err (which is indicative of difference between the output voltage V.sub.o and a reference voltage V.sub.ref of the voltage regulator 100) and a feedback signal S.sub.fb generated from the feedback loop circuit 106. Specifically, the PWM signal generator circuit 114 is arranged to deal with PWM control of the following power stage circuit 104. Hence, the PWM signal generator circuit 114 can regulate the output voltage V.sub.o delivered to the load 101 by controlling PWM pulses applied to the power stage circuit 104. For example, the power stage circuit 104 may include a high-side switch and a low-side switch controlled by PWM pulses generated from the PWM signal generator circuit 114. The voltage regulator 100 may be a multi-phase voltage regulator including N (N≥2) sets of power stage circuit and inductor coupled between the controller circuit (e.g. multi-phase PWM controller) 102 and the load 101 in parallel. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, the voltage regulator 100 may be a single-phase voltage regulator including only one set (N=1) of power stage circuit and inductor coupled between the controller circuit (e.g. single-phase PWM controller) 102 and the load 101.

[0017] As shown in FIG. 1, the average inductor current ave(I.sub.L) of the inductor L.sub.N is equal to a sum of the average capacitor current ave(I.sub.c) of the output capacitor C.sub.o and the average load current ave(I.sub.o) of the load 101 (i.e. ave(I.sub.L)=ave(I.sub.o)+ave(I.sub.c)). In a steady state, the average inductor current ave(I.sub.L) is equal to the average load current ave (I.sub.o) due to ave(I.sub.c)=0. The inductor current IL can be sensed to act as an approximation of the load current I.sub.o. Hence, the loadline 108 is arranged to generate the feedback signal S.sub.fb according to a sensed current signal I.sub.sen that provides information of the inductor current I.sub.L (I.sub.sen≅I.sub.L), and output the feedback signal S.sub.fb to the controller circuit 102. In a first exemplary design, the sensed current signal I.sub.sen may be derived from sensing the “actual” inductor current I.sub.L through some form of sensing circuit like direct current resistance (DCR)-sensing V.sub.o/I.sub.c. In a second exemplary design, the sensed current signal I.sub.sen may be provided by the power stage circuit 104. In a third exemplary design, the sensed current signal I.sub.sen may be provided by sensing other node of the voltage regulator (e.g. V.sub.o/I.sub.c). In a fourth exemplary design, the sensed current signal I.sub.sen may be generated with no physical sensing (e.g. purely synthesized by a digital/analog circuit). To put it simply, the present invention has no limitations on the means of generating the sensed current signal I.sub.sen that is representative of the inductor current I.sub.L.

[0018] However, the above-mentioned approximation fails under some cases. If no compensation is applied to the inaccurate loadline, the performance of the PWM controller will be degraded. FIG. 2 is a diagram illustrating a deviation of the output voltage V.sub.o resulting from a dynamic voltage identification (DVID) up event that happens under a condition that the proposed compensation circuit 110 is not enabled. The DVID up event is to change the output voltage V.sub.o from a present voltage setting to a next voltage setting, where the next voltage setting is higher than the present voltage setting. The increase of the inductor current I.sub.L is used to charge the output capacitor C.sub.o, such that the output voltage V.sub.o can ramp up accordingly. Specifically, the capacitor current I.sub.c of the output capacitor C.sub.o is a non-zero charging current. Though the load current I.sub.o is unchanged during the DVID up event, the extra charging current will be considered as an increase of the inductor current I.sub.L in the AVP loop. As a result, the output voltage V.sub.o has an undesired offset ΔV=ΔI.sub.L×R.sub.LL, where R.sub.LL is the loadline resistance value. During the DVID up event, the load 101 (e.g. microprocessor) expects that the output voltage V.sub.o follows the ramp-up curve 202. However, due to the fact that the inductor current I.sub.L cannot be an approximation of the load current I.sub.o during the DVID up event, the output voltage V.sub.o has a voltage decrease during a period T1, and has a voltage increase during a period T2.

[0019] FIG. 3 is a diagram illustrating a deviation of the output voltage V.sub.o resulting from a DVID down event that happens under a condition that the proposed compensation circuit 110 is not enabled. The DVID down event is to change the output voltage V.sub.o from a present voltage setting to a next voltage setting, where the next voltage setting is lower than the present voltage setting. The decrease of the inductor current IL is used to discharge the output capacitor C.sub.o, such that the output voltage V.sub.o can ramp down accordingly. Specifically, the capacitor current I.sub.c of the output capacitor C.sub.o is a non-zero discharging current. Though the load current I.sub.o is unchanged during the DVID down event, the extra discharging current will be considered as a decrease of the inductor current I.sub.L in the AVP loop. As a result, the output voltage V.sub.o has an undesired offset ΔV=ΔI.sub.L×R.sub.LL, where R.sub.LL is the loadline resistance value. During the DVID down event, the load 101 (e.g. microprocessor) expects that the output voltage V.sub.o follows the ramp-down curve 302. However, due to the fact that the inductor current I.sub.L cannot be an approximation of the load current I.sub.o during the DVID down event, the output voltage V.sub.o has a voltage increase during a period T3, and has a voltage decrease during a period T4.

[0020] Furthermore, during a phase number change event that changes a number of phases enabled in the voltage regulator 100 from a first phase number to a second phase number different from the first phase number, the inductor current I.sub.L also cannot be an approximation of the load current I.sub.o. For example, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage V.sub.o if no compensation is applied to the inaccurate loadline. The output voltage undershoot does not only happen when the phase number decreases. It could happen when an operation mode transition happens. For example, the output voltage undershoot happens when there is transition between a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM).

[0021] Regarding a voltage regulator with AVP, the output voltage is affected when the inductor current cannot be an approximation of the load current. Specifically, as long as the inductor current undergoes some kind of dynamic, it affects the output voltage, even the load current is unchanged. To address this issue, the present invention proposes using the compensation circuit 110 to generate a compensation signal S.sub.c to compensate for a deviation (e.g. offset or undershoot) of the output voltage V.sub.o. The feedback signal S.sub.fb generated from the loadline 108 is affected by the compensation signal S.sub.c. In other words, the feedback signal S.sub.fb is compensated before arriving at the controller circuit 102. For example, the compensation signal S.sub.c may be injected to the feedback signal S.sub.fb to update the feedback signal S.sub.fb finally obtained by the controller circuit 102, that is, S.sub.fb=S.sub.fb+S.sub.c. The polarity of the compensation signal S.sub.c may vary, depending upon the disturbance of the inductor current I.sub.L. The compensation circuit 110 may receive a plurality of parameters PR.sub.1-PR.sub.M (M≥2), and may refer to one or more of the parameters PR.sub.1-PR.sub.M to determine polarity and/or magnitude of the compensation signal S.sub.c. Further details of the compensation circuit 110 are described as below with reference to the accompanying drawings.

[0022] FIG. 4 is a diagram illustrating a second voltage regulator according to an embodiment of the present invention. The voltage regulator 400 may be a switching voltage regulator with AVP. Like the voltage regulator 100, the voltage regulator 400 is capable of regulating the output voltage V.sub.o delivered to the load (e.g. microprocessor) 101. As shown in FIG. 4, the voltage regulator 400 may include a controller circuit 402, a power stage circuit (labeled as “PS”) 404, an inductor L.sub.N, an output capacitor C.sub.o, and a feedback loop circuit 406. In this embodiment, the voltage regulator 400 may be a multi-phase voltage regulator including N (N≥2) sets of power stage circuit and inductor coupled between the controller circuit 402 and the load 101 in parallel. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, the voltage regulator 400 may be a single-phase voltage regulator including only one set (N=1) of power stage circuit and inductor coupled between the controller circuit 402 and the load 101.

[0023] The feedback loop circuit 406 includes a loadline 408 and a compensation circuit 410. The feedback signal S.sub.fb generated from the loadline 408 is based on the sensed current signal I.sub.sen that provides information of the inductor current I.sub.L. It should be noted that the present invention has no limitations on the means of generating the sensed current signal I.sub.sen that is representative of the inductor current I.sub.L. The compensation circuit 110 shown in FIG. 1 may be implemented by the compensation circuit 410, where the parameters PR.sub.1-PR.sub.M include parameters C.sub.o and SR. In this embodiment, the compensation circuit 410 is arranged to generate the compensation signal S.sub.c in response to a DVID event. As shown in FIG. 4, two parameters C.sub.o and SR are received by the compensation circuit 410, where the parameter C.sub.o is the capacitance of the output capacitor, and the parameter SR may be provided by the load 101 (e.g. microprocessor) and indicates a slew rate of changing the output voltage V.sub.o from a present voltage setting (which is indicated by a present VID) to a next voltage setting (which is indicated by a next VID). As mentioned above, the increase of the inductor current I.sub.L during a DVID up event results from a non-zero charging current of the output capacitor C.sub.o, and the decrease of the inductor current I.sub.L during a DVID down event results from a non-zero discharging current of the output capacitor C.sub.o. A product of the parameters (i.e. C.sub.0×SR) may be regarded as an estimation of the charging/discharging current of the output capacitor C.sub.o that happens during a DVID up/down event. The compensation signal S.sub.c is generated according to a compensation current I.sub.comp with a current value set by a product of the two parameters (i.e. C.sub.0×SR), and then injected to the feedback signal S.sub.fb generated from the loadline 408 according to the sensed current signal I.sub.sen that provides information of the inductor current I.sub.L (I.sub.sen≅I.sub.L). In this way, disturbance of the feedback signal S.sub.fb that results from mismatch between the load current I.sub.o (which may be unchanged during the DVID up/down event) and the load current I.sub.L (which may be increased/decreased by the charging/discharging current of the output capacitor C.sub.o during the DVID up/down event) can be compensated by the compensation signal S.sub.c. For example, |I.sub.c×R.sub.LL|=|C.sub.o×SR×R.sub.c|, where R.sub.c is the resistance value of the compensation circuit 410.

[0024] Please refer to FIG. 4 in conjunction with FIG. 5. FIG. 5 is a diagram illustrating dynamic current compensation during a DVID up event and a DVID down event according to an embodiment of the present invention. A DVID up event is triggered at t1, such that a VID voltage of the load 101 (e.g. microprocessor) changes from a present voltage setting at t1 to a higher voltage setting at t2according to a slew rate SR_UP determined by the load 101 (e.g. microprocessor). During the DVID up event, the inductor current I.sub.L is increased by the charging current I.sub.c of the output capacitor C.sub.o. In response to the DVID up event, the compensation current I.sub.comp is generated by the compensation circuit 410 according to the output capacitance C.sub.o and the slew rate SR (SR=SR_UP). During the DVID up event, the disturbance ΔI.sub.1 of the inductor current I.sub.L is compensated by the compensation current I.sub.comp. In this way, the final feedback signal S.sub.fb (S.sub.fb=S.sub.fb+S.sub.c) received by the controller circuit 402 remains unchanged under a condition that the load current I.sub.o is unchanged during the period from t1 to t2.

[0025] A DVID down event is triggered at t3, such that a VID voltage of the load 101 (e.g. microprocessor) changes from a present voltage setting at t3 to a lower voltage setting at t4 according to a slew rate SR_DN determined by the load 101 (e.g. microprocessor). During the DVID down event, the inductor current I.sub.L is decreased by the discharging current I.sub.c of the output capacitor C.sub.o. In response to the DVID down event, the compensation current I.sub.comp is generated by the compensation circuit 410 according to the output capacitance C.sub.o and the slew rate SR=SR_DN. During the DVID down event, the disturbance ΔI.sub.2 of the inductor current I.sub.L is compensated by the compensation current I.sub.comp. In this way, the final feedback signal S.sub.fb (S.sub.fb=S.sub.fb+S.sub.c) received by the controller circuit 402 remains unchanged under a condition that the load current I.sub.o is unchanged during the period from t3 to t4.

[0026] FIG. 6 is a diagram illustrating a third voltage regulator according to an embodiment of the present invention. The major difference between the voltage regulators 600 and 400 is that a compensation circuit 610 included in a feedback loop circuit 606 of the voltage regulators 600 has a compensation current generator (labeled by “I.sub.comp Gen”) 612 and a filter circuit (labeled by “A.sub.x(s)”) 614. The compensation circuit 110 may be implemented by the compensation circuit 610, where the parameters PR.sub.1-PR.sub.M include PHN, DCM, Trig, etc. The compensation current generator 612 is arranged to receive a plurality of parameters (e.g. PHN, DCM, and Trig), and generate a compensation circuit I.sub.comp according to information carried by at least one of the parameters. The loop filter 614 is arranged to apply filtering (e.g. low-pass filtering) to the compensation circuit I.sub.comp to generate the compensation signal S.sub.c.

[0027] In this embodiment, the voltage regulator 600 may be a multi-phase voltage regulator including N (N≥2) sets of power stage circuit and inductor coupled between the controller circuit 402 and the load 101 in parallel. The parameter PHN includes information of a phase change event. For example, the parameter PHN may indicate whether a phase change event happens, and may further indicate that the phase change event changes the number of phases enabled in the voltage regulator 600 from a present phase number to a next phase number (which may be larger than or smaller than the present phase number). In this embodiment, the compensation circuit 610 is arranged to generate the compensation signal S.sub.c in response to a phase number change event. For example, the compensation circuit 610 may set the compensation current I.sub.comp according to a difference between the present phase number and the next phase number.

[0028] The parameter Trig indicates whether triggering of PWM pulse happens. For example, a control voltage Vc fed into a PWM signal generator circuit 604 is derived from an output signal of a filter circuit 602, and triggering of PWM pulse happens each time the waveform of the control voltage Vc crosses over the waveform of the inductor current I.sub.L. In some embodiments of the present invention, the compensation circuit 610 may further refer to the parameter Trig to control the timing (e.g. start time and duration) of generating the compensation signal S.sub.c since the phase number change event. Hence, the compensation circuit 610 may not start generating the compensation signal S.sub.c at the time the phase number change event happens.

[0029] The parameter DCM indicates whether an operation mode transition event happens. For example, the operation mode transition event may include transition between CCM and DCM. For another example, the operation mode transition event may include transition between different operation modes supported by the voltage regulator 600. In this embodiment, the compensation circuit 610 is further arranged to generate the compensation signal S.sub.c in response to the operation mode transition event (e.g. DCM/CCM transition event). Furthermore, the compensation circuit 610 may further refer to the parameter Trig to control the timing (e.g. start time and duration) of generating the compensation signal S.sub.c since the operation mode transition event (e.g. DCM/CCM transition event). Hence, the compensation circuit 610 may not start generating the compensation signal S.sub.c at the time the operation mode transition event (e.g. DCM/CCM transition event) happens.

[0030] As mentioned above, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage V.sub.o. Furthermore, the output voltage undershoot may happen when an operation mode transition event (e.g. CCM/DCM transition event) happens. The compensation signal S.sub.c is derived from the compensation current I.sub.comp. Since the compensation current I.sub.comp is generated in response to the phase number change event or the operation mode transition event, and then injected to the feedback signal S.sub.fb generated from the loadline 408 according to the sensed current signal I.sub.sen that provides information of the inductor current I.sub.L (I.sub.sen≅I.sub.L), disturbance of the feedback signal S.sub.fb that results from mismatch between the load current I.sub.o (which may be unchanged during the phase number change event or the operation mode transition event) and the load current I.sub.L (which may be increased during the phase number change event or the operation mode transition event) can be compensated by the compensation signal S.sub.c.

[0031] Regarding the embodiment shown in FIG. 4, the output voltage offset during the DVID event can be compensated by means of the proposed compensation circuit 410. Regarding the embodiment shown in FIG. 6, the output voltage undershoot during the phase number change event or the operation mode transition event can be compensated by means of the proposed compensation circuit 610. In practice, any voltage regulator using one or both of the proposed compensation circuit designs shown in FIG. 4 and FIG. 6 falls within the scope of the present invention. FIG. 7 is a diagram illustrating a fourth voltage regulator according to an embodiment of the present invention. The voltage regulator 700 may be a switching voltage regulator with AVP. The voltage regulator 700 is capable of regulating the output voltage V.sub.o delivered to the load 101. As shown in FIG. 7, the voltage regulator 700 may include a controller circuit 702, a power stage circuit (labeled as “PS”) 704, an inductor L.sub.N, an output capacitor C.sub.o, and a feedback loop circuit 706. In this embodiment, the voltage regulator 700 may be a multi-phase voltage regulator including N (N≥2) sets of power stage circuit and inductor coupled between the controller circuit 702 and the load 101 in parallel. The feedback loop circuit 706 includes a loadline 708 and a compensation circuit 710. The compensation circuit 110 may be implemented by the compensation circuit 710. In this embodiment, the compensation circuit 710 is capable of generating a compensation signal to compensate for an output voltage offset during the DVID event and generating a compensation signal to compensate for an output voltage undershoot during the phase number change event or the operation mode transition event (e.g. CCM/DCM transition event). Since a person skilled in the art can readily understand details of the compensation circuit 710 after reading above paragraphs directed to the compensation circuits 410 and 610, further description is omitted here for brevity.

[0032] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.