Time domain integrated temperature sensor

Abstract

A time domain integrated temperature sensor described by the present invention adopts a shaped clock signal to control the charging time of capacitors, so that the capacitors generate charging time delay signals related to the cycle of an input clock, and a pulse signal related to pulse width, temperature and the cycle of the input clock is generated through logical XOR (Exclusive OR) operation on a time delay signal generated when the capacitors are charged by one way of PTAT (Proportional To Absolute Temperature) current in an above control manner and a time delay signal generated when the capacitors are charged by one way of CTAT (Complementary To Absolute Temperature) current in the same manner; then, the same input clock signal is adopted for quantifying the pulse width of the pulse signal, the relevance of the obtained quantization result and the cycle of the input clock is completely offset, namely, an output value of the temperature sensor is unrelated to the input clock signal, thereby solving the problem that the reading of the existing time domain integrated temperature sensor is inconsistent as the cycle of the clock signal changes and improving the precision of the time domain integrated temperature sensor to a certain degree.

Claims

1. A time domain integrated temperature sensor, comprising a PTAT (Proportional To Absolute Temperature) time delay circuit, a CTAT (Complementary To Absolute Temperature) time delay circuit, an XOR (Exclusive OR) gate, a counter and a pulse shaping circuit, wherein two input ends of the XOR gate are respectively connected to an output end of the PTAT time delay circuit and an output end of the CTAT time delay circuit, an output end of the XOR gate is connected with an enable end of the counter, and a clock signal input end of the counter is connected to an output end of the pulse shaping circuit, an input end of the pulse shaping circuit is connected to a clock input port of the temperature sensor; the PTAT time delay circuit comprises a PTAT current generation circuit, a first switch unit, a first capacitor, a first switch and a first level-detection circuit, an output end of the PTAT current generation circuit is connected to the first switch unit, an output end of the first switch unit is connected to a positive end of the first capacitor, the first switch and an input end of the first level-detection circuit, a control end of the first switch unit is connected to the clock input port of the temperature sensor through the pulse shaping circuit, the first capacitor and the first switch are connected with each other in parallel and then connected to the ground, and an output end of the first level-detection circuit is connected to a first input end of the XOR gate; the CTAT time delay circuit comprises a CTAT current generation circuit, a second switch unit, a second capacitor, a second switch and a second level-detection circuit, an output end of the CTAT current generation circuit is connected to the second switch unit, an output end of the second switch unit is connected to a positive end of the second capacitor and the second switch, an input end of the second level-detection circuit, and a control end of the second switch unit is connected to the clock input port of the temperature sensor through the pulse shaping circuit, the second capacitor and the second switch are connected with each other in parallel and then connected to ground, and an input end of the second level-detection circuit is connected to a second input end of the XOR gate; an output end of the pulse shaping circuit is connected to the control end of the first switch unit and the control end of the second switch unit respectively; the pulse shaping circuit is configured to shape an input clock signal into a square wave signal with the same cycle with the input clock signal, the time of high voltage-level of the square wave signal within the cycle is a constant time, the square wave signal is used for controlling switching on and off of the first switch unit and the second switch unit, the square wave signal is also taken as a clock of the counter to count during high voltage-level of a pulse signal, and the counting result is a quantization result of the pulse width of the pulse signal; wherein the pulse shaping circuit comprises a current source, a third P-type MOS transistor, a first amplifier, a first NOR (Nor OR) gate, a second NOR gate, a first buffer, a second buffer, a third capacitor and a third N-type MOS transistor; an output end of the current source is connected to a source electrode of the third P-type MOS transistor, a drain electrode of the third P-type MOS transistor is connected to ground through the third capacitor, a positive input end of the first amplifier is connected to a drain electrode of the third P-type MOS transistor, a negative input end of the first amplifier is connected to a first reference voltage end, an output end of the first amplifier is connected to a second input end of the first NOR gate, a first input end of the first NOR gate is connected to a reset signal end, a third input end of the first NOR gate is connected to an output end of the second NOR gate, the output end of the first NOR gate is connected to the first input end of the second NOR gate and an input end of the first buffer, an output end of the first buffer is taken as the output end of the pulse shaping circuit, a second input end of the second NOR gate is connected to a clock signal end as the input end of the pulse shaping circuit, an output end of the second NOR gate is connected to a grid electrode of the third P-type MOS transistor and a grid electrode of the third N-type MOS transistor through the second buffer, a drain electrode of the third N-type MOS transistor is connected to a drain electrode of the third P-type MOS transistor, and a source electrode of the third N-type MOS transistor is connected to ground.

2. The time domain integrated temperature sensor according to claim 1, wherein the first switch unit is a third switch, an input end of the third switch is connected to the output end of the PTAT current generation circuit, a control end of the third switch is connected to the output end of the pulse shaping circuit, and an output end of the third switch is connected to the positive end of the first capacitor.

3. The time domain integrated temperature sensor according to claim 1, wherein the first switch unit is a first compound switch, the first compound switch comprises a first N-type MOS (Metal Oxide Semiconductor) transistor and a first P-type MOS transistor that are connected with each other in parallel, a drain electrode of the first N-type MOS transistor is connected to a source electrode of the first P-type MOS transistor and then is connected to the output end of the PTAT current generation circuit, a source electrode of the first N-type MOS transistor is connected to a drain electrode of the first P-type MOS transistor and then is connected to the positive end of the first capacitor, a grid electrode of the first N-type MOS transistor is connected to the output end of the pulse shaping circuit, and a grid electrode of the first P-type MOS transistor is connected to the output end of the pulse shaping circuit through a phase inverter.

4. The time domain integrated temperature sensor according to claim 1, wherein the second switch unit is a fourth switch, an input end of the fourth switch is connected to the output end of the CTAT current generation circuit, a control end of the fourth switch is connected to the output end of the pulse shaping circuit, and an output end of the fourth switch is connected to the positive end of the second capacitor.

5. The time domain integrated temperature sensor according to claim 1, wherein the second switch unit is a second compound switch, the second compound switch comprises a second N-type MOS transistor and a second P-type MOS transistor that are connected with each other in parallel, a drain electrode of the second N-type MOS transistor is connected to a source electrode of the second P-type MOS transistor and then is connected to the output end of the CTAT current generation circuit, a source electrode of the second N-type MOS transistor is connected to a drain electrode of the second P-type MOS transistor and then is connected to the positive end of the second capacitor, a grid electrode of the second N-type MOS transistor is connected to the output end of the pulse shaping circuit, and a grid electrode of the second P-type MOS transistor is connected to the output end of the pulse shaping circuit through the phase inverter.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) In order to illustrate the technical solutions in the embodiments of the present invention or in the existing art more clearly, drawings to be used in description of the embodiments are introduced simply; apparently, the drawings in the following description are only some embodiments of the present invention, and those ordinary skilled in the art may acquire other drawings according to the following drawings on the premise of without contributing any creative effort.

(2) FIG. 1 shows a structure diagram of a temperature sensor circuit in the existing art;

(3) FIG. 2 shows a working principle diagram I of a temperature sensor in the existing art;

(4) FIG. 3 shows a working principle diagram II of a temperature sensor in the existing art;

(5) FIG. 4 shows a structure diagram of a temperature sensor circuit of the present invention;

(6) FIG. 5 shows a structure diagram of an embodiment I of a temperature sensor circuit of the present invention;

(7) FIG. 6 shows a structure diagram of an embodiment II of a temperature sensor circuit of the present invention;

(8) FIG. 7 shows a structure diagram of an embodiment I of a pulse shaping circuit of the present invention;

(9) FIG. 8 shows a structure diagram of an embodiment II of a pulse shaping circuit of the present invention;

(10) FIG. 9 shows a structure diagram of a PTAT current generation circuit of the present invention;

(11) FIG. 10 shows a structure diagram of a CTAT current generation circuit of the present invention;

(12) FIG. 11 shows a structure diagram of a level-detection circuit;

(13) FIG. 12 shows a comparison diagram of working sequence diagrams of two different frequencies of clock signals adopted by a temperature sensor;

(14) FIG. 13 shows a working sequence diagram of the embodiment of the present invention.

DETAILED DESCRIPTION

(15) The technical solutions in the embodiments of the present invention will be described clearly and completely below in combination with drawings in the embodiments of the present invention. Apparently, the described embodiments are merely a part of embodiments of the present invention but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments acquired by those ordinary skilled in the art on the premise of without contributing any creative effort belong to the protection scope of the present invention.

(16) FIG. 4 shows a structure diagram of a temperature sensor circuit of the present invention, the temperature sensor circuit 100 comprises the PTAT time delay circuit 1, the CTAT time delay circuit 2, the XOR gate 3 and the counter 4, wherein the two input ends of the XOR gate 3 are respectively connected to the output end of the PTAT time delay circuit 1 and the output end of the CTAT time delay circuit 2, the output end of the XOR gate 3 is connected with the enable end EN of the counter 4, and after XOR processing on the time delay signal in direct proportion with temperature generated by the PTAT time delay circuit 1 and the time delay signal in inverse proportion with temperature generated by the CTAT time delay circuit 2, the obtained pulse signal PW with pulse width changing with temperature is input into the counter 4. The clock signal input end of the counter 4 is connected to the clock input port CLK of the temperature sensor, so that the counter 4 can quantify the pulse signal PW with pulse width changing with temperature through the clock signal CLK, so as to obtain a quantified temperature signal D.sub.out, and the quantified temperature signal D.sub.OUT is output.

(17) As shown in FIG. 4, the PTAT time delay circuit 1 comprises the PTAT current generation circuit 10, the first capacitor C.sub.1, the first switch S.sub.1 and the first level-detection circuit 12. The PTAT current generation circuit 10 is used for generating charging current I.sub.PTAT in direct proportion with temperature, the output end of the PTAT current generation circuit 10 is connected to the positive end of the first capacitor C.sub.1 the first switch S.sub.1 and the input end V.sub.in of the first level-detection circuit 12, the first capacitor C.sub.1 and the first switch S.sub.1 are connected with each other in parallel and then connected to the ground, and the output end V.sub.out of the first level-detection circuit 12 is connected to the first input end of the XOR gate 3.

(18) In order to ensure the zero charge quantity of the first capacitor C.sub.1 when the charging current I.sub.PTAT starts to charge the first capacitor C.sub.1 and to ensure the counting precision of the counter 4, as shown in FIG. 4, a Start signal input port is connected with the first switch S.sub.1 and used for controlling the first switch S.sub.1 to be closed before the first capacitor C.sub.1 starts to be charged, the Start signal input port, the first switch S.sub.1 and the first capacitor C.sub.1 form a loop to dissipate the charge on the first capacitor C.sub.1 to ground, so that the voltage VP of the positive end of the first capacitor C.sub.1 is zero. In addition, the Start signal input port is also connected with a reset end Reset of the counter 4, so that the counter 4 can reset when starting to work. When the charging current I.sub.PTAT starts to charge the first capacitor C.sub.1, a Start signal is used for controlling the first switch S.sub.1 to be disconnected, the charging current IPTAT is used for charging the first capacitor C.sub.1, so that the voltage V.sub.P of the positive end of the first capacitor C.sub.1 increases gradually, when the voltage V.sub.P increases to over the threshold voltage V.sub.P,TH of the first level-detection circuit 12, the first level-detection circuit 12 is overturned, the voltage V.sub.P,TH output by the output end V.sub.out of the first level-detection circuit 12 is overturned from a low voltage-level signal to a high voltage-level signal.

(19) The output end of the PTAT current generation circuit is also connected with the first switch unit 11, the input end of the first switch unit 11 is connected with the output end of the PTAT current generation circuit 10, the control end of the first switch unit 11 is connected to the clock input port of the temperature sensor through the pulse shaping circuit 5, and the output end of the first switch unit 11 is connected to the positive end of the first capacitor C.sub.1. The first switch unit 11 is used for controlling the charging current I.sub.PTAT to charge the first capacitor C.sub.1 discontinuously according to the clock cycle of the clock signal, so as to generate the time delay signal related to temperature, so that the time delay of the time delay signal is related to the clock frequency.

(20) The CTAT time delay circuit comprises the CTAT current generation circuit 20, the second capacitor C.sub.2, the second switch S.sub.2 and the second level-detection circuit 22. The CTAT current generation circuit 20 is used for generating charging current I.sub.CTAT in inverse proportion with temperature, the output end of the CTAT current generation circuit 20 is connected to the positive end of the second capacitor C.sub.2, the second switch S.sub.2 and the input end V.sub.in of the second level-detection circuit 22, the second capacitor C.sub.2 and the second switch S.sub.2 are connected with each other in parallel and then connected to ground, and the input end V.sub.out of the second level-detection circuit 22 is connected to the second input end of the XOR gate 3.

(21) In order to ensure the zero charge quantity of the second capacitor C2 when the charging current I.sub.CTAT starts to charge the second capacitor C.sub.2 and to ensure the counting precision of the counter 4, as shown in FIG. 4, the Start signal input port is connected with the second switch S.sub.2 and used for controlling the second switch S.sub.2 to be closed before the second capacitor C.sub.2 starts to be charged, the Start signal input port, the second switch S.sub.2 and the second capacitor C.sub.2 form a loop to dissipate the charge on the second capacitor C.sub.2 to ground, so that the voltage V.sub.N of the positive end of the second capacitor C.sub.2 is zero. When the charging current I.sub.CTAT starts to charge the second capacitor C.sub.2, a Start signal is used for controlling the second switch S.sub.2 to be disconnected, the charging current I.sub.CTAT is used for charging the second capacitor C.sub.2, so that the voltage V.sub.N of the positive end of the second capacitor C.sub.2 increases gradually, when the voltage V.sub.N increases to over the threshold voltage V.sub.N,TH of the second level-detection circuit 22, the second level-detection circuit 22 is overturned, the voltage V.sub.N,D output by the output end V.sub.out of the second level-detection circuit 22 is overturned from a low voltage-level signal to a high voltage-level signal.

(22) The output end of the CTAT current generation circuit is also connected with the second switch unit 12, the input end of the second switch unit 12 is connected with the output end of the CTAT current generation circuit 20, the control end of the second switch unit 12 is connected to the clock input port of the temperature sensor through the pulse shaping circuit 5, and the output end of the second switch unit 12 is connected to the positive end of the second capacitor C.sub.2. The second switch unit 12 is used for controlling the charging current I.sub.CTAT to charge the second capacitor C.sub.2 discontinuously according to the clock cycle of the clock signal, so as to generate the time delay signal related to temperature, so that the time delay of the time delay signal is related to the clock frequency.

(23) The frequencies of the clock signals CLK adopted among different temperature sensors differ from one another, such as the CLK1 and the CLK2 shown in FIG. 12, and therefore different frequencies of the clock signals CLK can cause the inconsistency of the temperature readings in different temperature sensors. In order to solve the problem, the first switch unit 11 and the second switch unit 21 are added in the present invention, the pulse shaping circuit 5 is connected between the control end of the first switch unit 11 and the clock signal CLK and the control end of the second switch unit 21 and the clock signal CLK, the input end of the pulse shaping circuit 5 is connected to the clock input port of the temperature sensor, the output end of the pulse shaping circuit 5 is connected to the control end of the first switch unit 11, the control end of the second switch unit 21 and the clock signal input end of the counter 4 and used for shaping the input clock signal CLK into the square wave CLK_INT with the same cycle with the input clock signal, the time of high voltage-level of the square wave signal within the cycle is a constant time, the square wave signal CLK_INT is used for controlling switching on and off of the first switch unit 11 and the second switch unit 21, the square wave signal CLK_INT is also taken as the clock of the counter 4 to quantify the pulse width of the pulse signal related to temperature. As shown in FIG. 12, after the two different frequencies of input clock signals CLK1 and CLK2 are shaped by the pulse shaping circuit 5, the cycles of the corresponding output square wave signals CLK_INT1 and CLK_INT2 are respectively the same with the cycles of the input clock signals CLK1 and CLK2, but the time of high voltage-level of the square wave signal CLK_INT1 and the time of high voltage-level of the square wave signal CLK_INT2 are the constant as T.sub.PULSE and cannot change with the cycle of the input clock signal.

(24) FIG. 5 shows a structure diagram of an embodiment I of a temperature sensor circuit of the present invention, in the embodiment, the first switch unit 11 is the third switch S.sub.3, and the second switch unit 12 is the fourth switch S.sub.4. As shown in the figure, the input end of the third switch S.sub.3 is connected to the output end of the PTAT current generation circuit 10, the control end of the third switch S.sub.3 is connected to the output end of the pulse shaping circuit 5, and the output end of the third switch S.sub.3 is connected to the positive end of the first capacitor C.sub.1; the input end of the fourth switch S.sub.4 is connected to the output end of the CTAT current generation circuit 20, the control end of the fourth switch S.sub.4 is connected to the output end of the pulse shaping circuit 5, and the output end of the fourth switch S.sub.4 is connected to the positive end of the second capacitor C.sub.2.

(25) The control end of the third switch S.sub.3 and the control end of the fourth switch S.sub.4 are used for receiving control from the square wave signal CLK_INT output by the pulse shaping circuit 5, so when the square wave signal CLK_INT output by the pulse shaping circuit 5 is at high voltage-level, the third switch S.sub.3 and the fourth switch S.sub.4 are switched off, and the current I.sub.PTAT and the current I.sub.CTAT start to charge the first capacitor C.sub.1 and the second capacitor C.sub.2 respectively. When the square wave signal CLK_INT output by the pulse shaping circuit 5 is at low voltage-level, the third switch S.sub.3 and the fourth switch S.sub.4 are switched off, the first capacitor C.sub.1 and the second capacitor C.sub.2 stop charging, then charging continues when the square wave signal CLK_INT is at high voltage-level, the same process is repeated, until the voltage V.sub.P of the two ends of the first capacitor C.sub.1 and the voltage V.sub.N of the two ends of the second capacitor C.sub.2 respectively reach the threshold voltage V.sub.P,TH of the first level-detection circuit 12 and the threshold voltage V.sub.N,TH of the second level-detection circuit 22, the output signals of the first level-detection circuit 12 and the second level-detection circuit 22 are overturned, and therefore the time delay of the time delay signals formed by charging of the first capacitor C.sub.1 and the second capacitor C.sub.2 is in positive correlation to the cycle of the input clock, and the time delay signals can generate the pulse width in positive correlation to the cycle of the input clock signal.

(26) FIG. 6 shows a structure diagram of an embodiment II of a temperature sensor circuit of the present invention, in the embodiment, the first switch unit 11 is the first compound switch 13, the first compound switch 11 comprises a first N-type MOS (Metal Oxide Semiconductor) transistor NM1 and a first P-type MOS transistor PM1 that are connected with each other in parallel, a drain electrode of the first N-type MOS NM1 transistor is connected to a source electrode of the first P-type MOS transistor PM1 and then is connected to the output end of the PTAT current generation circuit 10, a source electrode of the first N-type MOS transistor NM1 is connected to a drain electrode of the first P-type MOS transistor PM1 and then is connected to the positive end of the first capacitor C.sub.1, a grid electrode of the first N-type MOS transistor NM1 is connected to the output end of the pulse shaping circuit 5, and a grid electrode of the first P-type MOS transistor PM1 is connected to the output end of the pulse shaping circuit 5 through a phase inverter, the second switch unit 12 is a second compound switch 23, the second compound switch 23 comprises a second N-type MOS transistor NM2 and a second P-type MOS transistor PM2 that are connected with each other in parallel, a drain electrode of the second N-type MOS transistor NM2 is connected to a source electrode of the second P-type MOS transistor PM2 and then is connected to the output end of the CTAT current generation circuit 20, a source electrode of the second N-type MOS transistor NM2 is connected to a drain electrode of the second P-type MOS transistor PM2 and then is connected to the positive end of the second capacitor C.sub.2, a grid electrode of the second N-type MOS transistor NM2 is connected to the output end of the pulse shaping circuit 5, and a grid electrode of the second P-type MOS transistor PM2 is connected to the output end of the pulse shaping circuit 5 through the phase inverter.

(27) The gird electrode of the first N-type MOS transistor NM1 and the control end of the first P-type MOS transistor PM1 are used for receiving control from the square wave signal CLK_INT output by the pulse shaping circuit 5, so when the square wave signal CLK_INT output by the pulse shaping circuit 5 is at high voltage-level, the first N-type MOS transistor NM1 and the first P-type MOS transistor PM1 are conducted at the same time, and the current I.sub.PTAT starts to charge the first capacitor C.sub.1; simultaneously, the second N-type MOS transistor NM2 and the second P-type MOS transistor PM2 are conducted at the same time, and the current I.sub.CTAT starts to charge the second capacitor C.sub.2. When the square wave signal CLK_INT output by the pulse shaping circuit 5 is at low voltage-level, the third switch S.sub.3 and the fourth switch S.sub.4 are switched off, the first capacitor C.sub.1 and the second capacitor C.sub.2 stop charging, then charging continues when the square wave signal CLK_INT is at high voltage-level, the same process is repeated, until the voltage V.sub.P of the two ends of the first capacitor C.sub.1 and the voltage V.sub.N of the two ends of the second capacitor C.sub.2 respectively reach the threshold voltage V.sub.N,TH of the first level-detection circuit 12 and the threshold voltage V.sub.N,TH of the second level-detection circuit 22, the output signals of the first level-detection circuit 12 and the second level-detection circuit 22 are overturned, and therefore the time delay signals in positive correlation to the cycle of the input clock signal are formed by the first capacitor C.sub.1 and the second capacitor C.sub.2.

(28) The first switch unit 11 and the second switch unit 21 of the present invention can be in a symmetrical structure and also be in an asymmetrical structure, namely, the first switch unit and the second switch unit can be any of the following four combinations: the first switch unit 11 is the third switch S.sub.3, and the second switch unit 21 is the fourth switch S.sub.4; the first switch unit 11 is the third switch S.sub.3, and the second switch unit 21 is the second compound switch 23; the first switch unit 11 is the first compound switch 13, and the second switch unit 21 is the fourth switch S.sub.4; the first switch unit 11 is the first compound switch 13, and the second switch unit 21 is the second compound switch 23.

(29) FIG. 7 shows a structure diagram of an embodiment I of a pulse shaping circuit of the present invention 5. The pulse shaping circuit comprises a current source, a third P-type MOS transistor PM3, a first amplifier 201, a first NOR (Nor OR) gate NOR1, a second NOR gate NOR2, a first buffer BUF1, a second buffer BUF2, a third capacitor C3 and a third N-type MOS transistor NM3,

(30) an output end of the current source is connected to a source electrode of the third P-type MOS transistor PM3, a drain electrode of the third P-type MOS transistor PM3 is connected to ground through the third capacitor C.sub.3, a positive input end of the first amplifier is connected to a drain electrode of the third P-type MOS transistor PM3, a negative input end of the first amplifier is connected to a first reference voltage end V.sub.R1, an output end of the first amplifier is connected to a second input end of the first NOR gate NOR1, a first input end of the first NOR gate NOR1 is connected to a reset signal end RESET, a third input end of the first NOR gate NOR1 is connected to an output end of the second NOR gate NOR2, the output end of the first NOR gate NOR 1 is connected to the first input end of the second NOR gate NOR 2 and an input end of the first buffer BUF1, an output end of the first buffer BUF1 is taken as the output end of the pulse shaping circuit, a second input end of the second NOR gate NOR2 is connected to the clock signal CLK as the input end of the pulse shaping circuit, an output end of the second NOR gate NOR2 is connected to a grid electrode of the third P-type MOS transistor PM3 and a grid electrode of the third N-type MOS transistor NM3 through the second buffer BUF2, a drain electrode of the third N-type MOS transistor NM3 is connected to a drain electrode of the third P-type MOS transistor PM3, and a source electrode of the third N-type MOS transistor NM3 is connected to ground.

(31) FIG. 8 is a structure diagram of an embodiment II of a pulse shaping circuit of the present invention; the differences between the embodiment II and the embodiment I are that a second input end of the second NOR gate NOR2 is connected to an output end of a second amplifier 202, a positive input end of the second amplifier 202 is connected to a second reference voltage end V.sub.R2, and a negative input end of the second amplifier 202 is connected to the clock signal CLK as the input end of the pulse shaping circuit.

(32) The pulse shaping circuit 5 is used for shaping the input clock signal CLK into the square wave signal CLK_INT with the same cycle with the input clock signal, the time of high voltage-level of the square wave signal within the cycle is a constant time, in order to ensure that the time lengths of high voltage-levels within the cycles are constant after different frequencies of clock signals are shaped by the pulse shaping circuit 5, it needs to ensure that the third capacitor C.sub.3 in the pulse shaping circuit 5 has the strictly constant capacity. For overcoming the defect of capacity inconsistency caused by the factors of process deviation and the like, the third capacitor C.sub.3 adopted by the pulse shaping circuit 5 of the present invention can adopt calibration technologies of laser trimming and the like or adopt an external capacitor with higher precision.

(33) FIG. 9 shows a structure diagram of a PTAT current generation circuit 10 of the present invention. As shown in the figure, the PTAT current generation circuit 10 comprises a fourth P-type MOS transistor PM4, a fifth P-type MOS transistor PM5, a sixth P-type MOS transistor PM6, a fourth N-type MOS transistor NM4, the fifth N-type MOS transistor NM5 and a first resistor R1.

(34) Source electrodes of the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5 and the sixth P-type MOS transistor PM6 are connected to a power supply V.sub.DD, and grid electrodes of the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5 and the sixth P-type MOS transistor PM6 are respectively connected with each other to form a current mirror. A drain electrode of the fourth P-type MOS transistor PM4 is connected with a drain electrode of the fourth N-type MOS transistor NM4, the drain electrode and a grid electrode of the fourth N-type MOS transistor NM4 are connected with each other, and a source electrode of the fourth N-type MOS transistor NM4 is connected to ground; a drain electrode and the grid electrode of the fifth P-type MOS transistor PM5 are connected with each other and then are simultaneously connected with a drain electrode of the fifth N-type MOS transistor NM5, a grid electrode of the fifth N-type MOS transistor NM5 is connected with the grid electrode of the fourth N-type MOS transistor NM4, a source electrode of the fifth N-type MOS transistor NM5 is connected with one end of the first resistor R1, and the other end of the first resistor R1 is connected to ground; the source electrode of the sixth P-type MOS transistor PM6 is connected to the power supply V.sub.DD, and a drain electrode of the sixth P-type MOS transistor PM6 is taken as the output current I.sub.PTAT of the output end of the PTAT current generation circuit 10.

(35) FIG. 10 shows a structure diagram of a CTAT current generation circuit 20 of the present invention. As shown in FIG. 10, the CTAT current generation circuit 20 comprises a seventh P-type MOS transistor PM7, an eighth P-type MOS transistor PM8, a third amplifier 203, a second resistor R2 and a diode D1.

(36) A positive power supply end of the third amplifier 203, a source electrode of the seventh P-type MOS transistor PM7 and a source electrode of the eighth P-type MOS transistor PM8 are commonly connected to the power supply V.sub.DD; a negative input end of the third amplifier 203 is connected with a positive electrode of the diode D1, and a negative electrode of the diode D1 is connected to ground; a positive input end of the third amplifier 203 is connected with a drain electrode of the seventh P-type MOS transistor PM7; a negative power supply end of the third amplifier 203 is directly connected to ground; a drain electrode of the seventh P-type MOS transistor PM7 is connected with one end of the second resistor R2, and the other end of the second resistor R2 is connected to ground; an output end of the third amplifier 203 is connected to a grid electrode of the seventh P-type MOS transistor PM7, a grid electrode of the eighth P-type MOS transistor PM8 is connected to the grid electrode of the seventh P-type MOS transistor PM7, the eighth P-type MOS transistor PM8 and the seventh P-type MOS transistor PM7 form a current mirror, and a drain electrode of the eighth P-type MOS transistor PM8 is taken as the output end of the CTAT current generation circuit 20 to output current I.sub.CTAT.

(37) In the present invention, the first level-detection circuit 12 in the PTAT time delay circuit 1 and the second level-detection circuit 22 in the CTAT time delay circuit 2 have the same structure, and the structure of the level-detection circuit is described in details below through combination with FIG. 11.

(38) As shown in FIG. 11, the level-detection circuit 12 comprises a comparator 121.

(39) A positive input end of the comparator 121 is taken as the input end V.sub.in of the level-detection circuit 12, a negative input end of the comparator 121 is connected to the reference voltage end, and an output end of the comparator 121 is taken as the output end V.sub.out of the level-detection circuit 12.

(40) FIG. 12 shows a comparison diagram of working sequence diagrams of two different frequencies of clock signals adopted by a temperature sensor circuit 100, and in order to show clearly, the relevant parts of the clock signals are only shown in the figure. As shown in the figure, after the first clock signal CLK1 is shaped by the pulse shaping circuit, the first square wave signal CLK_INT1 is output, the time length of high voltage-level within each cycle of the first square wave signal CLK_INT1 is constant as T.sub.pulse, and the frequency within each cycle of the first square wave signal CLK_INT1 is the same with that of the first clock signal CLK1. The first square wave signal CLK_INT1 is used for controlling the charging time of the first capacitor and the second capacitor; when the first square wave signal CLK_INT1 is at high voltage-level, the first capacitor and the second capacitor are charged; and when the first square wave signal CLK_INT1 is at low voltage-level, the first capacitor and the second capacitor stop to be charged. As the time of high voltage-level of the first square wave signal CLK_INT1 is constant as T.sub.pulse, it assumes that the effective charging time of the first capacitor is T.sub.pulse*n and the effective charging time of the second capacitor is T.sub.pulse*m (m and n are natural numbers), the time delay formed by the first capacitor is

(41) $T_{P,D}=n*T_{\mathrm{Pulse}}*\frac{T_{\mathrm{CLK}1}}{T_{\mathrm{Pulse}}},$
i.e., T.sub.N,D=m*T.sub.CLK1; similarly, the time delay formed by the second capacitor is

(42) $T_{N,D}=m*T_{\mathrm{Pulse}}*\frac{T_{\mathrm{CLK}1}}{T_{\mathrm{Pulse}}1},$
i.e., T.sub.N,D=m*T.sub.CLK1; and therefore the pulse signal PW is obtained through OR operation, and the pulse width of pulse signal PW is T.sub.PW1=(mn)*T.sub.CLK1. The counter adopts the first square wave signal CLK_INT1 to quantify the pulse width T.sub.PW1 of the pulse signal PW, the quantization result is

(43) $\frac{\left(m-n\right)*T_{\mathrm{CLK}1}}{T_{\mathrm{CLK}1}}=m-n*\mathrm{CLK}1\mathrm{cycle},$
and therefore in FIG. 12, the counting result k should be equal to mn.

(44) According to the same principle, when the clock signal is CLK2, after the second clock signal CLK2 is shaped by the pulse shaping circuit, the second square wave signal CLK_INT2 is output, the time length of high voltage-level within each cycle of the second square wave signal is constant as T.sub.pulse, and the frequency of high voltage-level with each cycle of the second square wave signal is the same with that of the second clock signal CLK2. The second square wave signal CLK_INT2 is used for controlling the charging time of the first capacitor and the second capacitor; when the second square wave signal CLK_INT2 is at high voltage-level, the first capacitor and the second capacitor are charged; and when the second square wave signal CLK_INT1 is at low voltage-level, the first capacitor and the second capacitor stop to be charged. As the time of high voltage-level of the second square wave signal CLK_INT2 is also constant as T.sub.pulse, the effective charging time of the first capacitor is also T.sub.Pulse*n, the effective charging time of the second capacitor is also T.sub.Pulse*m, similarly to the situation of the first clock signal, the result that the pulse width T.sub.PW2=(mn)*T.sub.CLK2 of the pulse signal PW is equal to (mn)*TCLK2 can be deducted in a similar way. The counter adopts the second square wave signal CLK_INT2 to quantify the pulse width T.sub.PW2, the quantization result is

(45) $\frac{\left(m-n\right)*T_{\mathrm{CLK}2}}{T_{\mathrm{CLK}2}}=m-n*\mathrm{CLK}2\mathrm{cycle},$
and therefore in FIG. 12, the counting result s should also be equal to mn.

(46) Based on the above analysis, although the first clock signal CLK1 and the second clock signal CLK2 have different frequencies, the temperature sensor of the present invention can output the same result mn for two different frequencies of clock signals. Therefore, the temperature output valve D.sub.out of the temperature sensor 100 is not affected by the frequency of the clock signal, thereby solving the problem that the temperature value read by the existing time domain integrated temperature sensor is inconsistent along with the change of the cycle of the clock signal when the temperature signal is processed by the TDC and improving the reading precision of the time domain integrated temperature sensor to a certain degree.

(47) FIG. 13 shows a working sequence diagram of the embodiment of the temperature sensor circuit 100 of the present invention. As shown in the figure, the cycle of a reference clock is T.sub.CLK, the cycle of the square wave signal output by the pulse shaping circuit 5 is the same with the cycle of the input clock signal, the time of high voltage-level with the cycle is T.sub.PULSE, the time delay T.sub.P,D of the rising edge of the output signal V.sub.P,D of the first level-detection circuit 12 is T.sub.P,D, i.e. n clock cycles, T.sub.CLK, the time delay T.sub.N,D of the rising edge of the output signal V.sub.N,D of the second level-detection circuit 22 is T.sub.N,D, i.e. m clock cycles T.sub.CLK, and the pulse width of the pulse signal output by the XOR gate is T.sub.PW.

(48) The output voltage V.sub.N,D of the second level-detection circuit 22 is taken as an example, the time delay T.sub.N,D of the rising edge thereof is calculated by the processes as follows:

(49) The voltage of two ends of the second capacitor C2 rises from 0 to V.sub.N,TH, the charging charge quantity of the second capacitor C.sub.2 is Q, and Q is obtained by the expression below:
Q=C.sub.2*V.sub.N,TH(1)

(50) wherein V.sub.N,TH is the threshold voltage of the second level-detection circuit 22, namely, when the input voltage thereof is higher than V.sub.N,TH, the output is high; and when the input voltage is lower than V.sub.N,TH, the output is low.

(51) On the other hand, during the period that the voltage of the two ends of the second capacitor C.sub.2 rises from 0 to V.sub.N,TH, the total charge quantity supplied by the charging current I.sub.CTAT should be equal to the charging charge quantity Q of the two ends of the second capacitor C.sub.2, and Q can be obtained by the expression below:
Q=m*T.sub.pulse*I.sub.CTAT(2)
T.sub.N,D=m*T.sub.CLK(3)

(52) Based on the above expressions (1), (2) and (3), the expression below is obtained:

(53) $\begin{array}{cc}{T}_{N,D}=\frac{C_2*V_{N,\mathrm{TH}}}{I_{\mathrm{CTAT}}*T_{\mathrm{pulse}}}*T_{\mathrm{CLK}}& \left(4\right)\end{array}$

(54) In a similar way, the charging charge quantity of the two ends of the first capacitor C1 can be obtained:
Q=C.sub.1*V.sub.P,TH(5)

(55) In addition, Q can be obtained by the expression below:
Q=n*T.sub.pulse*I.sub.PTAT(6)
T.sub.P,D=n*T.sub.CLK(7)

(56) Based on the above expressions (5), (6) and (7), the expression below is obtained:

(57) $\begin{array}{cc}{T}_{P,D}=\frac{C_1*V_{P,\mathrm{TH}}}{I_{\mathrm{PTAT}}*T_{\mathrm{pulse}}}*T_{\mathrm{CLK}}& \left(8\right)\end{array}$

(58) wherein V.sub.P,TH is the threshold voltage of the first level-detection circuit 12, and the pulse width T.sub.PW of the pulse signal can be obtained by the expression below:
T.sub.PW=T.sub.N,DT.sub.P,D(9)

(59) The above expressions (4) and (8) are substituted into the expression (9), obtaining:

(60) $\begin{array}{cc}{T}_{\mathrm{PW}}=\frac{T_{\mathrm{CLK}}}{T_{\mathrm{pulse}}}*\left(\frac{C_2*V_{N,\mathrm{TH}}}{I_{\mathrm{CTAT}}}-\frac{C_1*V_{P,\mathrm{TH}}}{I_{\mathrm{PTAT}}}\right)& \left(10\right)\end{array}$

(61) The output of the counter of the temperature sensor is obtained:

(62) $\begin{array}{cc}{D}_{\mathrm{out}}=\frac{T_{\mathrm{PW}}}{T_{\mathrm{CLK}}}=\frac{1}{T_{\mathrm{pulse}}}*\left(\frac{C_2*V_{N,\mathrm{TH}}}{I_{\mathrm{CTAT}}}-\frac{C_1*V_{P,\mathrm{TH}}}{I_{\mathrm{PTAT}}}\right)& \left(11\right)\end{array}$

(63) As seen from the above expression (11), the output D.sub.OUT of the counter of the temperature sensor circuit 100 is unrelated to the cycle T.sub.CLK of the clock signal, and therefore the temperature reading corresponding to the output D.sub.OUT of the counter is also unrelated to the cycle of the clock signal. Therefore, the temperature reading measured by the temperature sensor of the present invention is not affected by the change of the cycle of the clock signal, thereby ensuring the reading consistency of the temperature sensor under different clock signals and improving the measurement precision to a certain degree.