Radio frequency power amplifier

Abstract

An amplifier having a Radio Frequency (RF) power level detector circuit for producing a control signal in accordance with a power level of an RF input signal. The control signal indicates whether the power level of the input signal is within a predetermined range of power levels greater than zero. A bias circuit is fed by the control signal, for producing a fixed bias voltage at a gate electrode of a field effect transistor (FET) to establish a predetermined quiescent current for the FET when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels.

Claims

1. An amplifier, comprising: a Field Effect Transistor (FET); a Radio Frequency (RF) power level detector circuit for producing a control signal in accordance with a power level of an RF input signal, such control signal indicating whether the power level of the RF input signal is within a predetermined range of power levels greater than zero; and a bias circuit, connected to a voltage source and fed by the control signal, for producing a fixed bias voltage at a gate electrode of the FET to establish a predetermined quiescent current for the FET when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels greater than zero while the bias circuit is connected to the voltage source and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels while the bias circuit is connected to the voltage source.

2. An amplifier, comprising: a RF power level detector circuit/a control circuit fed by an RF input signal, for producing a control signal in accordance with a power level of the RF input signal, such control signal indicating whether the power level of the RF input signal is within a predetermined range of power levels greater than zero; an amplifier section, comprising: a field effect transistor having a gate for controlling a flow of carriers between a drain and a source of the field effect transistor; and a voltage source coupled to the drain; a reference potential connected to the source; wherein the drain provides an output for the amplifier section; and wherein the RF input signal is fed to the gate; and a bias circuit, connected to a voltage source and fed by the control circuit for producing a fixed bias to the gate to establish a predetermined drain quiescent current (Idq) for the field effect transistor when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels while the bias circuit is connected to the voltage source and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels while the bias circuit is connected to the voltage source.

3. The amplifier recited in claim 1 wherein the Field Effect Transistor (FET), the Radio Frequency (RF) power level detector circuit; and the bias circuit, are formed on a single Monolithic Microwave Integrated Circuit (MMIC) chip.

4. The amplifier recited in claim 2 wherein the RF power level detector circuit/a control circuit, the amplifier section, and the bias circuit, are formed on a single Monolithic Microwave Integrated Circuit (MMIC) chip.

Description

DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a diagrammatical sketch of a high power amplifier according to the PRIOR ART;

(2) FIG. 2 is an RF power amplifier circuit according to the disclosure; and

(3) FIG. 3 is a graph showing the relationship between a control signal produced by an RF power level detector circuit used in the RF power amplifier circuit of FIG. 2 and RF signal input power of an RF input signal fed to the RF power amplifier of FIG. 1.

(4) Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

(5) Referring now to FIG. 2, an amplifier circuit 10 is shown to include: an RF power level detector circuit 12; a control circuit 14; a bias circuit 16; and an RF amplifier 18, arranged as shown, all formed on Monolithic Microwave Integrated Circuit (MMIC) chip 11.

(6) The power amplifier 18 includes an output, depletion mode transistor Field Effect Transistor (FET) Q1 having a gate (G) for controlling a flow of carriers between a source (S) of the FET Q1 and the drain (D) of the FET Q1. The bias circuit 16 is coupled to the gate (G) through an inductor L1, as shown. A voltage source+V.sub.DD is connected to the drain (D) though an inductor L2, as shown. The source (S) is connected to a reference potential, here ground, (sometimes referred to as a common source connected FET). The drain (D) provides an output RF OUT for the amplifier 18 through capacitor C1, as shown. An input signal RF.sub.IN is fed to the gate electrode through a capacitor C2, as shown.

(7) The RF power level detector circuit 12 includes a plurality of serially connected diodes Da-Dd connected between RF.sub.IN and a terminal 20 through a de blocking capacitor Ca, as shown. The terminal 20 is connected to: a voltage source VEE, here, for example 5V volts relative to reference potential, here ground, through a resistor Ra; to the reference potential through a capacitor Cb; and to an output mode, or terminal, 22, through a resistor Rb, as shown. The RF power level detector circuit 12 produces a control signal at terminal 22 in accordance with a power level of an RF input signal fed to the input RF.sub.IN. The control signal indicates whether the power level of the input signal is within a predetermined range of power levels greater than zero. More particularly, as shown in FIG. 3, the control signal (voltage) at terminal 22 is VEE in the absence of an RF signal being applied to terminal RF.sub.IN (the RF input signal power level is zero) and the control signal at terminal 22 is more positive than VEE over the predetermined range of power levels ranging from power level P1 (established by the number of serially connected diodes) to a greater power level P2 where P1 is greater than zero; that is, when the input RF is present. The range between P1 and P2 is selected to prevent the power dissipation within the FET Q.sub.1, even in the absence of an RF input signal, from being no higher than the power dissipated under full RF drive, where the power dissipated under full RF drive is equal to the sum of the DC power applied to the output FET Q.sub.1 (the product of the drain voltage V.sub.DD and drain current) and the amount of RF power applied to the output FET Q.sub.1 minus the amount of power produced at the output of the output FET Q.sub.1.

(8) The control circuit 14 (FIG. 2) includes: a voltage level shifting section 14a comprising: a depletion mode FET Q5 configured as a current source and a depletion mode FET Q6 configured as a switch connected between +V.sub.DD and ground, for shifting the voltages input level swing at terminal 22 from between VEE and a voltage above ground (as discussed in connection with FIG. 3) to an output voltage swing at terminal 23 between +V.sub.DD (in the absence of an RF input signal) and ground; and a voltage inverter section 14b comprising: a depletion mode FET Q7 configured as a current source; a depletion mode FET Q8 configured as a switch and a plurality of diodes, here for example three diodes in D1-3, serially connected between V.sub.DD and ground, as shown, to invert the voltage signal at terminal 23 and produce such inverted voltage swing at terminal 24; and a switch section 14c, comprising a depletion mode FET (Q9) connected between V.sub.DD and the bias circuit 16, as shown. When the switch 14c is closed, as when the control signal at terminal 22 indicates the power level of the RF input at terminal RF.sub.IN is greater than the predetermined power level (that the RF input signal is present), the control circuit 14 allows the bias circuit 16 to operate normally and produce a predetermined gate bias voltage for the amplifier 18 to that a predetermined quiescent drain current, I.sub.dq, passes from +V.sub.DD to the drain (D) of FET Q1; and, on the other hand, when the switch 14c is open, as when the control signal at terminal 22 indicates the power level of the RF input at terminal RF.sub.IN is at or below the predetermined power level (the RF input signal is absent), the control circuit 14 transistor Q9 becomes non-conducting. As will be described in more detail below in connection with bias circuit 16, when FET Q9 is off (non-conducting), the gate (G) of FET Q1 goes to V.sub.SS (here 5 volts) and pinches off FET Q1 with the result that quiescent drain current, I.sub.dq, is removed (goes to zero).

(9) The bias circuit 16, comprises: a current mirror having: a current source I.sub.ref, and biasing circuitry (depletion mode transistors Q2, Q3, and Q4 and diodes Dn) arranged as shown, coupled to the current source I.sub.ref, and between the potential more positive than the reference potential (+V.sub.DD) and a potential more negative than the reference potential; coupled to a potential more negative than the reference potential (V.sub.SS). It should be noted that the diodes Dn is a series of a plurality n of diodes GaN diodes Dn, where n is the number of diodes in the series selected in accordance with the voltages used, here for example, V.sub.DD is 24 volts and V.sub.SS is 8.0 volts. One such circuit is described in U. S. Patent Application Publication No. US 2016/0373074 A1 Published Dec. 22, 2016, inventors Bettencourt et al, assigned to the same assignee as the present patent application. The bias circuit 16 is a depletion mode current mirror circuit for quiescent bias control of the amplifier 18 where Q2 is a Gallium Nitride (GaN) mirror FET and Q1 is the GaN HEMT. The reference current source Iref fed to FET Q2 controls the quiescent current I.sub.dq for FET Q1. The current source I.sub.ref may be a saturated resistor as described in U.S. Pat. No. 8,854,140 or a linear resistor, transistor or from an off chip reference if needed.

(10) Thus, RF power level detector circuit 12 produces a control signal at terminal 22 in accordance with a power level of an RF input signal applied to the power amplifier 10. The control signal indicates whether the RF input signal is being applied to the power amplifier 18 is within the predetermined range of power levels or less than the predetermined power level (in absence of such RF signal being applied to the power amplifier 10). After passing through the control circuit 14, the bias circuit 16 produces a predetermined gate bias voltage (Vg) at a gate of the output FET to establish a predetermined constant quiescent drain current, Idq, during a period of time when the RF input signal is indicated as being present (the power level is within the predetermined range of power levels) and applies a more negative voltage at a gate of the output FET and hence removes quiescent drain current, Idq when the control signal indicates the absence of such RF signal (the power level is less than the predetermined range of power levels). More particularly, when the switch 14c (FET Q9) is closed, as when the control signal at terminal 22 indicates the power level of the RF input at terminal RF.sub.IN is within the predetermined power level, FET Q9 conducts and Iref passes to FETS Q2 and Q3 to produce the predetermined bias voltage at the gate of FET Q1 establishing the predetermined quiescent drain current, I.sub.dq, for FET Q1; and, on the other hand, when the control signal at terminal 22 indicates the power level of the RF input at terminal RF.sub.IN is at or below the predetermined power level (the RF input signal is absent), FET Q9 is non-conducting and the gate (G) of FET Q1 goes to V.sub.SS (here 8 volts) and pinches off FET Q1 with the result that quiescent drain current, I.sub.dq, is removed (goes to zero).

(11) A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example other RF power detector circuits may be used to detect the presence or absence of the RF input signal. Accordingly, other embodiments are within the scope of the following claims.