Method and device for measuring the frequency of a signal

Abstract

A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.

Claims

1. A method for determining a frequency of a signal comprising using a frequency determining device, the method comprising: a) counting a number of whole periods of the signal during a first period of a periodic reference signal; b) repeating step a) for each period of the periodic reference signal until a first duration is equal to a first quantity of periods of the periodic reference signal; c) determining a first average of the numbers of whole periods; d) repeating at least one of steps a), b) and c) and at each repetition shifting a start of the counting of step a) by at least one period of the periodic reference signal; e) determining a second average of the first averages; and f) determining the frequency of the signal from the second average and the frequency of the periodic reference signal, wherein the frequency determining device comprises: a counter to count the number of whole periods of the signal, a setpoint counter incremented during a first portion of a second quantity of periods of the periodic reference signal and decremented during a second portion of the second quantity of periods of the periodic reference signal, a multiplier having a first input coupled to an output of the counter and a second input coupled to an output of the setpoint counter, an accumulator coupled to an output of the multiplier, and a shifter coupled to an output of the accumulator to perform a division by bit-right shifting, wherein an output of the shifter corresponds to the second average.

2. The method according to claim 1, wherein the repetitions of steps a), b) and c) are performed in parallel.

3. The method according to claim 1, wherein steps a) to e) are implemented by applying the following formula: $M2=\frac{1}{R}\left(\underset{k=1}{\overset{R}{.Math.}}\frac{1}{S}\underset{i=k}{\overset{k+S-1}{.Math.}}{C}_i\right)$ wherein M2 designates the second average, S corresponds to the first quantity of periods, R corresponds to a number of repetitions of steps during step d), and C.sub.i corresponds to the number of whole periods of the signal counted during a current period of the periodic reference signal.

4. The method according to claim 1, wherein the repetitions of steps a, b) and c) is equal to a second quantity of periods of the periodic reference signal reduced by the first quantity of periods.

5. The method according to claim 4, wherein the first quantity and the second quantity of periods are powers of two.

6. The method according to claim 5, wherein the first quantity of periods is equal to half the second quantity of periods.

7. The method according to claim 6, wherein steps a) to e) are implemented by applying the following formula: $M2=\frac{1}{P-S}\frac{1}{S}\left(\underset{i=1}{\overset{S}{.Math.}}i{C}_i+\underset{i=S+1}{\overset{P-1}{.Math.}}\left(P-i\right)C_i\right)$ wherein M2 designates the second average, S corresponds to the first quantity of periods, P corresponds to the second quantity of periods and C.sub.icorresponds to the number of whole periods of the signal counted during a current period of the periodic reference signal.

8. The method according to claim 5, wherein the first quantity of periods is less than half the second quantity of periods.

9. The method according to Claim 8, wherein steps a) to e) are implemented by applying the following formula: $M2=\frac{1}{P-S}\frac{1}{S}\left(\underset{i=1}{\overset{S}{.Math.}}i{C}_i+\underset{i=S+1}{\overset{P-S}{.Math.}}S{C}_i+\underset{i=P-S+1}{\overset{P-1}{.Math.}}\left(P-i\right)C_i\right)$ wherein M2 designates the second average, S corresponds to the first quantity of periods, P corresponds to the second quantity of periods and C.sub.i corresponds to the number of whole periods of the signal counted during a current period of the periodic reference signal.

10. The method according to claim 1, wherein in steps b) and c) accounting for the numbers of whole periods of the signal already counted during the at least one preceding group of steps a) and b).

11. A method for determining a frequency of a signal from a periodic reference signal using a frequency determining device, the method comprising: determining an average M2 obtained by the following formula $M2=\frac{1}{P-S}\frac{1}{S}\left(\underset{i=1}{\overset{S}{.Math.}}i{C}_i+\underset{i=S+1}{\overset{P-1}{.Math.}}\left(P-i\right)C_i\right)$ wherein S is a first quantity of periods of the periodic reference signal, P is a second quantity of periods of the periodic reference signal, P and S being powers of two with S equal to P/2, and C.sub.i corresponds to a number of whole periods of the signal counted during a current period of the periodic reference signal; and determining the frequency of the signal from the average M2 and a frequency of the periodic reference signal, wherein the frequency determining device comprises: a counter to count the number of whole periods of the signal, a setpoint counter incremented during a first portion of the second quantity of periods of the periodic reference signal and decremented during a second portion of the second quantity of periods of the periodic reference signal, a multiplier having a first input coupled to an output of the counter and a second input coupled to an output of the setpoint counter, an accumulator coupled to an output of the multiplier, and a shifter coupled to an output of the accumulator to perform a division by bit-right shifting, wherein an output of the shifter corresponds to the average M2.

12. A method for determining a frequency of a signal from a periodic reference signal using a frequency determining device, the method comprising: determining an average M2 obtained by the following formula $M2=\frac{1}{P-S}\frac{1}{S}\left(\underset{i=1}{\overset{S}{.Math.}}i{C}_i+\underset{i=S+1}{\overset{P-S}{.Math.}}S{C}_i+\underset{i=P-S+1}{\overset{P-1}{.Math.}}\left(P-i\right)C_i\right)$ wherein S is a first quantity of periods of the periodic reference signal, P is a second quantity of periods of the periodic reference signal, P and S being powers of two with S less than P/2, and C.sub.i corresponds to a number of whole periods of the signal counted during a current period of the periodic reference signal; and determining the frequency of the signal from the average M2 and a frequency of the periodic reference signal, wherein the frequency determining device comprises: a counter to count the number of whole periods of the signal, a setpoint counter incremented during a first portion of the second quantity of periods of the periodic reference signal and decremented during a second portion of the second quantity of periods of the periodic reference signal, a multiplier having a first input coupled to an output of the counter and a second input coupled to an output of the setpoint counter, an accumulator coupled to an output of the multiplier, and a shifter coupled to an output of the accumulator to perform a division by bit-right shifting, wherein an output of the shifter corresponds to the average M2.

13. A device to determine a frequency of a signal from a periodic reference signal, the device comprising: a processor configured to: a) count a number of whole periods of the signal during a first period of the periodic reference signal, b) repeat step a) for each other period of the periodic reference signal during a first duration equal to a first quantity of periods of the periodic reference signal, c) determine a first average of the numbers of whole periods, d) repeat at least one of steps a), b) and c), and at each repetition to shift a start of the counting of step a) by at least one period of the periodic reference signal, e) determine a second average of the first averages, and f) determine the frequency of the signal from the second average and a frequency of the periodic reference signal, wherein the processor comprises: a counter configured to count the number of whole periods of the signal, a setpoint counter configured to be incremented during a first portion of a second quantity of periods of the periodic reference signal and decremented during a second portion of the second quantity of periods of the periodic reference signal, a multiplier having a first input coupled to an output of the counter and a second input coupled to an output of the setpoint counter, an accumulator coupled to an output of the multiplier, and a shifter coupled to an output of the accumulator and configured to perform a division by bit-right shifting, wherein an output of the shifter corresponds to the second average.

14. The device according to claim 13, wherein the processor is configured to perform the repetitions of steps a), b) and c) in parallel.

15. The device according to claim 13, wherein the processor is configured to implement steps a) to e) by applying the following formula: $M2=\frac{1}{R}\left(\underset{k=1}{\overset{R}{.Math.}}\frac{1}{S}\underset{i=k}{\overset{k+S-1}{.Math.}}{C}_i\right)$ wherein M2 corresponds to the second average, S corresponds to the first quantity, R corresponds to a number of repetitions of steps during step d), and C.sub.i corresponds to the number of whole periods of the signal counted during a current period of the periodic reference signal.

16. The device according to claim 15, wherein R is equal to a second quantity of periods of the periodic reference signal reduced by the first quantity of periods.

17. The device according to claim 16, wherein the first quantity and the second quantity of periods are powers of two.

18. The device according to claim 17, wherein the first quantity of periods is half the second quantity of periods and the processor is configured to implement steps a) to e) by applying the following formula: $M2=\frac{1}{P-S}\frac{1}{S}\left(\underset{i=1}{\overset{S}{.Math.}}i{C}_i+\underset{i=S+1}{\overset{P-1}{.Math.}}\left(P-i\right)C_i\right)$ wherein M2 corresponds to the second average, S corresponds to the first quantity of periods, P corresponds to the second quantity of periods, and C.sub.i corresponds to the number of whole periods of the signal counted during a current period of the periodic reference signal.

19. The device according to claim 13 , wherein in steps b) and c) accounting for the numbers of whole periods of the signal already counted during the at least one preceding group of steps a) and b).

20. A device to determine a frequency of a signal from a periodic reference signal, the device comprising: a processor configured to: determine an average M2 obtained by the following formula $M2=\frac{1}{P-S}\frac{1}{S}\left(\underset{i=1}{\overset{S}{.Math.}}i{C}_i+\underset{i=S+1}{\overset{P-1}{.Math.}}\left(P-i\right)C_i\right)$ wherein S is a first quantity of periods of the periodic reference signal, P is a second quantity of periods of the periodic reference signal, P and S being powers of two with S equal to P/2, and C.sub.i corresponds to a number of whole periods of the signal counted during a current period of the periodic reference signal, and determine a frequency of the signal from the average M2 and a frequency of the periodic reference signal, wherein the processor comprises: a counter configured to count the number of whole periods of the signal; a setpoint counter configured to be incremented during a first portion of a second quantity of periods of the periodic reference signal and decremented during a second portion of the second quantity of periods of the periodic reference signal; a multiplier having a first input coupled to an output of the counter and a second input coupled to an output of the setpoint counter; an accumulator coupled to an output of the multiplier; and a shifter coupled to an output of the accumulator and configured to perform a division by bit-right shifting, wherein an output of the shifter corresponds to the average M2.

21. A device to determine a frequency of a signal from a periodic reference signal, the device comprising: a processor configured to: determine an average M2 obtained by the following formula $M2=\frac{1}{P-S}\frac{1}{S}\left(\underset{i=1}{\overset{S}{.Math.}}i{C}_i+\underset{i=S+1}{\overset{P-1}{.Math.}}\left(P-i\right)C_i\right)$ wherein S is a first quantity of periods of the periodic reference signal, P is a second quantity of periods of the periodic reference signal, P and S being powers of two with S equal to P/2, and C.sub.i corresponds to a number of whole periods of the signal counted during a current period of the periodic reference signal, and determine a frequency of the signal from the average M2 and a frequency of the periodic reference signal, wherein the processor comprises: a counter configured to count numbers of whole periods of the signal; a setpoint counter configured, during P1 reference periods of the periodic reference signal, to be incremented by one at each new reference period up to the first quantity of periods then being decremented by one at each new reference period; a multiplier having two inputs coupled respectively to outputs of the counter and the setpoint counter; an accumulator coupled at an output of the multiplier; and a shifter coupled to an output of the accumulator and configured to perform a bit shift corresponding to a division by a product of the first quantity of periods by a difference between the second quantity and the first quantity of periods.

22. The device according to claim 17, wherein the first quantity of periods is less than half the second quantity of periods and the processor is configured to implement steps a) to e) by applying the following formula: $M2=\frac{1}{P-S}\frac{1}{S}\left(\underset{i=1}{\overset{S}{.Math.}}i{C}_i+\underset{i=S+1}{\overset{P-S}{.Math.}}S{C}_i+\underset{i=P-S+1}{\overset{P-1}{.Math.}}\left(P-i\right)C_i\right)$ wherein M2 corresponds to the second average, S corresponds to the first quantity of periods, P corresponds to the second quantity of periods, and C.sub.i corresponds to the number of whole periods of the signal counted during a current period of the periodic reference signal.

23. A device to determine a frequency of a signal from a periodic reference signal comprising: a processor configured to determine an average M2 obtained by the following formula: $M2=\frac{1}{P-S}\frac{1}{S}\left(\underset{i=1}{\overset{S}{.Math.}}i{C}_i+\underset{i=S+1}{\overset{P-S}{.Math.}}S{C}_i+\underset{i=P-S+1}{\overset{P-1}{.Math.}}\left(P-i\right)C_i\right)$ wherein S is a first quantity of periods of the periodic reference signal, P is a second quantity of periods of the periodic reference signal, P and S being powers of two with S less than P/2 and C.sub.i corresponds to a number of whole periods of the signal counted during a current period of the periodic reference signal, and determine the frequency of the signal from the average M2 and a frequency of the periodic reference signal, wherein the processor comprises: a counter configured to count numbers of whole periods of the signal, a setpoint counter configured, during P1 reference periods of the periodic reference signal, to be incremented by one at each new reference period up to the first quantity, then being kept at the first quantity during a number of reference periods equal to a difference between P1 and 2S, and then being decremented by one at each new reference period, a multiplier having two inputs coupled respectively to outputs of the counter and the setpoint counter, an accumulator coupled at an output of the multiplier, and a shifter coupled to an output of the accumulator and configured to perform a bit shift corresponding to a division by the product of S by PS.

24. The device according to claim 23, wherein the device further comprises a decoder coupled between the counter and the multiplier, wherein the decoder is configured to reset the counter to zero each period of the periodic reference signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will appear on examination of the detailed description of implementations and embodiments of the invention, in no way restrictive, and the attached drawings in which:

(2) FIG. 1 is a graph of a frequency of a signal SIG and a periodic reference signal REF in accordance with the invention;

(3) FIG. 2 is a schematic diagram of a device to determine the frequency of the signal of FIG. 1 from a periodic reference signal;

(4) FIG. 3 is a graph of a setpoint counter of FIG. 2 being incremented and decremented in accordance with the invention;

(5) FIG. 4 is a graph of the frequency of the signal SIG and the periodic reference signal REF in accordance with an embodiment of the invention;

(6) FIG. 5 is a schematic diagram of a device to determine the frequency of the signal of FIG. 4 from a periodic reference signal in accordance with an embodiment of the invention; and

(7) FIG. 6 illustrates a graph of the setpoint counter of FIG. 5 being incremented and decremented in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

(8) FIG. 1 illustrates an example of a method for determining a frequency of a periodic signal SIG, from a periodic reference signal REF.

(9) The reference signal REF may be, for example, but not restrictively a reference signal of a phase-locked loop, and the signal SIG may be, for example, but not restrictively the signal delivered by a voltage-controlled oscillator forming part of this same phase-locked loop.

(10) In the rest of the description, the index i will be used to represent the various elements associated with a period P.sub.i of the reference signal, Thus, an index 1 is associated with the period P.sub.1, an index 2 with the period P.sub.2, etc.

(11) In a first step a) of the method a count is performed of a number C.sub.i of whole periods of the first signal SIG during a first reference period P.sub.1 of the reference signal REF.

(12) The count a) is repeated (step b)) for each other successive period P.sub.i of the reference signal REF, during a first quantity S of reference periods P.sub.i.

(13) In this example S=4. Thus successive counts are performed of the numbers C.sub.1, C.sub.2, C.sub.3 and C.sub.4 of whole periods of the first signal SIG taking place during the successive periods P.sub.1, P.sub.2, P.sub.3 and P.sub.4.

(14) Then (step c)) a first average M11 is determined of the different numbers C.sub.i counted during the four repetitions of the first step a). In this example, the first average M11 will be equal to the sum of the numbers C.sub.1, C.sub.2, C.sub.3 and C.sub.4, divided by the first quantity S=4.

(15) Steps a) to c) are repeated a quantity of times equal to the difference between a second quantity P of reference periods and the first quantity S=4, by shifting the start of the counting of a reference period P.sub.i at each repetition.

(16) In this example P=8. Thus PS=4 first averages M11, M12 , M13 and M14 are determined in parallel each relating to 4 successive numbers C.sub.i.

(17) M11 is thus the average of the numbers C.sub.1 to C.sub.4, M12 the average of the numbers C.sub.2 to C.sub.5, M13 the average of the numbers C.sub.3 to C.sub.6, and M14 the average of the numbers C.sub.3 to C.sub.7.

(18) Finally, a second average M2 is determined on the values of the first averages M11, M12, M13, and M14.

(19) Here, the value of the second average M2 is thus equal to the sum of the first averages M11, M12, M13 and M14, divided by PS=4.

(20) In order to obtain the frequency of the first signal, the frequency of the reference signal is then multiplied by the value of the second average M2.

(21) The method thus implemented is equivalent to applying the following first formula F1:

(22) $\begin{array}{cc}M2=\frac{1}{P-S}*\left(\underset{k=1}{\overset{P-S}{.Math.}}\frac{1}{S}\underset{i=k}{\overset{k+S-1}{.Math.}}{C}_i\right)& \left(\mathrm{F1}\right)\end{array}$

(23) This formula could be implemented in a software form e.g. within a microcontroller.

(24) However, the inventors have observed that by selecting the first quantity S and the second quantity P as powers of two and particularly by selecting

(25) $S=\frac{P}{2},$
the method is equivalent to applying the following second formula F2:

(26) 0$\begin{array}{cc}M2=\frac{1}{P-S}\frac{1}{S}\left(\underset{i=1}{\overset{S}{.Math.}}i{C}_i+\underset{i=S+1}{\overset{P-1}{.Math.}}\left(P-i\right)C_i\right)& \left(\mathrm{F2}\right)\end{array}$

(27) This formula is particularly advantageous since it can be used to apply the formula not only with software means, but also with simple hardware means such as those of the device DIS1 illustrated in FIG. 2.

(28) It is then also possible not to repeat the counting of certain numbers C.sub.i at each repetition and to keep these numbers C.sub.i for subsequently weighting them.

(29) The device DIS1 in FIG. 2 here includes a counting means 1, receiving as input the reference signal REF and the first signal SIG. The counting means 1 is configured for counting each number C.sub.i of whole periods of the first signal SIG taking place during each reference period P.sub.i.

(30) In this example, the counting means 1 includes a counter 11 clocked by the signal REF associated with a decoder 12.

(31) The counter 11 is configured for being incremented at each period of the signal SIG, and the decoder 12 is configured for resetting the counter 11 to zero at each reference period P.sub.i.

(32) The device DIS1 also includes a setpoint counter 2a configured for delivering a counter value V.sub.i at each reference period P.sub.i of the reference signal.

(33) As illustrated in FIG. 3, the counter 2a is in this example configured, during the P1=7 reference periods P.sub.1 to P.sub.7, for being incremented by one at each new reference period P.sub.i up to the first quantity S=4 then being decremented by one at each new reference period P.sub.i.

(34) Thus, the value V.sub.i of the setpoint counter will be successively equal to 1, 2, 3, 4, 3, 2, 1 respectively during the reference periods P.sub.1, P.sub.2, P.sub.3, P.sub.4, P.sub.5, P.sub.6, P.sub.7.

(35) The outputs of the counting means 1 and the setpoint counter 2a are both connected to a multiplier 3 (FIG. 2). Thus, each successive number C.sub.i is multiplied by the associated counter value V.sub.i.

(36) An accumulator 4 comprises an asynchronous adder 40 and a register 41 for synchronizing the sums to be performed. A first input of the adder is connected at the output of the multiplier 3 so as to receive each number C.sub.i multiplied by its associated counter value V.sub.i. The output of the register 41 is looped back onto a second input of the adder. Initially, the accumulator 4 contains a zero value.

(37) At each reference period P.sub.i, the accumulator stores the output value of the multiplier and adds it together with the previously stored value. The sum of the stored values is returned on the second input of the adder 40 and synchronized by the register 41.

(38) The sum finally stored is therefore equal to
C.sub.1+2*C.sub.2+3*C.sub.1+4*C.sub.4+3*C.sub.5+2*C.sub.6+C.sub.7

(39) The device further includes a shifting means 6, e.g. a software module, configured for performing a bit shift on the binary value of the stored sum and delivering the second average M2.

(40) In this example, the bit shift corresponds to a division by the product (PS)*S=16, i.e. a 4-bit right shift.

(41) It should be noted that the division thus performed by a bit shift is possible thanks to the selection of powers of 2 for the first quantity S and the second quantity P.

(42) Thus it is possible, for a 16 MHZ reference signal, to obtain an accuracy of 62.5 kHz in a number of periods of the reference signal equal to 32, while 256 periods of the reference signal would have been required with a conventional counter.

(43) According to another implementation illustrated in FIGS. 4 to 6, S is selected less than

(44) $\frac{P}{2},$
e.g. S=2 and P=8.

(45) Thus successive counts are performed of the numbers C.sub.i of whole periods of the signal SIG taking place during two successive periods P.sub.i.

(46) Then the average M11 is determined of the two numbers C.sub.1 and C.sub.2 counted during the two reference periods P.sub.1 and P.sub.2.

(47) This step of the method is repeated a quantity of times equal to PS=6, by shifting the start of the counting of a reference period P.sub.i at each repetition.

(48) Thus 6 averages M11, M12, M13, M14, M15 and M16 are determined in parallel, each relating to 2 successive numbers C.sub.i.

(49) Finally, a second average M2 is determined on the values of the first averages M11, M12, M13, M14, M15 and M16.

(50) The inventors have noticed that by selecting S<

(51) $\frac{P}{2},$
with P and S as powers of two, the above formula F1 is equivalent to the following formula F3:

(52) $\begin{array}{cc}M2=\frac{1}{P-S}\frac{1}{S}\left(\underset{i=1}{\overset{S}{.Math.}}i{C}_i+\underset{i=S+1}{\overset{P-S}{.Math.}}S{C}_i+\underset{i=P-S+1}{\overset{P-1}{.Math.}}\left(P-i\right)C_i\right)& \left(\mathrm{F3}\right)\end{array}$

(53) This formula can be used to apply this method with software means, but also again with simple hardware means such as the device DIS2 illustrated in FIG. 5 while avoiding repetitive counts of certain numbers C.sub.i.

(54) This device DIS2 is similar to the device DIS1 illustrated in FIG. 2 and described previously, but differs in that it includes a setpoint counter 2b configured differently.

(55) FIG. 6 illustrates a possible operation of the setpoint counter 2b in the case where P=8 and S=2.

(56) Here the counter is configured for being incremented at the second reference period P.sub.2, then during five reference periods P.sub.2 to P.sub.6 for being kept at a value equal to two, and then for being decremented once during the reference period P.sub.7.

(57) Thus, the sum finally stored by the accumulator is therefore
C.sub.1+2*C.sub.2+2*C.sub.1+2*C.sub.4+2*C.sub.5+2*C.sub.6+C.sub.7

(58) In this embodiment also, the division again comprises a bit shift on the accumulator value, and this is possible thanks to the selection of powers of two for the first quantity S and the second quantity P.

(59) Although implementations and embodiments of the invention have been described here in which the second quantity P is 8 and the first quantity S is 2 or 4, the invention is compatible with any other first quantity and any other second quantity, whether or not these two quantities are powers of two, so long as S is less than P. The fact that S and P are powers of two enables a particularly compact integrated embodiment to be obtained and the division by S (PS) to be performed by a simple bit shift.