Semiconductor chip

Abstract

A semiconductor chip (20) is described comprising a semiconductor layer sequence (10) based on a phosphide compound semiconductor material or arsenide compound semiconductor material wherein the semiconductor layer sequence (10) contains a p-type semiconductor region (4) and an n-type semiconductor region (2). The n-type semiconductor region (2) comprises a superlattice structure (20) for improving current spreading, wherein the superlattice structure (20) has a periodic array of semiconductor layers (21, 22, 23, 24). A period of the superlattice structure (20) has at least one undoped first semiconductor layer (21) and a doped second semiconductor layer (22), wherein an electronic band gap E.sub.2 of the doped second semiconductor layer (22) is larger than an electronic band gap E.sub.1 of the undoped first semiconductor layer (21).

Claims

1. A semiconductor chip having a semiconductor layer sequence having one or more layers comprising a III-phosphide compound semiconductor material or III-arsenide compound semiconductor material, wherein the semiconductor layer sequence contains a p-type semiconductor region and an n-type semiconductor region, wherein the n-type semiconductor region comprises a superlattice structure for improving current spreading, the superlattice structure having a periodic arrangement of semiconductor layers, a period of the superlattice structure has at least one undoped first semiconductor layer and a doped second semiconductor layer, an electronic band gap E.sub.2 of the doped second semiconductor layer being larger than an electronic band gap E.sub.1 of the undoped first semiconductor layer, the undoped first semiconductor layer is arranged in the superlattice structure in each case between an undoped first intermediate layer and an undoped second intermediate layer.

2. The semiconductor chip according to claim 1, wherein the undoped first semiconductor layer comprises In.sub.0.5Al.sub.x1Ga.sub.0.5-x1P, where 0x10.27, or Al.sub.y1Ga.sub.1-y1As, where 0y1<0.4, and the doped second semiconductor layer comprises In.sub.0.5Al.sub.x2Ga.sub.0.5-x2P, where 0x20.5 and x1<x2, or Al.sub.y2Ga.sub.1-y2As, where 0<y21 and y1<y2.

3. The semiconductor chip according to claim 2, wherein the aluminum content x1 of the undoped first semiconductor layer is less than 0.25.

4. The semiconductor chip according to claim 1, wherein the doped second semiconductor layer has a dopant concentration between 110.sup.16 cm.sup.3 and 110.sup.20 cm.sup.3.

5. The semiconductor chip according to claim 1, wherein a thickness of the undoped first semiconductor layer is between 3 nm and 15 nm.

6. The semiconductor chip according to claim 1, wherein a thickness of the doped second semiconductor layer is between 20 nm and 30 nm.

7. The semiconductor chip according to claim 1, wherein the undoped first intermediate layer and the undoped second intermediate layer have the same electronic band gap E.sub.2 as the doped second semiconductor layer.

8. The semiconductor chip according to claim 1, wherein a thickness of the undoped first intermediate layer and/or the undoped second intermediate layer is between 0.5 nm and 20 nm.

9. The semiconductor chip according to claim 1, wherein the superlattice structure has between 5 and 70 periods.

10. The semiconductor chip according to claim 1, wherein a specific resistance of the superlattice structure is less than 0.05 cm.

11. The semiconductor chip according to claim 1, wherein the semiconductor chip is an optoelectronic semiconductor chip, and the optoelectronic semiconductor chip has an active layer disposed between the p-type semiconductor region and the n-type semiconductor region.

12. The semiconductor chip according to claim 11, wherein the active layer has a quantum well structure having at least one quantum well layer and at least one barrier layer, and wherein the electronic band gap E.sub.1 of the undoped first semiconductor layer of the superlattice structure is larger than an electronic band gap E.sub.QW of the at least one quantum well layer of the quantum well structure.

13. A semiconductor chip having a semiconductor layer sequence having one or more layers comprising a III-phosphide compound semiconductor material or III-arsenide compound semiconductor material, wherein the semiconductor layer sequence contains a p-type semiconductor region and an n-type semiconductor region, wherein the n-type semiconductor region comprises a superlattice structure for improving current spreading, the superlattice structure having a periodic arrangement of semiconductor layers, a period of the superlattice structure has at least one undoped first semiconductor layer and a doped second semiconductor layer, an electronic band gap E.sub.2 of the doped second semiconductor layer being larger than an electronic band gap E.sub.1 of the undoped first semiconductor layer, the undoped first semiconductor layer is arranged in the superlattice structure in each case between an undoped first intermediate layer and an undoped second intermediate layer, the period of the superlattice structure consists of four layers, wherein in each period an undoped first intermediate layer, the undoped first semiconductor layer, an undoped second intermediate layer and the doped second semiconductor layer follow one another.

Description

(1) In the figures:

(2) FIG. 1 shows a schematic representation of a cross-sectional view of an optoelectronic semiconductor chip according to a first embodiment,

(3) FIG. 2 shows a schematic graphic representation of the electron density n.sub.e in the superlattice structure for an exemplary embodiment as a function of a local coordinate z running perpendicular to the layer planes,

(4) FIG. 3 shows a schematic graphic representation of the electronic band structure in the superlattice structure according to an embodiment, and

(5) FIG. 4 shows a schematic representation of a cross-sectional view of an optoelectronic semiconductor chip according to a second embodiment.

(6) Identical or similar elements are provided with the same reference signs in the figures. The sizes of the individual elements and the proportions of the elements among each other are not to be regarded as true to scale.

(7) The optoelectronic semiconductor chip 100 shown in FIG. 1 contains a semiconductor layer sequence 10, which has an n-type semiconductor region 2 and a p-type semiconductor region 4. An active layer 3 is arranged between the n-type semiconductor region 2 and the p-type semiconductor region 4.

(8) The semiconductor layer sequence 10 is preferably based on a phosphide compound semiconductor, i.e. one or more semiconductor layers contained in the semiconductor layer sequence 10 have in particular In.sub.xGa.sub.yAl.sub.1-x-yP, where 0x1, 0y1 and x+y1, preferably In.sub.0.5Al.sub.xGa.sub.0.5-xP, where 0x0.5. In particular, one or more layers of the n-type semiconductor region 2, the active layer 3, and the p-type semiconductor region 4 are formed from phosphide compound semiconductor materials. However, it cannot be ruled out that semiconductor layer sequence 10 may contain one or more layers of another III-V compound semiconductor material, such as one or more arsenide compound semiconductor layers or arsenide phosphide compound semiconductor layers.

(9) In the embodiment, the active layer 3 is formed as a quantum well structure, in particular a multiple quantum well structure. In the embodiment, the quantum well structure, for example, has a periodic arrangement of alternating quantum well layers 31 and barrier layers 32. The quantum well structure has a number of P periods, wherein P for example is between 1 and 120.

(10) The quantum well layers 31 intended for radiation generation have an electronic band gap E.sub.QW which is smaller than an electronic band gap E.sub.B of the barrier layers 32.

(11) The p-type semiconductor region 4 can contain one or more p-doped semiconductor layers. However, it cannot be ruled out that the p-type semiconductor region 4 contains one or more undoped layers. Accordingly, the n-type semiconductor region 2 may contain one or more n-doped layers and one or more undoped layers.

(12) In the optoelectronic semiconductor chip 100, the n-type semiconductor region 2 has a superlattice structure 20, which acts as a current spreading layer. In addition to the superlattice structure 20, the n-type semiconductor region 2 can include further semiconductor layers 25, 26. The superlattice structure 20 has a periodic sequence of semiconductor layers 21, 22, wherein the number of periods is N. With increasing number of periods the electrical conductivity can be increased, but on the other hand the absorption can increase due to the increasing total thickness. The number N of periods is advantageously between 5 and 70.

(13) Preferably, the number N of periods is between 30 and 50, which makes it possible to achieve good electrical conductivity with little or no absorption. Each period of the superlattice structure 20 comprises an undoped first semiconductor layer 21 and a doped second semiconductor layer 22. The doped semiconductor layers 22 each have an electronic band gap E.sub.2, which is larger than the electronic band gap E.sub.1 of the undoped first semiconductor layers 21. The undoped first semiconductor layers 21 form potential wells between the doped second semiconductor layers 22 in the superlattice structure. The band gap E.sub.1 of the undoped first semiconductor layers 21 that form the potential wells is larger than the band gap E.sub.QW of quantum well layers 31 in the multiple quantum well structure, which functions as active layer 3. In contrast to quantum well layers 31, the potential wells formed by the undoped first semiconductor layers 21 are not used to generate radiation.

(14) In order to achieve the larger electronic band gap E.sub.2, it is advantageous if the doped second semiconductor layers 22 have a higher aluminum content than the undoped first semiconductor layers 21. The undoped first semiconductor layers 21 in particular can have In.sub.0.5Al.sub.x1Ga.sub.0.5-x1P, where 0x10.27 or Al.sub.y1Ga.sub.1-y1As, where 0y10.4. The doped second semiconductor layers 22 in particular can have In.sub.0.5Al.sub.x1Ga.sub.0.5-x1P, where 0<x20.5 and x2>x1, or Al.sub.y2Ga.sub.1-y2As, where y2>y1.

(15) For example, the undoped first semiconductor layer 21 comprises In.sub.0.5Al.sub.0.1Ga.sub.0.4P and the doped second semiconductor layer 22 comprises In.sub.0.5Al.sub.0.28Ga.sub.0.22P. The doped second semiconductor layer 22 is preferably doped with Si or Te and has a dopant concentration of e.g. 1*10.sup.18 cm.sup.3. For example, the thickness of the undoped first semiconductor layer 21 is about 7 nm and the thickness of the doped second semiconductor layer 22 is about 30 nm.

(16) In the undoped first semiconductor layers 21, which are arranged in the superlattice structure 20 between the doped second semiconductor layers 22, a two-dimensional electron gas is advantageously formed, which increases the electrical conductivity advantageously. In particular, by means of the superlattice structure 20 it can be achieved that the specific resistance is not more than 0.05 cm. The optoelectronic semiconductor chip 100 is therefore characterized by a good current spreading, which leads to a particularly homogeneous radiation emission over the surface of the optoelectronic semiconductor chip 100. In particular, the superlattice structure 20 has the advantage that a good current spreading can already be achieved with a comparatively thin n-type semiconductor region 2. Due to the superlattice structure in the n-type semiconductor region 2, in particular the conductivity can be increased without increasing the total thickness of the n-type semiconductor region 2, or the total thickness can be reduced at a given conductivity compared to a homogeneous current spreading layer.

(17) The embodiment of the optoelectronic semiconductor chip 100 shown here is a so-called thin-film LED in which the semiconductor layer sequence 10 is detached from its original growth substrate. The original growth substrate is removed from the n-type semiconductor region 2, which in this embodiment is located on the radiation exit side of the optoelectronic semiconductor chip 100. On the side opposite the original growth substrate, the optoelectronic semiconductor chip 100 is applied to a carrier substrate 1 with at least one connection layer 7, for example a solder layer. Seen from the active layer 3, the p-type semiconductor region 4 faces the carrier substrate 1. The carrier substrate 1 is not the same as the growth substrate used for epitaxial growth of semiconductor layer sequence 10. The carrier substrate 1 can, for example, contain a semiconductor material such as silicon, germanium or molybdenum or a ceramic.

(18) The p-type semiconductor region 4 adjoins a mirror layer 6 in certain areas. Mirror layer 6 is provided to reflect the radiation emitted by the active zone 3 in the direction of the carrier substrate 1 to the opposite radiation exit surface on the surface of the n-type semiconductor region 2. The mirror layer 6 can contain or consist of silver or gold in particular. Silver and gold are characterized by a high reflectivity.

(19) In the exemplary embodiment shown here, a dielectric layer 5 is arranged between the p-type semiconductor region 4 and the mirror layer 6 in certain areas, which dielectric layer 5 can be a silicon oxide layer in particular. Due to the comparatively low refractive index of the dielectric material of dielectric layer 5, for example SiO.sub.2, dielectric layer 5 can cause a total reflection of part of the radiation emitted in the direction of the carrier substrate 1 towards the radiation exit surface. The reflective effect of metallic mirror layer 6 is therefore further enhanced by dielectric layer 5. Since the dielectric layer 5 is not electrically conductive, mirror layer 6 is connected to p-type semiconductor region 4 through one or more through-holes in dielectric layer 5.

(20) An n connection layer 8 and a p connection layer 9 are provided for electrical contacting of the optoelectronic semiconductor chip 100. The n-connection layer 8 for electrical contacting from the n-side can, for example, be arranged at the radiation exit side on the n-type semiconductor region 2. For example, the p connection layer 9 may be located on the rear side of carrier substrate 1 if an electrically conductive carrier substrate 1 is used.

(21) FIG. 2 shows schematically the electron density n.sub.e as a function of a vertical coordinate z in an embodiment of the superlattice structure. For simplification, a superlattice structure with only three periods is shown here, but wherein the superlattice structure can actually have between 5 and 70, preferably between 30 and 50 periods, for example. In the undoped first semiconductor layers 21, which are arranged between the doped second semiconductor layers 22, there is a comparatively high electron density. Due to the high electron density and high mobility of the electrons in the undoped first semiconductor layers 21, the electrical conductivity of the superlattice structure increases advantageously.

(22) FIG. 3 shows schematically the course of the conduction band edge E.sub.L, the Fermi energy E.sub.F and the valence band edge E.sub.V in an example of the superlattice structure. The conduction band edge of the undoped first semiconductor layers 21 is advantageously below the Fermi energy. The conduction band of the undoped first semiconductor layers 21 therefore contains free electrons which form a so-called two-dimensional electron gas. The free electrons in the undoped first semiconductor layers 21 have a high mobility, which increases the electrical conductivity of the superlattice structure.

(23) The second examplary embodiment of the optoelectronic semiconductor chip 100 shown in FIG. 4 differs from the optoelectronic semiconductor chip shown in FIG. 1 in that the undoped first semiconductor layers 21 are arranged in the superlattice structure 20 in each case between an undoped first intermediate layer 23 and an undoped second intermediate layer 24.

(24) In this embodiment, the periods of the superlattice structure 20 each have four layers, wherein in the periods the undoped first intermediate layer 23, the undoped first semiconductor layer 21, the undoped second intermediate layer 24 and the doped second semiconductor layer 22 follow one another. The undoped first intermediate layer 23 and the undoped second intermediate layer 24 each have substantially the same electronic band gap as the doped second semiconductor layer 22, in particular the undoped first intermediate layer 23 and the undoped second intermediate layer 24 may each have the same semiconductor material as the doped second semiconductor layer 22 apart from the doping.

(25) For example, the undoped first intermediate layer 23 comprises In.sub.0.5Al.sub.0.28Ga.sub.0.22P, the undoped first semiconductor layer 21 comprises In.sub.0.5Al.sub.0.1Ga.sub.0.4P, the undoped second intermediate layer 23 comprises In.sub.0.5Al.sub.0.28Ga.sub.0.22P and the doped second semiconductor layer 22 comprises In.sub.0.5Al.sub.0.28Ga.sub.0.22P. The doped second semiconductor layer 22 is preferably doped with Si or Te and has a dopant concentration of e.g. 1*10.sup.18 cm.sup.3.

(26) For example, the thickness of the undoped first intermediate layer 23 is about 6 nm, the thickness of the undoped first semiconductor layer 21 about 7 nm, the thickness of the undoped second intermediate layer 24 about 4 nm and the thickness of the doped second semiconductor layer 22 about 25 nm.

(27) The undoped first semiconductor layers 21 of the superlattice structure each form potential wells in which a high electron density is present. In particular, a two-dimensional electron gas can form in the undoped first semiconductor layers 21, as in the first embodiment, which causes an increase in conductivity. If the undoped first semiconductor layers 21 were directly connected to the doped second semiconductor layers 22 at the interface between the undoped first semiconductor layers 21 and the doped second semiconductor layers 22, more electrons would be scattered at phonons. The arrangement of the undoped first semiconductor layers 21 between the undoped intermediate layers 23, 24 has the advantage that the scattering of electrons is reduced.

(28) In other respects, the embodiment of FIG. 4 corresponds to the embodiment shown in FIG. 1 with regard to its mode of operation and other advantageous configurations.

(29) The invention is not limited by the description based on the embodiments. Rather, the invention includes each new feature and each combination of features, which includes in particular each combination of features in the claims, even if this feature or this combination itself is not explicitly indicated in the claims or embodiments.

LIST OF REFERENCE SIGNS

(30) 1 carrier 2 n-type semiconductor region 3 active layer 4 p-Type semiconductor region 5 dielectric layer 6 mirror layer 7 connection layer 8 n connection layer 9 p connection layer 10 semiconductor layer sequence 20 superlattice structure 21 undoped first semiconductor layer 22 doped second semiconductor layer 23 undoped first intermediate layer 24 undoped second intermediate layer 31 quantum well layer 32 barrier layer 100 optoelectronic semiconductor chip