APPARATUS AND METHOD OF FAST COMMUTATION FOR MATRIX CONVERTER-BASED RECTIFIER

Abstract

A method of commutation in a matrix rectifier from an active vector to a zero vector includes two steps. A method of commutation in a matrix rectifier from a zero vector to an active vector includes three steps.

Claims

1. A matrix rectifier comprising: first, second, and third phases; and uni-directional switches Sij, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where uni-directional switches S1j and S2j are connected together to define first, second, third, fourth, fifth, and sixth bi-directional switches; wherein first ends of the first, third, and fifth bidirectional switches are connected together to provide a positive-voltage node; first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negative-voltage node; second ends of the first and fourth bidirectional switches are connected to the first phase; second ends of the third and sixth bidirectional switches are connected to the second phase; second ends of the fifth and second bidirectional switches are connected to the third phase; a zero vector is defined by either uni-directional switches S1m and S1n switched on or unidirectional switches S2m and S2n switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other uni-directional switches Spq switched off, where pm and qn; an active vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other uni-directional switches Spq switched off, where pm and qn; Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6); commutation from an active vector to a zero vector includes: step (a): for an active vector with uni-directional switches S1m and S1n switched on, in Sectors I, III, V, turning on uni-directional switch S1x, where x is chosen such that (m, x)=(1, 4), (3, 6), (5, 2); and in Sectors II, IV, VI, turning on uni-directional switch S1x, where x is chosen such that (x, n)=(1, 4), (3, 6), (5, 2); or for an active vector with uni-directional switches S2m and S2n switched on, in Sectors I, III, V, turning on uni-directional switch S2y, where y is chosen such that (y, n)=(1, 4), (3, 6), (5, 2); and in Sectors II, IV, VI, turning on uni-directional switch S2y, where y is chosen such that (m, y)=(1, 4), (3, 6), (5, 2); and step (b): for the active vector with uni-directional switches S1m and S1n initially switched on, in Sectors I, III, V, turning off uni-directional switch S1n; and in Sectors II, IV, VI, turning off uni-directional switch S1m; or for the active vector with uni-directional switches S2m and S2n initially switched on, in Sectors I, III, V, turning off uni-directional switch S2m; in Sectors II, IV, VI, turning off uni-directional switch S2n; the commutation includes measuring output voltage and not measuring output current or input voltage.

2. A matrix rectifier comprising: first, second, and third phases; and uni-directional switches Sij, where i=1, 2 and j=1, 2, 3, 4, 5, 6 and where uni-directional switches S1j and S2j are connected together to define first, second, third, fourth, fifth, and sixth bi-directional switches; wherein first ends of the first, third, and fifth bidirectional switches are connected together to provide a positive-voltage node; first ends of the second, fourth, and sixth bidirectional switches are connected together to provide a negative-voltage node; second ends of the first and fourth bidirectional switches are connected to the first phase; second ends of the third and sixth bidirectional switches are connected to the second phase; second ends of the fifth and second bidirectional switches are connected to the third phase; a zero vector is defined by either uni-directional switches S1m and S1n switched on or unidirectional switches S2m and S2n switched on, where (m, n)=(1, 4), (3, 6), (5, 2), and by all other uni-directional switches Spq switched off, where pm and qn; an active vector is defined by either uni-directional switches S1m and S1n switched on or uni-directional switches S2m and S2n switched on, where m=1, 3, 5; n=2, 4, 6; and m, n are not connected to the same phase, and by all other uni-directional switches Spq switched off, where pm and qn; and Sectors I, II, III, IV, V, and VI are defined by using active vectors with (a, b)=(1, 6), (1, 2), (3, 2), (3, 4), (5, 4), and (5, 6); commutation from a zero vector to an active vector includes: step (a): for a zero vector with uni-directional switches S1m and S1n switched on, in Sectors I, III, V, turning on uni-directional switch S1x, where x=1, 3, 5 and x is chosen such that a negative voltage is provided at the positive-voltage node; and in Sectors II, IV, VI, turning on uni-directional switch S1x, where x=2, 4, 6 and x is chosen such that a positive voltage is provided at the negative-voltage node; or for a zero vector with uni-directional switches S2m and S2n switched on, in Sectors I, III, V, turning on uni-directional switch S2y, where y=2, 4, 6 and y is chosen such that a positive voltage is provided at the negative-voltage node; and in Sectors II, IV, VI, turning on uni-directional switch S2y, where y=1, 3, 5 and y is chosen such that a negative voltage is provided at the positive-voltage node; step (b): for the zero vector with uni-directional switches S1m and S1n initially switched on, in Sectors I, III, V, turning off uni-directional switch S1m; and in Sectors II, IV, VI, turning off uni-directional switch S1n; or for the zero vector with uni-directional switches S2m and S2n initially switched on, in Sectors I, III, V, turning off uni-directional switch S2n; and in Sectors II, IV, VI, turning off uni-directional switch S2m; and step (c): for the zero vector with uni-directional switches S1m and S1n initially switched on, in Sectors I, III, V, turning off uni-directional switches S1x and S1n and turning on uni-directional switches S2x and S2n; and in Sectors II, IV, VI, turning off uni-directional switches S1x and S1m and turning on uni-directional switches S2x and S2m; or for the zero vector with uni-directional switches S2m and S2n initially switched on, in Sectors I, III, V, turning off uni-directional switches S2m and S2y and turning on uni-directional switches S1m and S1y; and in Sectors II, IV, VI, turning off uni-directional switches S2n and S2y and turning on uni-directional switches S1n and S1y; the commutation includes measuring output voltage and not measuring output current or input voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0098] FIGS. 1A and 1B are circuit diagrams of matrix-converters.

[0099] FIG. 2 is a circuit diagram of a two-phase-to-single-phase matrix converter.

[0100] FIGS. 3A and 3B show the steps of current-based commutation.

[0101] FIGS. 4A and 4B show the steps of voltage-based commutation.

[0102] FIG. 5 shows the waveforms of the rectifier of a matrix converter.

[0103] FIG. 6 shows eight switching modes in one sampling period in sector I.

[0104] FIGS. 7A and 7B show 2-step commutation from an active vector to a zero vector for a positive current in sector I.

[0105] FIGS. 8A and 8B show 3-step commutation from a zero vector to an active vector.

[0106] FIG. 9 is a block diagram of gate-signal generator.

[0107] FIG. 10 shows SVM-modulation and commutation signals in one sampling period.

[0108] FIG. 11 shows gate signals in one sampling period in sector I.

[0109] FIG. 12 shows 2-step commutation at time t.sub.2.

[0110] FIG. 13 shows 3-step commutation at time t.sub.3.

[0111] FIG. 14 shows a current-space vector hexagon.

[0112] FIG. 15 shows 2-step commutation from an active vector to a zero vector for a negative current in sector I.

[0113] FIG. 16 shows 3-step commutation from a zero vector to an active vector for a negative current in sector I.

[0114] FIG. 17 shows 2-step commutation from an active vector to a zero vector for a positive current in sector II.

[0115] FIG. 18 shows 3-step commutation from a zero vector to an active vector for a postive current in sector II.

[0116] FIG. 19 shows 2-step commutation from an active vector to a zero vector for a negative current in sector II.

[0117] FIG. 20 shows 3-step commutation from a zero vector to an active vector for a negative current in sector II.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0118] Preferred embodiments of the present invention improve the known four-step commutation methods. Current commutation can ensure reliable operation. Because the rectifiers of 3-phase-to-1-phase matrix-converters have a different structure compared to the rectifiers of known 3-phase-to-3-phase matrix converters, rectifiers of a 3-phase-to-1-phase matrix-converter can use a different current-based commutation method, as discussed below.

[0119] As shown in FIG. 5, the matrix-converter output current i.sub.p(t) is positive in adjacent P- and Z-intervals, except for the commutation area, and the matrix-converter output current i.sub.p(t) is negative in adjacent N- and Z-intervals, except for the commutation area. During adjacent P- and Z-intervals, converter #1 works normally and converter #2 stops working, and in contrast, during adjacent N- and Z-intervals, converter #2 works normally and converter #1 stops working. Thus, there are eight switching modes in one sampling period exclusive of the commutation areas as shown in FIG. 6. In one sampling period, there are two types of current-based commutations: (1) active vector (i.e., either P-vector or N-vector) to zero vector and (2) zero vector to active vector. A two-step active-vector-to-zero-vector commutation and a three-step zero-vector-to-active-vector commutation are discussed below.

(1) Active Vector to Zero Vector (P-Vector to Z-Vector or N-Vector to Z-Vector)

[0120] As seen in FIGS. 5 and 6, active-vector-to-zero-vector commutations include the commutations from mode 1 (P-vector) to mode 2 (Z-vector), mode 3 (N-vector) to mode 4 (Z-vector), mode 5 (P-vector) to mode 6 (Z-vector), and mode 7 (N-vector) to mode 8 (Z-vector). During active-vector-to-zero-vector commutation, the direction of the output current of the rectifier of the matrix converter does not change. Thus, active-vector-to-zero-vector commutation only adds an overlap time just as the commutation method of the current-source inverter. The overlap time is added to make sure that the current can smoothly transition from one switch to another switch and that no overvoltage is induced during this transition. The overlap time is determined by the turn on and turn off speed of these two switches. For example, as shown in FIGS. 7A and 7B, the commutation from mode 1 to mode 2 only has two steps: [0121] (24) switch S.sub.14 turns on, and [0122] (25) switch S.sub.16 turns off.
Thus, commutation from an active vector to a zero vector is achieved. FIGS. 7A and 7B show an example of the 2-step commutation from an active vector to a zero vector for a positive current in sector I. Similar commutation steps are performed in sectors III and V.

[0123] FIG. 15 shows a 2-step commutation from an active vector to a zero vector for a negative current in sector I. The commutation steps include: [0124] (26) switch S.sub.21 turns on, and [0125] (27) switch S.sub.23 turns off.
Similar commutation steps are performed in sectors III and V.

[0126] FIG. 17 shows a 2-step commutation from an active vector to a zero vector for a positive current in sector II. The commutation steps include: [0127] (28) switch S.sub.15 turns on, and [0128] (29) switch S.sub.11 turns off.
Similar commutation steps are performed in sectors IV and VI.

[0129] FIG. 19 shows a 2-step commutation from an active vector to a zero vector for a negative current in sector II. The commutation steps include: [0130] (30) switch S.sub.22 turns on, and [0131] (31) switch S.sub.24 turns off.
Similar commutation steps are performed in sectors IV and VI.

(2) Zero Vector to Active Vector (Z-Vector to P-Vector or Z-Vector to N-Vector)

[0132] As seen in FIGS. 5 and 6, zero-vector-to-active-vector commutations include the commutations from mode 2 (Z-vector) to mode 3 (N-vector), mode 4 (Z-vector) to mode 5 (P-vector), mode 6 (Z-vector) to mode 7 (N-vector), and mode 8 (Z-vector) to mode 1 of the next sampling period (P-vector). During zero-vector-to-active-vector commutation, the direction of the output current of the rectifier of the matrix converter changes. Thus, zero-vector-to-active-vector commutation requires an additional step. For example, as shown in FIGS. 8A and 8B, the commutation from mode 2 to mode 3 in sector I includes three steps: [0133] (32) switch S.sub.15 turns on. The purpose of this step is to provide a current path for the next step. Although switch S.sub.15 is on in this step, there is no current passing through switch S.sub.15 because the voltage u.sub.a is larger than the voltage u.sub.c and because the diode in series with the switch S.sub.15 is reversed biased. The output vector is still the Z-vector. The time span t.sub.1 that this step maintains can be decided according to the overlap time of the current-source inverter. The overlap time is added to make sure that the switch S.sub.15 is on before switch S.sub.11 turns off, considering the delay between the gate signals of the switches S.sub.11 and S.sub.15. [0134] (33) Switch S.sub.11 turns off. After turning switch S.sub.11 off, the output vector is substantially the N-vector, so the output current will be reduced sharply and reach zero quickly. This step should last long enough to ensure that the current reaches zero. The holding time t.sub.2 of this step can be estimated by the maximum current I.sub.1max of the matrix converter, the minimum output voltage U.sub.1min of the matrix converter, and the leakage inductance L.sub.o of the transformer:

[00005]$\begin{array}{cc}{.Math.t}_2=\frac{L_o.Math.I_{1.Math.\max }}{U_{1.Math.\mathrm{mi}.Math.n}}& \left(1\right)\end{array}$ For simplicity, the holding time t.sub.2 can be selected as a fixed value according to eq. (1). The holding time t.sub.2 is determined by the transition time required for the output current to reach zero. The holding time t.sub.2 based on eq. (1) is long enough to ensure that the current reaches zero under all the conditions. [0135] (34) Switches S.sub.15 and S.sub.14 turn off and switches S.sub.24 and S.sub.24 turn on.
Thus, commutation from a zero vector to an active vector is achieved. FIGS. 8A and 8B show an example of the 3-step commutation from a zero vector to an active vector for a positive current in sector I. Similar commutation steps are performed in sectors III and V.

[0136] FIG. 16 shows a 3-step commutation from a zero vector to an active vector for a negative current in sector I. The commutation steps include: [0137] (35) switch S.sub.22 turns on, [0138] (36) switch S.sub.24 turns off, and [0139] (37) switches S.sub.21 and S.sub.22 turn off and switches S.sub.11 and S.sub.12 turn on.
Similar commutation steps are performed in sectors III and V.

[0140] FIG. 18 shows a 3-step commutation from a zero vector to an active vector for a positive current in sector II. The commutation steps include: [0141] (38) switch S.sub.16 turns on, [0142] (39) switch S.sub.12 turns off, and [0143] (40) switches S.sub.15 and S.sub.16 turn off and switches S.sub.25 and S.sub.26 turn on.
Similar commutation steps are performed in sectors IV and VI.

[0144] FIG. 20 shows a 3-step commutation from a zero vector to an active vector for a negative current in sector II. The commutation steps include: [0145] (41) switch S.sub.23 turns on, [0146] (42) switch S.sub.25 turns off, and [0147] (43) switches S.sub.23 and S.sub.22 turn off and switches S.sub.13 and S.sub.12 turn on.
Similar commutation steps are performed in sectors IV and VI.

[0148] As shown in FIG. 10, the time periods (or effective area in FIG. 10) when only converter #1 is on and the time periods when only converter #2 is on are separate from each other. In FIG. 10, the signal SelectCon1 is 1 when converter #1 is on, i.e., the effective area for converter #1, and is 0 when converter #1 is off, i.e., the effective area for converter #2. Similarly, the signal SelectCon2 when converter #2 is on, i.e., the effective area for converter #2, and is 0 when converter #2 is off, i.e., the effective area for converter #1. As shown in FIG. 9, the following three steps can be used to achieve modulation and commutation.

(1) Generate the Signals S.SUB.i .(i=1, 2, 3, 4, 5, 6)

[0149] Accordingly, a carrier signal and three compare value signals CMP0, CMP1, CMP2 are used to generate the SVM PWM signals S.sub.i (i=1, 2, 3, 4, 5, 6). The compare values signals CMP0, CMP1, CMP2 are determined by the dwell time of each vector. After the holding time t.sub.1 for the falling edge of signals S.sub.i has lapsed, the signals S.sub.i (i=1, 2, 3, 4, 5, 6) can be generated. The falling edge of signal S.sub.i is delayed for holding time t.sub.1 compared with the signal S.sub.i. An overlap time is added to the signals S.sub.1, S.sub.3, S.sub.5, and S.sub.4, S.sub.6, S.sub.2 just as in the commutation method of the current-source inverter. In sector I, for example, the signals S.sub.1, S.sub.3, S.sub.5 and S.sub.4, S.sub.6, S.sub.2 are shown in FIG. 10.

(2) Generate Signal SelectCon1 and Signal SelectCon2

[0150] After comparison between the carrier signal and CMP1 and the delay t of both rising and falling edges, signal SelectCon1 can be generated, as shown in FIGS. 9 and 10. The fixed delay time t is based on the three steps of zero-vector-to-active-vector commutation. So the delay time t can be determined by eq. (2).

t=t.sub.1+t.sub.2(2)

where t.sub.t is the overlap time and t.sub.2 is estimated by eq. (1).

(3) Generate Gate Signals S.SUB.i1 .for Converter #1 and Gate Signals S.SUB.i2 .for Converter #2

[0151] The gate signals S.sub.1j for converter #1 can be generated by eq. (3), and the gate signals S.sub.2j for converter #2 can be generated by eq. (4):

S.sub.1j=S.sub.1SelectCon1(j=1,3,5,4,6,2)(3)

S.sub.2j=S.sub.jSelectCon2(j=1,3,5,4,6,2)(4)

[0152] For example, in sector I, the gate signals S.sub.11, S.sub.13, S.sub.15, S.sub.14, S.sub.16, and S.sub.12 are generated for converter #1, and the gate signals S.sub.21, S.sub.23, S.sub.22, S.sub.24, S.sub.26, and S.sub.22 are generated for converter #1 as shown in FIG. 10.

[0153] FIGS. 11-13 show the gate signals generated using a field programmable gate array (FPGA) to implement the method described above. FIG. 11 shows the gate signals for switches S.sub.1 to S.sub.6 in sector I. The time period from time t.sub.1 to time t.sub.9 is one sampling period T.sub.s. Times t.sub.2, t.sub.4, t.sub.6, and t.sub.8 use 2-step commutation, and times t.sub.1, t.sub.2, t.sub.3, t.sub.7, and t.sub.9 use 3-step commutation.

[0154] For example, at time t.sub.2, the commutation from mode 1 to mode 2 (from active vector to zero vector) as shown in FIG. 7 is in two steps. The 2-step commutation waveforms are shown in FIG. 12. At time t.sub.3, the commutation from mode 2 to mode 3 (from zero vector to active vector) as shown in FIG. 8 is in three steps. The 3-step commutation waveforms are shown in FIG. 13.

[0155] It should be understood that the foregoing description is only illustrative of the present invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the present invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variances that fall within the scope of the appended claims.