Optoelectronic Semiconductor Chip

Abstract

An optoelectronic semiconductor chip is disclosed. In an embodiment a chip includes an active zone with a multi-quantum-well structure, wherein the multi-quantum-well structure includes multiple quantum-well layers and multiple barrier layers, which are arranged sequentially in an alternating manner along a growth direction and which each extend continuously over the entire multi-quantum-well structure, wherein seen in a cross-section parallel to the growth direction, the multi-quantum-well structure has at least one emission region and multiple transport regions, wherein the quantum-well layers and the barrier layers are thinner in the transport regions than in the emission region, wherein, along the growth direction, the transport regions have a constant width, and wherein the quantum-well layers and the barrier layers are oriented parallel to one another in the emission region and in the transport regions.

Claims

1. An optoelectronic semiconductor chip comprising: an active zone with a multi-quantum-well structure, wherein the multi-quantum-well structure comprises multiple quantum-well layers and multiple barrier layers, which are arranged sequentially in an alternating manner along a growth direction and which each extend continuously over the entire multi-quantum-well structure, wherein, seen in a cross-section parallel to the growth direction, the multi-quantum-well structure has at least one emission region and multiple transport regions, which are arranged sequentially in an alternating manner in a direction perpendicular to the growth direction, wherein the quantum-well layers and the barrier layers are thinner in the transport regions than in the emission region, wherein, along the growth direction, the transport regions have a constant width, and wherein the quantum-well layers and the barrier layers are oriented parallel to one another in the emission region and in the transport regions.

2. The optoelectronic semiconductor chip according to claim 1, wherein the quantum-well layers run obliquely to the growth direction in the transport regions and perpendicular to the growth direction in the emission region, seen in a cross-section parallel to the growth direction.

3. The optoelectronic semiconductor chip according to claim 2, wherein the quantum-well layers and the barrier layers in the transport regions are triangular in shape, seen in a cross-section parallel to the growth direction.

4. The optoelectronic semiconductor chip according to claim 1, wherein the quantum-well layers are arranged equidistant to one another within the transport regions.

5. The optoelectronic semiconductor chip according to claim 1, wherein the quantum-well layers are shaped as elevations in the transport regions, relative to the emission region, such that parts of the quantum-well layer that are located in the transport regions project beyond parts of the corresponding quantum-well layer in the emission region along the growth direction.

6. The optoelectronic semiconductor chip according to claim 1, wherein the quantum-well layers are shaped as depressions in the transport regions, relative to the emission region, such that parts of the quantum-well layer that are located in these transport regions are set back relative to parts of the corresponding quantum-well layer in the emission regions along the growth direction.

7. The optoelectronic semiconductor chip according to claim 1, wherein the transport regions run completely through the active zone along the growth direction.

8. The optoelectronic semiconductor chip according to claim 1, wherein, seen in a top view, a proportion of surface area occupied by the emission region is between 70% and 98% inclusive, wherein the emission region, seen in a top view, appear brighter than the transport regions by at least a factor of 3 during operation, wherein thicknesses of the quantum-well layers and the barrier layers differ from one another by at least a factor of 1.5 and by no more than a factor of 10 between the transport regions and the emission region, and wherein an average width of the transport regions is between 250 nm and 5 m transverse to the growth direction.

9. The optoelectronic semiconductor chip according to claim 1, wherein the barrier layers comprise GaN, InGaN or AlGaN and the quantum-well layers consists essentially of InGaN, wherein a number of quantum-well layers is between 4 and 25 inclusive, wherein, seen in top view, the transport regions and the emission region are arranged in a regular manner, wherein an average thickness of the quantum-well layers in the emission region is between 1.2 nm and 15 nm inclusive, wherein an average indium content of the quantum-well layers in the transport regions is no more than 50% of an average indium content of the quantum-well layers in the emission region, and wherein, in the transport regions and in the emission region, the same number of quantum-well layers and barrier layers is present.

10. An optoelectronic semiconductor chip comprising: an active zone with a multi-quantum-well structure, wherein the multi-quantum-well structure comprises multiple quantum-well layers and multiple barrier layers, which are arranged sequentially in an alternating manner along a growth direction and which each extend continuously over the entire multi-quantum-well structure, wherein, seen in a cross-section parallel to the growth direction, the multi-quantum-well structure has at least one emission region and multiple transport regions, which are arranged sequentially in an alternating manner in a direction perpendicular to the growth direction, wherein at least one of the quantum-well layers and the barrier layers are thinner in the transport regions than in the emission region, and wherein the quantum-well layers and the barrier layers are arch-shaped in the transport regions and run perpendicular to the growth direction in the emission region, seen in cross-section.

11. The optoelectronic semiconductor chip according to claim 10, wherein the quantum-well layers and the barrier layers are arch-shaped only in the transport regions and run only perpendicular to the growth direction in the emission region, seen in cross-section.

12. The optoelectronic semiconductor chip according to claim 10, wherein, in the transport regions, a distance between adjacent quantum-well layers decreases monotonically or strictly monotonically towards a central axis of the transport regions, and wherein the central axis is an axis of symmetry of the transport regions and is oriented parallel to the growth direction.

13. The optoelectronic semiconductor chip according to claim 12, wherein a smallest distance between adjacent quantum-well layers is at the central axis.

14. The optoelectronic semiconductor chip according to claim 10, wherein the transport regions have a varying width along the growth direction.

15. The optoelectronic semiconductor chip according to claim 10, further comprising a substrate, wherein the substrate is a growth substrate for the active zone, wherein the substrate has a patterned substrate surface, and wherein the subdivision into the transport regions and the emission region is defined by the patterned substrate surface.

16. The optoelectronic semiconductor chip according to claim 10, wherein a gradient is present in at least one of a material composition and a layer thickness of the quantum-well layers and of the barrier layers, wherein the gradient extends over more than one of the quantum-well layers and of the barrier layers and is present in a direction parallel to the growth direction such that the quantum-well layers differ in terms of their emission wavelength along the growth direction and such that quantum-well layers located closer to an n-side of an semiconductor layer sequence are configured to emit shorter-wave radiation.

17. The optoelectronic semiconductor chip according to claim 10, wherein in a transition region between adjacent transport regions and the emission region, a doping layer is present which comprises a p-type dopant having a concentration of at least 10.sup.18 per cm.sup.3.

18. The optoelectronic semiconductor chip according to claim 17, wherein the doping layer completely fills the transport regions such that the transport regions and emission region are flush with one another as a result of the doping layer, and wherein the doping layer completely covers facets of the emission region not covered by the transport regions.

19. An optoelectronic semiconductor chip comprising: an active zone with a multi-quantum-well structure, wherein the multi-quantum-well structure comprises multiple quantum-well layers and multiple barrier layers, which are arranged sequentially in an alternating manner along a growth direction and which each extend continuously over the entire multi-quantum-well structure, wherein, seen in a cross-section parallel to the growth direction, the multi-quantum-well structure has at least one emission region and multiple transport regions, which are arranged sequentially in an alternating manner in a direction perpendicular to the growth direction, wherein the quantum-well layers and the barrier layers are thinner in the transport regions than in the emission region, wherein the quantum-well layers and the barrier layers run perpendicular to the growth direction in the emission region, seen in cross-section, and wherein, the quantum-well layers and the barrier layers are semi-circular or triangular with rounded corners in the transport regions, seen in cross-section.

20. The optoelectronic semiconductor chip according to claim 19, wherein triangular-shaped quantum-well layers with rounded corners are combined with arch-shaped quantum-well layers in the transport regions, seen in cross-section.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0047] An optoelectronic semiconductor chip as described here is explained in more detail below with reference to the drawing with the aid of exemplary embodiments. The same reference signs relate to the same elements in the individual figures here. However, relationships are not shown to scale; rather, to aid understanding, the size of individual elements may be exaggerated.

[0048] The figures show the following:

[0049] FIGS. 1, 12 and 13 show cross-sectional diagrams of exemplary embodiments of optoelectronic semiconductor chips,

[0050] FIGS. 2 to 11 and 17 to 19 show cross-sectional diagrams of exemplary embodiments of multi-quantum-well structures for optoelectronic semiconductor chips,

[0051] FIGS. 14A-14D show a top-view diagram of an exemplary embodiment of a multi-quantum-well structure for optoelectronic semiconductor chips,

[0052] FIG. 15 shows a schematic curve of current versus luminous flux and external quantum efficiency of semiconductor chips, and

[0053] FIG. 16 shows a cross-sectional diagram of a conventional multi-quantum-well structure.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0054] In FIG. 1, an exemplary embodiment of an optoelectronic semiconductor chip 1 is shown. The semiconductor chip 1 comprises a substrate 6, on the substrate surface 60 of which a semiconductor layer sequence is grown. The semiconductor layer sequence is preferably based on AlInGaN.

[0055] The semiconductor layer sequence comprises an n-doped side 2 and a p-doped side 5. Between these doped sides 2, 5 there is a multi-quantum-well structure 3, which represents an active zone of the semiconductor chip 1. Contact metallizations 8 for an electrical contacting of the semiconductor chip 1 are located on both the n-doped side 2 and the p-doped side 5. To simplify the illustration, optional current distribution structures are not shown. A growth direction G of the semiconductor layer sequence points away from the substrate 6 in a direction towards the p-doped side 5.

[0056] The multi-quantum-well structure 6 comprises alternating quantum-well layers 31 and barrier layers 32. The quantum-well layers 31 and the barrier layers 32 extend continuously over the entire active zone without any interruptions or gaps being formed intentionally. However, the quantum-well layers 31 and/or the barrier layers 32 are modulated in terms of their thickness.

[0057] Thus, regions with a greater thickness of the quantum-well layers 31 and/or barrier layers 32 are present. These regions form emission regions 41 in which light generation primarily takes place. Furthermore, transport regions 42 are present in which the quantum-well layers 31 and/or the barrier layers 32 are thinner in form. Transport primarily takes place in the transport regions 42, of holes in particular, in a direction parallel to the growth direction G and in quantum-well layers 31 which are close to the n-doped side 2.

[0058] From the transport regions 42, charge carriers are further distributed into the emission regions 41 in a direction perpendicular to the growth direction G. In other words, the energy levels of the quantum-well layers 31 in the emission regions 41 and the transport regions 42 are adjusted such that charge carrier recombination takes place primarily in the emission regions 41. As a result, seen in a top view, the emission regions 41 appear brighter than the transport regions 42.

[0059] According to FIG. 1, the quantum-well layer 31 closest to the substrate 6 is identical in form, i.e., is present in unvarying thickness and material composition, over the emission regions 41 and the transport regions 42. As a result of the thinner barrier layers 32 and/or quantum-well layers 31 in the transport regions 42, the individual layers in the transport regions 42 have a trapezium-like, symmetrical shape, seen in cross-section. A patterning into the transport regions 42 and the emission regions 41 takes place, e.g., as a result of the presence of different growth rates on different crystal planes and/or of the local modification of a growth temperature, for instance by irradiation with laser light. Lithographic or self-assembling masking techniques can also be used.

[0060] Light outcoupling structures 7 are optionally formed on a side of the semiconductor layer sequence. It is possible that the light outcoupling structures 7 are spatially correlated with the transport regions 42. The same is also possible in all the other exemplary embodiments.

[0061] In the exemplary embodiment as seen in FIG. 2, the quantum-well layers 31 are formed symmetrically about an axis of symmetry S, the axis of symmetry S being aligned perpendicularly to the growth direction G. The transport of charge carriers is symbolized by arrows, with h.sup.+ denoting holes and e.sup. denoting electrons.

[0062] Optionally, as in all the other exemplary embodiments, it is possible that the transport regions 42 each have a central axis M. The central axis M is oriented parallel to the growth direction G. Seen in cross-section, the transport regions 42 are preferably constructed symmetrically about the central axis M.

[0063] In the exemplary embodiment of FIG. 3, in the transport regions 42 the barrier layers 32 and the quantum-well layers 31 are each triangular in shape. According to FIG. 4, the quantum-well layers 31 and the barrier layers 32 have an arched shape, seen in cross-section.

[0064] In a direction towards the middle of the transport regions 42, according to FIGS. 3 and 4, the distance between adjacent quantum-well layers 31 decreases. The smallest distance between adjacent quantum-well layers 31 is in the region of the central axis M.

[0065] According to FIG. 5, the quantum-well layers 31 and the barrier layers 32 in the transport regions 42 are likewise triangular in shape, seen in cross-section. The quantum-well layers 31 here are arranged equidistant to one another within the region 42, and therefore the distance between adjacent quantum-well layers 31 remains constant or approximately constant over the entire width of the transport regions 42. The same can also apply to arched or trapezium-shaped embodiments, see, e.g., in particular FIGS. 1 and 4.

[0066] As can be seen in FIG. 6, the quantum-well layers 31 can be in the form of elevations in the transport regions 42, relative to the quantum-well layers 31 in the emission regions 41 and with reference to the growth direction G. Otherwise, the transport regions 42 of FIG. 6 are formed in exactly the same way as the transport regions 42 in FIG. 5.

[0067] The quantum-well layers 31 according to FIGS. 1, 3 and 4 can also, unlike the illustrations in these figures, be configured as elevations similar to those in FIG. 6.

[0068] In FIGS. 2 to 6, the modified layers 31, 32 in the transport regions 42 each extend through the multi-quantum-well structure 3 completely along the growth direction G. In the exemplary embodiment as illustrated in FIG. 7, only some of the quantum-well layers 31 are thinner in the transport regions 42, and therefore trapezium-shaped. More than one of the quantum-well layers 31 extend in unmodified and constant thickness both over the emission regions 41 and over the sections with the thinner quantum-well layers 31. Along the growth direction G, the actual transport region 42 extends approximately 40% of the way through the multi-quantum-well structure 3. The same can apply to quantum-well layers 31 that are shaped similarly to those in FIGS. 3 to 6.

[0069] As illustrated in FIG. 7 with the aid of the reference signs, transport regions 42 are understood to be those sections of the multi-quantum-well structure 3 comprising quantum-well layers 31 and/or barrier layers 32 that have been at least partly modified in a direction parallel to the growth direction G, since in these sections improved charge carrier conductivity is achieved in a direction parallel to the growth direction G.

[0070] In the exemplary embodiment as illustrated in FIG. 8, the quantum-well layers 31 have a variable thickness in the transport regions 42. Against the growth direction G, the width of the quantum-well layers 31 decreases in the transport regions 42. Differing from the illustration, it is also possible here that the transport regions 42 pass through the quantum well structure 3 completely in a direction along the growth direction G.

[0071] In the exemplary embodiment as illustrated in FIG. 9, the width of the quantum-well layers 31 increases in the transport regions 42 in a direction towards the middle of the quantum well structure 3. Deviating from the illustration in FIG. 9, it is possible that the widest of the quantum-well layers 31 in the transport regions 42 is located not in the middle of the quantum well structure 3 along the growth direction G but, e.g., in a lower quarter or a lower third, seen along the growth direction G. In other words, the transport regions 42 pass, e.g., or or of the way through the quantum well structure 3 in this case and the quantum-well layer 31 of the transport regions 42 lying furthest away within the quantum well structure 3 then has the greatest thickness, starting from a side of the multi-quantum-well structure 3. As in all the other exemplary embodiments, the transport regions 42 preferably start on a side of the multi-quantum-well structure 3 facing towards the p-doped side of the semiconductor layer sequence, but can also start on an n-doped side.

[0072] It is shown in FIG. 10 that the quantum-well layers 31 in the transport regions 42 are triangular in shape, seen in cross-section. Along the growth direction G here, the width of the quantum-well layers 31 increases in the transport regions 42, e.g., in a linear fashion.

[0073] The number of quantum-well layers 31 is, e.g., at least 5 or 7 and/or no more than 9 or 15. The thicknesses of the quantum-well layers 31 are preferably between 2 nm and 4 nm inclusive, in particular approx. 3 nm, in the emission regions 41 and between 0.25 nm and 3 nm inclusive, in particular approx. 1 nm, in the transport regions 42. The quantum-well layers 31 preferably consist of InGaN with an indium content of between 6% and 25% inclusive, in particular approx. 12%, in the emission regions 41 and with an indium content of between 2% and 15% inclusive, in particular approx. 3%, in the transport regions 42. The thicknesses of the barrier layers 32 are preferably between 3 nm and 15 nm inclusive, in particular approx. 9 nm, in the emission regions 41 and between 0.5 nm and 8 nm inclusive, in particular approx. 3 nm, in the transport regions 42. The transport regions 42 can have an average diameter of between 50 nm and 800 nm inclusive or 80 nm to 400 nm, in particular approx. 200 nm. The transport regions 42 preferably occupy a proportion of the surface area of between 2% and 20% inclusive, in particular approx. 6%, seen in a top view. These values preferably also apply to all the other exemplary embodiments.

[0074] It is illustrated in FIG. 11 that multiple different types of transport regions 42 can be combined with one another within a quantum well structure 3. It is also possible here that a relatively small proportion of the transport regions 42 start on an n-doped side. Deviating from the illustration according to FIG. 11, different structures can also be combined with one another, e.g., triangular-shaped quantum-well layers 31, seen in cross-section, from FIGS. 5, 6 or 10 with trapezium-shaped quantum-well layers 31, for instance from FIGS. 7 to 9, with arch-shaped quantum-well layers 31, for instance from FIG. 4.

[0075] In the semiconductor chip 1 as shown in FIG. 12, the substrate 6 has a patterned substrate surface 60. The emission regions 41 and the transport regions 42 are defined by the patterning of the substrate surface 60. The quantum-well layers 31 have the same contour as the substrate surface 60, seen in cross-section. The emission regions 41 here are defined by regions of the substrate surface 60 that run perpendicular to the growth direction G and are shaped like a plateau. A corresponding shaping of the quantum-well layers 31 in the transport regions 42 can also take place in all the other exemplary embodiments.

[0076] In FIG. 13, a further exemplary embodiment of the semiconductor chip 1 is illustrated. An electrical contacting here is formed as specified in the document US 2010/0171135 A1, the disclosure content of which is incorporated by reference. Thus, contacting also takes place by means of contact regions, which run from the p-side 5 through the multi-quantum-well structure 3 into the n-side 2. These vias through the multi-quantum-well structure 3 preferably have a significantly greater width than the transport regions 42, e.g., a width which is greater by at least a factor of 5 or 10 or 20.

[0077] Furthermore, FIG. 13 shows a diagram of crystal defects 10 in the form of so-called V-pits. These V-pits are described, e.g., in the document Cho et al. in the Journal of the Korean Physical Society, vol. 42, February 2003, pages S547 to S550. As a result of these V-pits 10, it is possible that the quantum-well layers 31 in the multi-quantum-well structure 3 are locally dislocated. However, these V-pits 10 are preferably not present in spatial correlation with the transport regions 42 but are randomly distributed. Furthermore, spatial dimensions of the V-pits 10 are preferably smaller than the dimensions of the transport regions 42 by a factor of at least 2 or 5 in a direction perpendicular to the growth direction G, but are greater along parallel to the growth direction G. The V-pits 10 can also widen in a direction towards the p-side 5, contrarily to the quantum-well layers 31 in the transport regions 42. Deviating from the illustration in FIG. 13, however, it is also possible that the V-pits 10 and the transport regions 42 both widen in a direction towards the p-side, seen in cross-section.

[0078] In the top view according to FIG. 14A, it is shown that the transport regions 42 are insular and can be arranged in a hexagonal lattice. According to FIG. 14B, the transport regions 42 are arranged regularly in a rectangular lattice.

[0079] The arrangement of the transport regions 42 in FIGS. 14C and 14D likewise takes place in a regular pattern. As can be seen in FIG. 14C, however, the individual transport regions 42 can be shifted slightly relative to a pure rectangular lattice, e.g., on average by no more than 30% or 20% of a lattice constant. In FIG. 14D, it is shown that the transport regions 42 are arranged around lattice points of a regular lattice, which is in particular a rectangular lattice. In this case, for example, between 1 and 5 inclusive of the transport regions 42 closely surround a lattice point, e.g., in a radius of no more than 20% or 10% of the lattice constant.

[0080] A corresponding arrangement of the transport regions 42, seen in a top view, can likewise be present in all the other exemplary embodiments.

[0081] In FIG. 16, a conventional multi-quantum-well structure 3 is shown. In this case, the thickness of the quantum-well layers 31 and barrier layers 32 is not modulated, so that charge carriers h.sup.+, e.sup. are pushed uniformly into the multi-quantum-well structure 3 over the entire surface.

[0082] Compared with a conventional multi-quantum-well structure 3 of this type, the multi-quantum-well structures 3 of FIGS. 1 to 14 are improved in terms of a luminous flux and an external quantum efficiency Y, see, e.g., FIG. 15. FIG. 15 shows a dependence of the luminous flux on an operating current I and a dependence of the external quantum efficiency Y, plotted against the logarithm of the operating current I.

[0083] In the exemplary embodiment of FIG. 17, adjacent emission regions 41, seen in cross-section, are arranged offset to one another along the growth direction G. Between adjacent emission regions 41 there is a transport region 42 in each case, which runs obliquely to the growth direction G.

[0084] In FIGS. 18 to 19, transmission electron microscope images of exemplary embodiments of semiconductor chips 1 are shown. The quantum-well layers 31 here appear brighter than the barrier layers 32.

[0085] According to FIG. 18, the quantum-well layers 31 in the emission region 41 are significantly thicker in form than in the transport region 42. The quantum-well layers 31 are not interrupted in a junction region between the emission region 41 and the transport region 42.

[0086] FIG. 19 shows that in the transport region 42, seen in cross-section, a twin structure composed of two triangles can be present.

[0087] The description with the aid of the exemplary embodiments does not limit the invention described here thereto. Rather, the invention comprises any new feature and any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or this combination is not itself explicitly stated in the patent claims or exemplary embodiments.