NANOWIRE-BASED INTEGRATED VIA IN ANODIC ALUMINUM OXIDE LAYER FOR CMOS APPLICATIONS

Abstract

A complementary metal-oxide-semiconductor (CMOS) device includes a metal oxide layer comprising anodic aluminum oxide (AAO) and one or more nanowires (NW) of an electrically conducting material each formed within a corresponding pore extending through the AAO from a first side of the layer to a second side of the layer opposite the first side, a first electrically conducting layer disposed on the first side of the metal oxide layer, and a second electrically conducting layer disposed on the second side of the metal oxide layer. The nanowires form a via electrically connecting first electrically conducting layer and the second electrically conducting layer.

Claims

1. A complementary metal-oxide-semiconductor (CMOS) device, comprising: a metal oxide layer comprising anodic aluminum oxide (AAO) and one or more nanowires (NW) of an electrically conducting material each formed within a corresponding pore extending through the AAO from a first side of the layer to a second side of the layer opposite the first side; a first electrically conducting layer disposed on the first side of the metal oxide layer; and a second electrically conducting layer disposed on the second side of the metal oxide layer, wherein the one or more nanowires form a via electrically connecting the first electrically conducting layer and the second electrically conducting layer.

2. The CMOS device of claim 1, wherein the metal oxide layer has a thickness of 5 μm or less.

3. The CMOS device of claim 1, wherein the metal oxide layer has a thickness in a range from 1 μm to 2 μm.

4. The CMOS device of claim 1, wherein the electrically conducting material of the NWs is Cu.

5. The CMOS device of claim 1, further comprising a Si layer, the metal oxide layer and first and second electrically conducting layers being disposed on the Si layer.

6. The CMOS device of claim 1, wherein the via comprises a bundle of NWs.

7. The CMOS device of claim 1, wherein the AAO has a porosity in a range from 8% to 30%.

8. The CMOS device of claim 7, wherein the first electrically conducting layer is a Cu layer.

9. The CMOS device of claim 8, further comprising an adhesion layer between the Cu layer and the metal oxide layer.

10. The CMOS device of claim 9, wherein the adhesion layer comprises TiW alloy and TiW oxide.

11. The CMOS device of claim 10, further comprising a layer of Ti between the Cu layer and the Si layer.

12. The CMOS device of claim 1, wherein at least the first or second electrically conducting layer comprises a coplanar waveguide (CPW).

13. An integrated circuit comprising the CMOS device of claim 1.

14. A communication system for operation at millimeter or sub-millimeter wavelengths comprising the integrated circuit of claim 13.

15. A method for forming a semiconductor device, comprising: forming a first electrically conducting layer on a substrate; forming an adhesion layer comprising an alloy on the first electrically conducting layer; forming a layer of aluminum on the adhesion layer; anodizing the aluminum to form a metal oxide layer comprising anodic aluminum oxide (AAO), the metal oxide layer comprising a plurality of nanopores extending through the AAO from a first side of the metal oxide layer to the first electrically conducting layer; depositing an electrically conducting material in the nanopores to form nanowires (NW) in the nanopores; and after depositing the electrically conducting material in the nanopores, forming a second electrically conducting layer on the metal oxide layer, wherein the one or more nanowires form a via electrically connecting the first electrically conducting layer and the second electrically conducting layer.

16. The method of claim 15, wherein the semiconductor device is a complementary metal-oxide-semiconductor (CMOS) device.

17. The method of claim 16, wherein the via comprises a bundle of NWs.

18. The method of claim 16, wherein the metal oxide layer has a thickness of 5 μm or less.

19. The method of claim 16, wherein the electrically conducting material is Cu.

20. The method of claim 19, wherein the adhesion layer comprises TiW.

Description

DESCRIPTION OF DRAWINGS

[0039] FIG. 1A is a cross-sectional schematic diagram showing a portion of an example device with NW vias formed in a AAO layer between two electrically conducting layers on a silicon substrate.

[0040] FIG. 1B is a cross-sectional schematic diagram showing a close up of an adhesion layer of the example device shown in FIG. 1A.

[0041] FIG. 2A-2H are cross-sectional schematic diagrams showing a sequence of steps in an example method of forming the device shown in FIG. 1A.

[0042] FIG. 3 is a Scanning Electron Micrograph (SEM) of an example article with nanowires formed in an AAO layer on a silicon substrate.

[0043] FIG. 4A is a cross-sectional diagram showing a one-unit CPW circuit that includes NW vias in an AAO layer.

[0044] FIG. 4B is a plan view of the one-unit CPW circuit shown in FIG. 4A.

[0045] FIG. 4C is a plan view of another example, five-unit CPW circuit that includes NW vias in an AAO layer.

[0046] FIGS. 5A-5E are plots showing insertion loss performance of example CPW circuits with NW vias across a frequency range from 0 GHz to 40 GHz.

[0047] Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0048] Referring to FIG. 1A, an integrated circuit (IC) device 100 includes a nanopore layer 150 that includes multiple nanowires (NWs) 170 penetrating through the nanopore layer 150 providing a via electrically connecting an upper conducting layer 160 and a lower electrically conducting layer 130. The nanopore layer 150 is composed of AAO. The electrically conducting layers 130 and 160 are typically metal layers (e.g., Au, Pt, or Cu). NWs 170 are formed by depositing an electrically conducting material, such as a suitable metal (e.g., Cu or Ni), in the nanopores in the nanopore layer 150. The material forming the NWs can be the same electrically conducting material as that used for one or both of the electrically conducting layers 130 and 160. In some embodiments, copper can be used for the NWs 170 and/or one or both of the electrically conducting layers 130 and 160.

[0049] The nanopore layer 150 and conducting layers 130 and 160 are supported by a substrate 110, such as a Si wafer (e.g., a high resistivity Si wafer). An adhesion layer 120 is deposited between the lower electrically conducting layer 130 and substrate 110. The intervening layer 120 can be formed from a material that promotes adhesion between the substrate material and the material forming the lower electrically conducting layer 130. For example, intervening layer 120 can be a titanium layer which can promote adhesion between a Si wafer and an electrically conducting layer.

[0050] A second adhesion layer 140 is deposited between the lower electrically conducting layer 130 and the nanopore layer 150. Referring also to FIG. 1B, which shows a close up section of device 100, adhesion layer 140 is composed in part of an alloy (e.g., TiW) and in part of an oxide of the alloy (e.g., TiW oxide). These portions are depicted in FIG. 1B as layers 142 and 144 in which layer 144 is the oxide portion of adhesion layer 140 and is generally adjacent the AAO of the nanopore layer 150, while layer 142 is the alloy portion and is generally adjacent electrically conducting layer 130. While depicted as discrete planar layers, these portions may have uneven thicknesses. For example, in some areas, the alloy oxide portion can penetrate nearly the entire depth of adhesion layer 140 from the nanopore layer 150 to close to the top surface of the lower electrically conduction layer 130. In other areas, the entire adhesion layer may be pure alloy through its depth with no oxidation.

[0051] The porosity of the nanopore layer 150 can be in a range from about 8% to about 30%. Typically, the porosity varies by about 1% within a single sample. The size of the nanopores can also vary as desired. In some embodiments, the nanopores have a lateral dimension (i.e., in the plane of the nanopore layer) in a range from 5 nm up to 250 nm. Nanopore lateral dimensions may vary about 10% in any one sample. For example, individual samples can include nanopores with a lateral dimension that varies from 9-11 nm or 45-55 nm.

[0052] In some embodiments, nanopore layer 150 includes areas in which the nanopores do not include NWs. For example, patterned deposition can be used to selectively formed NWs in certain regions of nanopore layer 150. Generally, the area of nanopore layer 150 that includes NWs corresponds to the size of the via and this size can vary depending on the application. In some embodiments, vias can have a lateral dimension of 100 μm or less (e.g., 50 μm or less, 20 μm or less, 10 μm or less, 5 μm or less).

[0053] The NWs 170 may penetrate through adhesion layer 140 so that the electrically conducting material forming the NWs is in physical contact with the lower electrically conducting layer 130. Alternatively, or additionally, adhesion layer 140 can provide an electrical connection between NWs 170 and the lower electrically conducting layer 130.

[0054] In general, the composition of the alloy can be established empirically. As noted above, the alloy in adhesion layer 140 can be TiW. Generally, the relative concentration of Ti to W can vary as appropriate and the relative concentrations can be optimized empirically. In some embodiments, the alloy is at least 50% W by weight (e.g., 60% or more, 70% or more, 80% or more, 90% or more, such as up to 98%.) In some embodiments, the TiW alloy is Ti.sub.xW.sub.1-x, where 0.05<x<0.2. For example, the alloy can be Ti.sub.0.1 W.sub.0.9 (Ti 10/W 90 wt. %). In some embodiments, other metals can be included either as an alternative to Ti or W, or in addition to Ti and W.

[0055] In general, the thickness of the different layers disposed on the substrate 110 can vary as appropriate and can, in certain embodiments, be relatively thin. For example, the nanopore layer 150 can be about 2 μm or less (e.g., 1.5 μm or less, 1.2 μm or less, 1.0 μm or less, 0.9 μm or less, 0.8 μm or less, such as as thin as 0.5 μm). The thickness of electrically conducting layers 130 and 160 can be the same, or the two layers can have different thickness. In some embodiments, these layers have a thickness in a range from 0.5 μm to about 5 μm (e.g., from 1 μm to 3 μm, such as 1 μm to 2 μm). Generally, intervening layer 120 and adhesion layer 140 are thinner than lower electrically conducting layer 130. In certain embodiments, intervening layer 120 has a thickness less than 100 nm (e.g., 20 nm to 80 nm, such as 40 nm to 50 nm). Adhesion layer 140 can have a thickness less than 200 nm (e.g., 20 nm to 150 nm, such as 50 nm to 100 nm).

[0056] In general, the IC device 100 can be incorporated into a variety of more elaborate IC structures, including complementary metal-oxide-semiconductor (CMOS) devices. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS), and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for many types of communication. Accordingly, IC device 100 can be incorporated into any of the aforementioned CMOS devices. In some embodiments, IC device 100 is incorporated into a millimeter or sub-millimeter wave communication system using CMOS technology.

[0057] Forming IC device 100 generally involves anodizing a layer of aluminum to form the nanoporous AAO layer 150 over a copper layer and then depositing a metal (or other electrically conducting material) over the AAO layer to provide NWs 170 within the pores of the AAO layer. Referring to FIGS. 2A-2H, which schematically shows cross-sectional portions of the device at different stages of the fabrication process, an example process proceeds as follows.

[0058] First, a multilayer film stack 200 is formed on a Si wafer substrate 110. This stack is shown in FIG. 2A and is composed of, in order, layer 120 of Ti on the Si substrate 110's surface, metal layer 130 (e.g., Cu) on the Ti layer 120, an adhesion layer 220 composed of a TiW alloy on the surface of metal layer 130, and an Al layer 210 on the adhesion layer 220.

[0059] FIGS. 2B-2G show different stages in the Al anodization process. Referring to FIG. 2B specifically, anodization of the Al layer 210 chemically transforms aluminum in the Al layer 210 into AAO 250 perforated by pores 271. The nanoporous oxide 271 extends progressively deeper into the remaining Al 211, but the pores are separated from the aluminum by a barrier layer of aluminum oxide at the base of each pore 271.

[0060] Referring to FIGS. 2C and 2D, oxidation of the aluminum proceeds through the depth of the Al layer 250 to the TiW adhesion layer below where it begins to oxidize portions of the adhesion layer, resulting in portions 222 of TiW oxide in a continuous layer 221 of TiW. Without wishing to be bound by theory, it is believed that when the anodization process reaches the TiW layer 220, O.sup.2− and OH.sup.− anions in the anodizing solution are drawn through the barrier layer at the base of the pore 271 by the strong electric field and TiW then starts to be anodized to TiW oxide 222.

[0061] Referring to FIG. 2E, further anodization results an inverted pore base 272 forming in the adhesion layer beneath pore 271 due to further oxidation of the TiW of the adhesion layer and the deepening on the pore 271. It is believed that TiW directly under the pore is anodized to TiW oxide, while TiW under the pore walls remains, and the barrier layer shape is changed due to the volume expansion stress of further anodization. The result is inverted pore base 272

[0062] Referring to FIG. 2F, ongoing anodization further reduces the thickness of the barrier layer separating pore 271 from inverted pore base 272. Over anodization begins to etch the TiW oxide separating the pore 271 from the inverted pore base 272 (FIG. 2G), ultimately forming a channel through the AAO layer 250, the TiW oxide 222, and the TiW 221 (FIG. 2H), resulting in a nanopore that extends from the top surface of the AAO layer 250 through to the Cu layer 130. Over-anodization for 1-2 minutes can enable the anodizing solution to etch the barrier layer and TiW oxide in an attempt to reach the bottom metal layer 130. At this stage, the anodization current may increase because most pores start to open together by over-anodization and the electrically conductive area (i.e., of metal layer 130) increases rapidly. Further over-anodization can increase the current very rapidly and decreases after some time, resulting in damage to the metal layer 130 and/or dissolution of metal from the metal layer 130. Accordingly, the anodization can be stopped at the soon after an increase in current is observed in order to reduce damage to the metal layer 130 due to over-anodization.

[0063] Further process steps are possible. For example, the diameter of the pores can be widened by further chemical etching. In some embodiments, in order to complete pore perforation and widen the pores as needed, conventional chemical etching (e.g., using 5 wt % H.sub.3PO.sub.4) can be used since TiW oxide can be etched in aqueous solutions.

[0064] After forming the pores, the NW material (e.g., Cu) is deposited into the pores to form the NWs. While Cu is mentioned as an example, more generally any suitable electrically conducting material can be used, including other metals such as nickel. Any method appropriate for depositing the material into the pores under conditions in which the AAO layer is maintained can be used. For example, electrodeposition can be used to deposit, e.g., metals into the pores.

[0065] After formation of the NWs, the top surface can be polished (e.g., using chemical mechanical polishing) to provide a flat surface for further processing steps (e.g., deposition of another electrically conducting layer or other materials).

[0066] An example of an AAO nanoporous layer with NWs formed using this method is shown in cross-section in FIG. 3. In this example, a 1-μm thick layer of AAO is integrated on a Si substrate using a TiW adhesion layer with electrodeposited Cu NWs. The AAO layer is the top layer and the NWs are visible as white rods through AAO due to 15 kV acceleration voltage.

[0067] In general, it is believed that the TiW adhesion layer allows robust and reliable integration of AAO on substrates, to remove barrier layer for electrical contact, and to widen pores of the AAO for various nanomaterials and devices without issues caused by using Ti and reverse bias-based etching (e.g., unremovable barrier layer or AAO delamination).

[0068] Conventional techniques to remove a barrier layer that results from AAO formation: (i) decreasing the anodization voltage; and (ii) electrochemical etching via reversed bias. However, decreasing the anodization voltage can result in the dendritic pore channels near the barrier layer, which are not uniformly straight vertical pores. Also, electrochemical etching via reversed bias (e.g., for inducing localized alumina dissolution to reveal the metal base) can catalyze the electrolysis of water and makes H.sub.2 gas causing delamination of AAO from the substrate even with a Ti adhesion layer.

[0069] When a Ti adhesion layer is used between metal layer and Al, for example, Ti can be oxidized to TiO.sub.2 under Al anodization conditions. But, TiO.sub.2 is another insulating oxide and can be hard to remove since it is chemically stable. Also, when a thin Ti layer (e.g., <5 nm) is used as an adhesion promoter, the whole Ti layer can easily be converted to TiO.sub.2 and its adhesion can be lost. Conversely, thick Ti (e.g., >20 nm) can form a thick TiO.sub.2 barrier layer which is difficult to remove. An intermediate thickness Ti layer (e.g., 5-20 nm) can be used, but electrochemical etching via reversed bias may be needed to remove the barrier layer, causing AAO delamination.

[0070] Viability of vias formed using the techniques disclosed herein for CMOS application at millimeter-wave frequencies has been demonstrated as described below. Coplanar waveguide (CPW) lines were fabricated on a 5000 Ω.Math.cm high resistivity silicon wafer and connected by Cu nanowire vias that were grown in integrated anodized alumina oxide (AAO). The AAO layer was fabricated by anodizing an evaporated aluminum layer on the silicon wafer as described above. This co-integrated technology was demonstrated as having 0.095 dB insertion loss for 0.3 mm long circuits with two vias at 40 GHz. Estimated loss per via was ˜0.0275 dB. The fabricated structure showed excellent performance agreement with reference test circuits of similar length. The design comparisons of circuits with different via dimensions and positions showed that the shorter via length, wider via width and placing the via on the CPW ground plane closer to the signal line provided improved performance.

[0071] Referring to FIGS. 4A-4B, the NW vias are tested through CPW lines, shown in sectional view in FIG. 4A and plan view in FIG. 4B. Here, a one-unit cell circuit includes a Via-AAO-CPW section and two CPW feed lines 460 and 461. The Via-AAO-CPW section is defined by two rectangular vias 472 (each composed of numerous NWs 470) plus a CPW 430 below an AAO section 452 having a length L1. The entire structure was formed on a Si substrate 410 and feed lines 460 and 461 were electrically isolated from CPW 430 by air regions 411. The one-unit CPW circuit was surrounded by a grounded electrode, G.

[0072] Two types of vias were constructed. Type 1 had via length (VL) of 90 μm and via a width (VW) on signal line (S) and ground (G) of 80 μm and 390 μm, respectively. Type 2 had equal VW on S and G, VL is varied from 30 μm to 150 μm and VW was varied from 30 μm to 70 μm. The optimized via location on G was studied by comparing an offset value, Δx, of zero and 130 μm.

[0073] Referring specifically to FIG. 4C, to further enhance the signal level of vias, a five-unit CPW circuit 401 with vias was designed to include five Via-AAO-CPW sections for a total of 10 NW vias.

[0074] Here, a CPW line was fabricated on a 500 μm thick 5000 Ω.Math.cm resistivity Si wafer. The 1.2 μm AAO template was anodized from an evaporated aluminum (Al) layer that was pore widened to an average of 20 nm pore diameter and 9% porosity. Next, the Cu NWs were grown into the AAO template using electrodeposition. The vias were created by connecting the NWs in pores to the top Cu layer.

[0075] The fabricated structures were characterized using an Anritsu 37369D VNA up to 40 GHz connected to a Cascade probe station RF-1. A 500 μm thick 5000 Ω.Math.cm high resistivity Si wafer was included between measured sample and the metallic chuck for isolation. LRM calibration was performed with Cascade ACP50 probes (pitch of 150 μm) and an ISS 101-190 calibration chip. The reference plane was the probe tip.

[0076] In FIG. 5A, a comparison of insertion loss for a one-unit CPW with type 1 NW via and its 1,224 μm reference circuits are shown as a function of signal frequency from 0 to 40 GHz. The data of CPW with type 1 via agrees well with the reference circuits and demonstrates around 0.05 dB lower insertion loss between 25-30 GHz. This is believed to confirm the benefit of using Cu NW-based vias which provide similar performance to standard CPW lines. Here, S11 and S21 refer to scattering parameters commonly used to describe the performance of microwave circuits. They may be determined as the voltage ratio between output port and input port. For example, S21 can be determined as the output voltage at port 2 divided by input voltage at port 1. Put another way, S11 is a reflection coefficient and describes how much of the input signal is reflected signal. S21 is an insertion loss and describes how much of the input signal is transmitted to the output port

[0077] In FIG. 5B, a comparison of HFSS (High Frequency Structure Simulation, software commercially available from Ansys, Inc., Canonsburg Pa.) simulation and measurement results are shown. For the simulation, due to the high aspect ratio between the Cu NW diameters and CPW dimensions (e.g., nm diameters vs um widths and lengths and height), the NW vias were represented by Cu pillars with 1.2 μm thickness, 5×5 μm.sup.2 area and 9% porosity. The comparison shows that the measurement follows the simulation trend in S21 data presented in FIG. 5A. It is believed that the differences between the measured S11 and the simulation may be due to the fabrication defects, such as over etching.

[0078] FIG. 5C shows a plot of measurement data comparing insertion loss for different via widths. With the same VL of 90 μm, larger VW shows better insertion loss and reflection coefficient. CPW with type 1 NW via shows the best performance among the different vias, presumably due to its widest VW on both S and G plane which provides more area for current to flow through.

[0079] In FIG. 5D, a via length comparison is shown. Specifically, insertion loss is shown as a function of frequency for vias with differing VLs. Both circuits have VW of 30 μm. The circuits with VL of 150 μm shows higher insertion loss compared to VL of 90 μm. It is believed that this is because the longer VL introduces a longer signal path which can result in higher insertion loss.

[0080] FIG. 5E shows a comparison of via offset, Δx, relative to the midpoint in the ground plane width. In particular, insertion loss is plotted as a function of frequency for vias with a Δx of 0 μm (traces A and C) and for vias with a Δx of 130 μm (traces B and D). Both circuits possess the same via size dimensions. From the measurement results, higher Δx shows better S21 data. Therefore, it is believed that placing via position on G closer to S can provide better via performance.

[0081] In order to find the loss of Via-AAO-CPW section, influences from other CPW lines in the test circuits should be removed. The five-unit CPW 401 with vias includes two feed line (L2), four CPW sections (L3) and five Via-AAO-CPW sections. The loss of L2 and L3 sections can be measured and obtained from standard CPW lines. So, the insertion loss of 0.3 mm long Via-AAO-CPW section with type 1 vias can be calculated with the values of 0.043 at 20 GHz, 0.07 at 30 GHz and 0.095 at 40 GHz (in dB) using the following equation.

[00001]$\mathrm{Loss}=-10\times \log \frac{.Math.S_{21}.Math..Math..Math.S_{12}.Math.}{1-.Math.S_{11}.Math..Math..Math.S_{22}.Math.}$

[0082] Next, to find the loss of single G-S-G via, the loss of CPW below AAO section (L1) should be removed from Via-AAO-CPW section. Two methods are available to remove the loss of L1 and approximate each via loss. The first assumes the loss of a 100 μm CPW below the AAO layer is equal to a 100 μm standard CPW without AAO and can be obtained from measurement. Using the equation above, the attenuation loss can be obtained. The loss of a 100 μm standard CPW above Si wafer is 0.011 at 20 GHz, 0.018 at 30 GHz and 0.024 at 40 GHz (in dB). Therefore, each type 1 G-S-G via loss is expected to be 0.016 at 20 GHz, 0.026 at 30 GHz and 0.035 at 40 GHz (in dB).

[0083] The second method assumes the loss of the CPW below the AAO layer is represented by simulation results which is 0.024 at 20 GHz, 0.0379 at 30 GHz and 0.04 at 40 GHz (in dB). Then, each type 1 G-S-G via loss is calculated to be 0.0095 at 20 GHz, 0.016 at 30 GHz and 0.0275 at 40 GHz (in dB).

[0084] The comparison of type 1 via and other via technologies reported in technical literature is shown in the following table.

TABLE-US-00001 Insertion loss of Insertion loss of test line with two Via Line one G-S-G via G-S-G vias at 40 Hz Thickness Length No. Substrate (dB) (dB) Via Size (mm) (mm) 1 Si: 5000 ~0.0275 0.095 (Via-AAO- S: VL × VW = 1.2 0.300 Ω .Math. cm at 40 GHz CPW section) 90 μm × 80 μm resistivity G: VL × VW = (CPW) & 90 μm × 390 μm AAO (via) 2 Si: 5000 0.53 0.93 Via diameter = 252 3.15 Ω .Math. cm at 75 GHz 42 μm resistivity 3 Si: High 0.03 ~0.3 Via diameter = 100 2.7 resistivity at 40 GHz 200 μm 4 AAO 0.035 ~0.21 20 × 30 μm.sup.2 50 0.200 at 40 GHz

[0085] No. 1 refers to the via technology reported here. No. 2 was reported by S. J. Bleiker, A. C. Fischer, U. Shah, N. Somjit, T. Haraldsson, N. Roxhed, J. Oberhammer, G. Stemme, and F. Niklaus, in in “High Aspect-ratio through silicon vias for high-frequency application fabricated by magnetic assembly of gold-coated nickel wires,” IEEE Trans. Compon., Packag. Manuf. Technol., vol. 5, no. 1, pp. 21-27, January 2015. No. 3 was reported by A. Margomenos and L. P. B. Katehi, in “Fabrication and accelerated hermeticity testing of an on-wafer package for RF MEMS,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 6, pp. 1626-1636, 2004. No. 4 was reported by J. M. Pinheiro, M. V Pelegrini, L. Amorese, P.

[0086] Ferrari, G. P. Rehder, and A. L. C. Serrano, in “Nanowire-based through substrate via for millimeter-wave frequencies,” in IEEE MTT-S Int. Microw. Symp. Dig., San Francisco, Calif., USA, May 2016, pp. 1-4.

[0087] Compared to the other work, the vias disclosed here are extremely thin. Considering the 50 μm via thickness in No. 4 and the circuit has 2 vias, the total signal path length is 0.3 mm which is similar to the via-AAO-CPW structures described above. The lower insertion loss of the total signal line with via at 40 GHz, 0.095 dB, is significantly lower than that reported by J. M. Pinheiro et al.

[0088] Of course, the dimensions of the vias, CPWs, and other portions of the structures described in FIGS. 4A-4C that are characterized by the experimental data presented in FIGS. 5A-5E are merely examples and, generally, dimensions for similar structures in other embodiments can be determined (e.g., empirically or by calculation) based on the specific application in mind.

[0089] A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, while the foregoing techniques involves forming vias on a Si substrate, the techniques can be applied to forming vias on other substrates, such as on glass (e.g., borosilicate glass) and polymer (e.g., polyimide) substrates. Accordingly, other embodiments are within the scope of the following claims.