Electronic circuit and electronic timepiece

Abstract

Provided are an electronic circuit and electronic timepiece that can initialize internal circuits even if chattering occurs when a battery is installed. In the electronic circuit, when the initialization state hold signal is input, the initialization control circuit continues outputting the initialization control signal at the first level until the clock signal is output; and when the initialization state hold signal is input and the clock signal is output, outputs the initialization control signal at the second level cancelling the initialization process to the initialization circuit.

Claims

1. An electronic circuit comprising: an oscillator circuit configured to output a clock signal; a function control circuit configured to output a function control signal that sets a function mode and a non-function mode; an internal circuit; an initialization circuit configured to output an initialization control signal that changes between a first level executing an internal circuit initialization process, and a second level cancelling the initialization process; an initialization control circuit configured to control the initialization circuit; an input control circuit configured to change input and non-input of the function control signal to the initialization control circuit; and an initialization state holding circuit; the initialization circuit outputting the initialization control signal at the first level when a battery is installed; the input control circuit not inputting the function control signal to the initialization control circuit when the initialization control signal is output at the first level, and inputting the function control signal to the initialization control circuit when the initialization control signal is output at the second level; the initialization state holding circuit outputting an initialization state hold signal to the initialization control circuit when the function control signal is not input to the initialization control circuit; and the initialization control circuit, when the initialization state hold signal is input, continuing to output the initialization control signal at the first level to the initialization circuit until the clock signal is output, and when the initialization state hold signal was input and the clock signal then output, outputting the initialization control signal at the second level to the initialization circuit.

2. The electronic circuit described in claim 1, wherein: the initialization circuit has a capacitor, outputs the initialization control signal at the first level when the voltage charge of the capacitor is less than a previously set threshold, and outputs the initialization control signal at the second level when the voltage charge is greater than or equal to the threshold; and the initialization control circuit charges the capacitor according to the clock signal when the initialization state hold signal is input.

3. The electronic circuit described in claim 1, further comprising: a delay circuit configured to delay the initialization control circuit output from the initialization circuit to the internal circuit.

4. The electronic circuit described in claim 1, further comprising: an operation input terminal to which an operating signal corresponding to operation of an operating member is input; and an operation input control circuit configured to switch input and non-input of the operating signal to the function control circuit; the function control circuit outputting the function control signal that sets the function mode in response to the operating signal; the function control signal is input to the internal circuit; and the operation input control circuit does not input the operating signal to the function control circuit while the initialization control signal is output at the first level.

5. An electronic timepiece comprising: the electronic circuit described in claim 1; and a display device configured to display time as controlled by the internal circuit.

6. An electronic timepiece comprising: the electronic circuit described in claim 2; and a display device configured to display time as controlled by the internal circuit.

7. An electronic timepiece comprising: the electronic circuit described in claim 3; and a display device configured to display time as controlled by the internal circuit.

8. An electronic timepiece comprising: the electronic circuit described in claim 4; and a display device configured to display time as controlled by the internal circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a plan view of an electronic timepiece according to the invention.

(2) FIG. 2 is a circuit diagram of an IC device according to an embodiment of the invention.

(3) FIG. 3 is a circuit diagram of an initialization control circuit and initialization circuit according to an embodiment of the invention.

(4) FIG. 4 is a circuit diagram of an input control circuit according to an embodiment of the invention.

(5) FIG. 5 is a timing chart of the operation of the IC device according to an embodiment of the invention.

(6) FIG. 6 is a circuit diagram of an IC device according to another embodiment of the invention.

(7) FIG. 7 is a circuit diagram of a delay circuit according to another embodiment of the invention.

(8) FIG. 8 is a timing chart of the operation of the IC device according to another embodiment of the invention.

(9) FIG. 9 is a circuit diagram of an IC device according to another embodiment of the invention.

(10) FIG. 10 is a circuit diagram of an IC device according to the related art.

(11) FIG. 11 is a circuit diagram of an initialization control circuit and initialization circuit according to the related art.

(12) FIG. 12 is a timing chart of the operation of the IC device according to the related art.

(13) FIG. 13 illustrates operation when chattering occurs in an IC device according to the related art.

DESCRIPTION OF EMBODIMENTS

Embodiments

(14) Preferred embodiments of an electronic timepiece 1 according to the present invention are described below with reference to the accompanying figures. Note that like configurations in the following embodiments and the electronic timepiece according to the related art described above are identified by like reference numerals, and further description thereof is omitted.

(15) As shown in FIG. 1, the electronic timepiece 1 in this embodiment of the invention is a wristwatch worn on the user's wrist, and has an outside case 2, round dial 3, a movement not shown, a second hand 5, minute hand 6, and hour hand 7 that are hands driven by a motor disposed to the movement, and a crown 8 and button 9 as operating members. The second hand 5, minute hand 6, and hour hand 7 are driven by a motor not shown, and indicate the second, minute, and hour by pointing to markers on the dial 3. The hands 5 to 7 and dial 3 thus embody a display unit for displaying the time.

(16) As shown in FIG. 2, the IC device 10A, which is an electronic circuit of the electronic timepiece 1, includes an oscillator circuit 11, frequency divider 12, pulse shaping filter 13, driver 14, test control circuit 15 as a function control circuit, initialization control circuit 20A, initialization circuit 30, initialization state holding circuit 16, and input control circuit 40. The frequency divider 12, pulse shaping filter 13, and driver 14 are internal circuits. The IC device 10A includes power supply terminals VDD, VSS, connection terminals GATE, DRAIN, O1, O2, operation input terminal P1, and test terminal TEST.

(17) An initialization control signal is input to the input control circuit 40. When a Low level initialization control signal is input, the test control signal (function control signal) is not input to the initialization control circuit 20A. When a High level initialization control signal is input, the test control signal is input to the initialization control circuit 20A. In this embodiment of the invention, the signal level of the test control signal is inverted when input to the initialization control circuit 20A.

(18) When the test control signal is not input to the initialization control circuit 20A, the initialization state holding circuit 16 outputs a Low level initialization state hold signal to the initialization control circuit 20A. When the test control signal is input to the initialization control circuit 20A, the initialization state hold signal is not output to the initialization control circuit 20A. This embodiment uses a constant-current source as the initialization state holding circuit 16.

(19) Configuration of the Initialization Control Circuit

(20) As shown in FIG. 3, the initialization control circuit 20A has logic circuits 23, 24. The logic circuits 23, 24 each have a first input terminal 231, 241 and second input terminal 232, 242, and one output terminal.

(21) The output terminal 41 (see FIG. 4) of the input control circuit 40 and the initialization state holding circuit 16, which is a constant-current source, are connected to the first input terminal 231 of the logic circuit 23, and the clock signal is input to the second input terminal 232. The output terminal of the logic circuit 23 is connected to the gate electrode of the field effect transistor N2 of the initialization circuit 30, and the second input terminal 242 of logic circuit 24.

(22) The output terminal 41 of the input control circuit 40, and the initialization state holding circuit 16, are connected to the first input terminal 241 of the logic circuit 24, and the output terminal of the logic circuit 23 is connected to second input terminal 242. The output terminal of the logic circuit 24 is connected to the gate electrode of the field effect transistor N1 of the initialization circuit 30.

(23) When the test control signal is not input, an initialization state hold signal (Low level) is input, and the clock signal is not input to the initialization control circuit 20A, logic circuit 23 outputs a High level signal and field effect transistor N2 goes on, and logic circuit 24 outputs a Low level signal and field effect transistor N1 goes off.

(24) When the test control signal is not input, the initialization state hold signal is input, and the clock signal is input, logic circuit 23 outputs a Low level signal each time the clock signal changes from the Low level to the High level, and outputs a High level signal each time the clock signal changes from the High level to the Low level. The logic circuit 24 outputs a signal at the inverted level of the output level of logic circuit 23. As a result, a state in which field effect transistor N1 is on and field effect transistor N2 is off, and a state in which field effect transistor N1 is off and field effect transistor N2 is on, are alternately set.

(25) When the High level signal setting the non-test mode (non-function mode) is input inverted by the input control circuit 40, the initialization control circuit 20A operates in the same way as when the initialization state hold signal is input.

(26) When the Low level signal setting the test mode (function mode) is input inverted by the input control circuit 40 to the initialization control circuit 20A, the logic circuits 23, 24 always output a High level signal regardless of the clock signal. As a result, field effect transistors N1 and N2 are on.

(27) Configuration of the Input Control Circuit

(28) The input control circuit 40 is embodied by a clocked inverter, and as shown in FIG. 4, has n-channel field effect transistors N11, N12, N13, and p-channel field effect transistors P11, P12, P13.

(29) Field effect transistors P12, P13 are connected in series between the power supply terminal VDD and output terminal 41. Field effect transistors N12, N13 are connected in series between power supply terminal VSS and output terminal 41.

(30) The test control signal is input to the gate electrodes of field effect transistors N13, P13. The initialization control signal is input to the gate electrode of field effect transistor N12.

(31) Field effect transistors P11, N11 are connected in series between power supply terminal VDD and power supply terminal VSS. The connection node between field effect transistors P11, N11 is connected to the gate electrode of field effect transistor P12. The initialization control signal is input to the gate electrode of field effect transistors P11, N11.

(32) When a Low level initialization control signal is input, the field effect transistors N1 and N2 of the input control circuit 40 turn off, field effect transistor P11 turns on, and field effect transistor N11 turns off. As a result, the potential of the gate electrode of field effect transistor P12 goes to VDD, and field effect transistor P12 turns off. As a result, the output terminal 41 is isolated form power supply terminals VDD, VSS, and goes to a high impedance state.

(33) When a High level initialization control signal is input, the field effect transistors N1 and N2 of the input control circuit 40 go on, field effect transistor P11 turns off, and field effect transistor N11 turns on. As a result, the potential of the gate electrode of field effect transistor P12 goes to VSS, and field effect transistor P12 turns on. As a result, the output terminal 41 is connected to power supply terminals VDD, VSS, and a signal of the inverted phase of the test control signal is output from the output terminal 41. In other words, when a High level test control signal is input, a Low level signal is output from the output terminal 41. The input control circuit 40 is able to pass more current than the constant-current source. As a result, a High level signal is output from the output terminal 41 when the Low level test control signal is input.

(34) IC Device Operation

(35) Operation of the IC device 10A is described next with reference to the timing chart in FIG. 5.

(36) As shown in FIG. 5, because a charge is not stored in capacitors C1 and C2 of the initialization circuit 30 when a battery is installed in the electronic timepiece 1 at time T1, the potential of node A1 is VDD, and a Low level initialization control signal is output from the NOT gate 31.

(37) Immediately after time T1, the oscillator circuit 11 does not output the clock signal. The test control circuit 15 outputs a test control signal setting the non-test mode (normal mode) by outputting a High level signal.

(38) Because a Low level initialization control signal is output, the output terminal 41 of the input control circuit 40 is isolated from the power supply terminals VDD, VSS, and goes to a high impedance state. As a result, because of the constant-current source, that is, the initialization state holding circuit 16, the potential of the first input terminals 231, 241 of the logic circuits 23, 24 in the initialization control circuit 20A decreases to VSS, and goes to a Low level. That is, a Low level initialization state hold signal is output from the initialization state holding circuit 16 to the initialization control circuit 20A.

(39) As a result, the capacitors C1 and C2 are not charged, and the potential of node A1 is held at VDD. The NOT gate 31 therefore continues to output a Low level initialization control signal. The frequency divider 12, pulse shaping filter 13, and driver 14 therefore execute the initialization process, and circuits 12 to 14 are set to the time display mode.

(40) When a battery is installed, chattering may occur at the power supply terminal VDD as indicated by waveform W1. When this happens, the signal level of the test control signal may repeatedly change between the High level and Low level. However, the test control signal is not input to the initialization control circuit 20A by the input control circuit 40, and the initialization state hold signal is output from the initialization state holding circuit 16 to the initialization control circuit 20A in this embodiment of the invention, the capacitors C1 and C2 are not charged as described above, and the initialization circuit 30 can continue to output a Low level initialization control signal.

(41) When the oscillator circuit 11 then starts operating and outputs the clock signal at time T2 while the test control circuit 15 outputs a test control signal setting the non-test mode, capacitors C1 and C2 are alternately charged, and the potential of node A1 decreases toward VSS.

(42) Then at time T3, the potential of node A1 goes to or below the threshold of the NOT gate 31, and a High level initialization control signal is output from the NOT gate 31. As a result, the initialization process of the frequency divider 12, pulse shaping filter 13, and driver 14 is cancelled. Note that the circuits 12 to 14 remain in the time display mode.

(43) When a High level initialization control signal is output, the output terminal 41 of the input control circuit 40 is connected to power supply terminals VDD, VSS, and a signal of the inverted phase of the test control signal is output from the output terminal 41. Because the test control signal is a High level signal at this time, a Low level signal is output from the output terminal 41. As a result, the potential of node A1 of the initialization circuit 30 is held at VSS by the initialization control circuit 20A, and the NOT gate 31 continues outputting a High level initialization control signal.

(44) When at time T4 the crown is pulled out to the first stop in the operation to start the test mode, and the test signal is input to the test terminal TEST, the test control circuit 15 outputs the test control signal setting the test mode by outputting a Low level signal. As a result, the frequency divider 12 and pulse shaping filter 13 are set to the test mode. In the test mode, the waveform of the motor drive pulse is tested, and the consumption current is tested.

(45) As a result, a High level signal is output from the input control circuit 40. The potential of node A1 therefore goes to the VSS by the initialization control circuit 20A, and the NOT gate 31 continues outputting a High level initialization control signal.

(46) Because the frequency divider 12, pulse shaping filter 13, and driver 14 test runs at time T5, the clock signal output process of the oscillator circuit 11 is stopped by control of the test control circuit 15. Because the potential of node A1 remains at VSS in this case, the NOT gate 31 continues outputting a High level initialization control signal.

Effect of the Invention

(47) In this embodiment of the invention the initialization circuit 30 does not output a Low level initialization control signal after a battery is installed until the oscillator circuit 11 operates the clock signal is output. The initialization process of internal circuits can therefore execute and the internal circuits can be set to the time display mode even if chattering occurs when a battery is installed and the signal level of the test control signal changes repeatedly.

(48) As a result, the reliability of an electronic timepiece 1 in which the displayed time is controlled by internal circuits can be improved.

(49) Furthermore, because the internal circuits do not operate improperly due to not being initialized, current consumption increasing and the battery life shortening due to incorrect circuit operation can be suppressed.

(50) Furthermore, because the capacitor C2 is not charged before the battery is installed, the initialization circuit 30 can reliably output a Low level initialization control signal when a battery is installed.

(51) In addition, the initialization circuit 30 can be embodied by a simple circuit using capacitors C1 and C2.

(52) This embodiment of the invention can also reduce current consumption in the test mode as the capacity of the constant-current source used as the initialization state holding circuit 16 decreases.

Other Embodiments

(53) The invention is not limited to the embodiments described above, and can be modified and improved in many ways without departing from the scope of the accompanying claims.

(54) Because the length of the initialization process increases in the embodiment described above, a delay circuit 50 that delays the initialization control signal may be disposed after the initialization circuit 30 as shown in FIG. 6.

(55) A circuit having S-R latches connected in multiple stages can be used for the delay circuit 50. As shown in FIG. 7, the delay circuit 50 in this case comprises NAND gates 51, 52, and NOR gates 53, 54. The initialization control signal and the output signal from NAND gate 52 are input to NAND gate 51. The clock signal and output signal from NAND gate 51 are input to NAND gate 52. The output signal of the NAND gate 51 and output signal from NOR gate 54 are input to NOR gate 53, and the output signal is output from the output terminal 55. The clock signal and the output signal from the NOR gate 53 are input to NOR gate 54.

(56) When a Low level initialization control signal is input, this delay circuit 50 always outputs a Low level signal. When a High level initialization control signal is input and the clock signal is not input, the delay circuit 50 continues outputting a Low level initialization control signal. When the clock signal is then input, the delay circuit 50 outputs a High level signal. As a result, the High level initialization control signal can be delayed for one period of the clock signal.

(57) By using this delay circuit 50, as shown in FIG. 8, a Low level signal is output from the delay circuit 50 at time T3 when the initialization circuit 30 outputs a High level initialization control signal. At time T3A when the clock signal changes from High to Low level, a High level signal is output from the delay circuit 50. The time delay of the delay circuit 50 can be changed according to the number of S-R latches.

(58) Because this configuration can increase the duration of the initialization process, the internal circuits can be reliably initialized even when chattering lasts for a long time. Furthermore, because there is no need to change the configuration of the initialization circuit 30 and initialization control circuit 20A, the duration of the initialization process can be increased by a small scale design change.

(59) An operation input control circuit 17 that does not input an operating signal to the test control circuit 15 if the crown 8 is operated when a Low level initialization control signal is output to the IC device 10A, but inputs the operating signal to the test control circuit 15 if the crown 8 is operated when a High level initialization control signal is output to the IC device 10A, may be disposed to the embodiments described above.

(60) FIG. 9 shows an example of this embodiment having an operation input control circuit 17. As shown in FIG. 9, the operation input control circuit 17 is embodied by an AND gate, has one input terminal connected to the operation input terminal P1, and the initialization control signal is input to the other input terminal.

(61) Thus comprised, when the internal circuits are initialized, an operating signal is not input to the test control circuit 15. More specifically, the operating signal can be masked so that the operating signal is not input to the test control circuit 15. As a result, setting the test mode while the frequency divider 12 and pulse shaping filter 13 are executing the initialization process can be avoided when the crown 8 is not intentionally operated to set the test mode (by pulling the crown 8 out to the first stop, for example). As a result, the initialization process of the circuits 12 to 14 can be appropriately executed.

(62) Furthermore, because the operating signal is input to the test control circuit 15 when the initialization process is not executing, the test control signal setting the test mode can be output from the test control circuit 15 by operating the crown 8 to set the test mode, and the frequency divider 12 and pulse shaping filter 13 can be set to the test mode.

(63) This embodiment may also be configured to not input the operating signal of the button 9 to the test control circuit 15 or mode setting circuit that sets the stopwatch mode, alarm mode, or other mode while the internal circuits are being initialized. In other words, a mask circuit that does not input the operating signal from the button 9 to the mode setting circuits while the Low level initialization control signal is being output, and inputs the operating signal from the button 9 to the mode setting circuits while a High level initialization control signal is being output, may also be disposed to the IC device.

(64) Thus comprised, setting the internal circuits to an operating mode while the initialization process is executing can be avoided if the button 9 is unintentionally operated to set a particular mode while the internal circuits are being initialized. As a result, the internal circuit initialization process can be appropriately executed.

(65) The input control circuit 40 is embodied by a clocked inverter in the foregoing embodiments, but the invention is not so limited. For example, the input control circuit 40 may be configured with an n-channel field effect transistor. In this configuration, the transistor is connected between the test control circuit 15 and initialization control circuit 20A, the initialization control signal is input to the gate electrode, and a NOT gate is disposed after the transistor.

(66) The input control circuit 40 may also be configured with a p-channel field effect transistor. In this configuration, the transistor is connected between the test control circuit 15 and initialization control circuit 20A, the initialization control signal is input inverted to the gate electrode, and a NOT gate is disposed after the transistor.

(67) The initialization state holding circuit 16 is embodied by a constant-current source in the foregoing embodiments, but the invention is not so limited. For example, the initialization state holding circuit 16 may be configured by pull-up resistors or pull-down resistors. However, a constant-current source is preferable because deviation in the signal level of the initialization state hold signal due to variation in resistance is low.

(68) In the foregoing embodiments the initialization circuit 30 outputs a Low level signal as the first level signal for initializing the internal circuits, and outputs a High level signal as the second level signal to cancel initialization, but the invention is not so limited. More specifically, a High level signal may be output as the first level signal, and a Low level signal output as the second level signal.

(69) A circuit having capacitors C1 and C2 is used as the initialization circuit 30 in the foregoing embodiments, but the invention is not so limited. More specifically, the initialization circuit 30 may be any circuit design that outputs an initialization control signal of a first level when a battery is installed, and outputs an initialization control signal of a second level when a clock signal is input.

(70) The function control circuit in the foregoing embodiments is a test control circuit 15 that controls the test mode, but the invention is not so limited. More specifically, the function control circuit may be any circuit design that controls a stopwatch function, alarm function or other function than the test mode.

(71) The display device of the electronic timepiece 1 in the foregoing embodiments is embodied by hands 5 to 7 and a dial 3, but the invention is not so limited. For example, the display device may be embodied by an LCD panel or other digital display device.

(72) The invention is also not limited to use in electronic timepieces, and may be broadly applied to wrist-word devices, cell phones, and other electronic devices that display time.

(73) The invention being thus described, it will be obvious that it may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

(74) The entire disclosure of Japanese Patent Application No. 2017-058223, filed Mar. 23, 2017 is expressly incorporated by reference herein.