Flexible silicon infrared emitter

Abstract

An apparatus includes a flexible silicon (Si) substrate, such as a crystalline n-type substrate, and a heterostructure structure formed on the silicon substrate. The heterojunction structure includes a first layered structured deposited on a first side of the silicon substrate. The first layered structured includes a first amorphous intrinsic silicon layer, an amorphous n-type or p-type silicon layer, and a transparent conductive layer. The second layered structure includes a second amorphous intrinsic silicon layer, an amorphous p-type or n-type silicon layer, and a transparent conductive layer. The heterostructure structure is configured to operate as a photovoltaic cell and an infrared light emitting diode.

Claims

1. A method of forming a photovoltaic cell and a light emitting diode apparatus, the method comprising: growing a flexible crystalline silicon substrate; depositing a first layered structure on a first side of the flexible crystalline silicon substrate, the first layered structure including a first passivation layer, a first amorphous silicon layer doped as one of n-type or p-type, and a first transparent conductive layer; treating a portion of the first passivation layer with a first hydrogen plasma treatment before depositing the first amorphous silicon layer and the first transparent conductive layer of the first layered structure on the flexible crystalline silicon substrate; depositing a second layered structure on a second side of the flexible crystalline silicon substrate, the second layered structure including a second passivation layer, a second amorphous silicon layer doped as one of n-type or p-type, wherein the second amorphous silicon layer is doped to be an opposite type as the first amorphous silicon layer, and a second transparent conductive layer, the first layered structure and the second layered structure together forming a heterostructure on the flexible crystalline silicon substrate; treating a portion of the second passivation layer with a second hydrogen plasma treatment before depositing the second amorphous silicon layer and the second transparent conductive layer of the second layered structure on the flexible crystalline silicon substrate; and applying metallization to the apparatus for conducting electricity.

2. The method of claim 1, wherein growing the flexible crystalline silicon substrate comprises growing the flexible crystalline substrate as a p-doped or n-doped substrate.

3. The method according to claim 1, wherein growing the flexible crystalline silicon substrate comprises: growing a first silicon substrate to a first thickness larger than 100 micrometers; and reducing, through wet alkaline etching and chemical washes, the first silicon substrate to a second thickness of between a few micrometers and 100 micrometers to produce the flexible crystalline silicon substrate.

4. The method according to claim 1, wherein applying the metallization comprises: screen printing a first layer of silver over the first side of the flexible crystalline substrate in a grid pattern; and sputter depositing a second layer of conductive metal plating over the second side of the flexible crystalline substrate.

5. The method according to claim 1, wherein applying the metallization comprises: copper plating the first side of the flexible crystalline substrate; and sputter depositing a conductive metal reflector over the second side of the flexible crystalline substrate.

6. The method of claim 1, further comprising: depositing the first passivation layer by: depositing a first intrinsic amorphous silicon layer before the first hydrogen plasma treatment; depositing a second intrinsic amorphous silicon layer after the first hydrogen plasma treatment.

7. The method of claim 6, wherein the second intrinsic amorphous silicon layer is thicker than the first intrinsic amorphous silicon layer.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a cross-sectional diagrammatic view of an example layer structure of flexible infrared emitter according to the present disclosure;

(2) FIG. 2 is a cross-sectional diagrammatic view of another example layer structure of flexible infrared emitter according to the present disclosure;

(3) FIG. 3 is a side view schematic of solar cells connected in series, in accordance with the present disclosure; and

(4) FIG. 4 is a top view of FIG. 3 showing solar cells connected in series, in accordance with the present disclosure.

DETAILED DESCRIPTION

(5) Typically solar cells are rated by their open circuit voltage (V.sub.oc), or the maximum available voltage from a particular solar cell. The open circuit voltage depends, in a general sense, on the carrier concentration within the semiconducting material. Higher open circuit voltages are indicative of a solar cell's ability to generate electric power, and is important for a solar cell's efficiency and performance. The open-circuit voltage varies greatly across different materials due to the wide range of energy bandgaps. For comparing the open-circuit voltage of experimental devices made with different materials, a measure that quantifies the quality of the device is the band gap-open voltage offset (W.sub.oc), where a lower W.sub.oc indicates better device quality. The upper limit of open-circuit voltage is dependent on carrier recombination for a given solar cell, which can vary by material and manufacturing choices.

(6) The invention described herein is a thin crystalline silicon semiconductor that operates as a solar cell with high open circuit voltages. Due to the thin structure of the crystalline silicon wafers comprising the cells, they are highly flexible modules that can be operated in a bent position without losing efficiency, generating power from absorbed photons from the sun. The silicon based semiconductive cells are also capable of operating as LEDs when a current is applied, creating a novel hybrid silicon solar cell/light emitter that is highly transportable and flexible. The specific material structure and methods of manufacture of the device enable high open-circuit voltages by operating the cell near the intrinsic limits of carrier recombination.

(7) At the outer surfaces of a semiconductor where the crystal lattice ends, the outermost atoms are not bound on all sides and therefore have unpaired outer shell electrons. The unpaired shells of the atoms on the edge of the surface introduce energy bands in the semiconductor bandgap between the conductive and valence bands of the other atoms in the lattice. These additional energy bands at the edges of the semiconductor create additional recombination sites through a process of surface recombination. As semiconductor wafers become thinner, the effects of surface recombination become more pronounced as surface recombination sites become a larger percentage of the recombination sites in the semiconductor.

(8) Auger recombination is another recombination process that can occur. The difference in crystal momentum between energy bands in indirect bandgap materials means that spontaneous emission of a photon through radiative recombination is less common. In these materials, Auger recombination is the dominant method of recombination, where energy released when an electron drops from the conduction band to the valence band is transferred to a third carrier particle. Thus indirect bandgap materials, such as crystalline silicon, germanium, and gallium-phosphide are limited by Auger recombination rather than radiative recombination, typically making them inappropriate choices for LED devices.

(9) In order to achieve high-voltage solar cells, thinner wafers are required, as the V.sub.oc increases as function of the excess carrier density. In order to achieve high open-circuit voltages in thin solar cells near the Auger and radiative recombination limits, reducing the amount of surface recombination is essential. Surface passivation is a process by where the outer surface of a semiconductor may be treated with a material that forms an outer shield and inhibiting surface recombination effects by reducing the number of interface states.

(10) Silicon heterostructure (SHS) solar cell architecture enables remarkable passivation of crystalline silicon materials. A heterostructure is where two layers of materials with different inherent band gaps interface in a semiconductor. In the invention described herein, high quality passivation is achieved by creating a heterostructure where a shield layer of a protective coating material is applied over the crystalline silicone of the solar cell to prevent excess surface recombination. In a preferred embodiment, hydrogenated amorphous silicon (a-Si:H) may be used as the passivation layer, though other materials such as silicon oxide, aluminum oxide, titanium dioxide, silicon carbide, or other suitable choice may be used. Hydrogenated amorphous silicon acts as a buffer layer that separates an area of photon absorption in the semiconductor from highly recombination-active surface areas. Surface passivation is particularly relevant for thinner wafers where recombination at the surface dominates total recombination. In order to achieve higher voltages, improvements in surface passivation and wafer thicknesses are necessary.

(11) Additional layers on the photovoltaic cell/light emitter include transparent conducting oxides (TCOs). These layers are comprised of optically transparent, electrically conductive oxide compositions. These optoelectronic materials serve two main purposes. The first is to improve the lateral movement of charge carriers through the passivation layers. To capture the current that is generated by a photovoltaic cell, it is typically transferred to a power storage device such as a power grid or battery through metal contacts attached to the cell. A TCO layer improves the mobility of the charge carriers and improves the efficiency of the cell, while remaining optically transparent so photon may pay through. The other purpose of a TCO is to improve the amount of absorption that occurs in the underlying silicon layer. TCOs have been used in other arts as an anti-reflective coating, and in the present invention serves to enable more light to be absorbed by the underlying layers by decreasing the reflectivity of silicon.

(12) The result of silicon solar cells fabricated with SHS structures and designed to optimize surface passivation and charge carrier mobility is a thin module capable of high V.sub.oc. The thin structure of preferred embodiments disclosed herein enable silicon photovoltaic cells that are flexible without compromising performance. Cells with a thickness in below 100 m range have been shown to exhibit flexible properties, though often suffer from brittleness than can introduce cracks or other mechanical deficiencies over time. In preferred embodiments, the cells are less than 70 micrometers (m) thick and include high quality passivation resulting in greater than 740 millivolts (mV) V.sub.OC. Further, the structures perform with W.sub.OC values below 0.38 mV. To date this is the best W.sub.OC measured with indirect bandgap crystalline silicon, and one of the best after thin-film gallium arsenide (GaAs) structuresa direct bandgap material whose environmental and health safety are questionable. Test structures of thin silicon solar cells demonstrating V.sub.oc of 760 mV and Woc of 0.35 mV have been measured as well. It is further contemplated that passivated silicon wafers as thin as 5-10 m may be used in some embodiments.

(13) Turning now to FIG. 1, a schematic representation of a preferred embodiment of a silicon based device 100 that can be operated as a photovoltaic cell (solar cell) or infrared light emitting diode is depicted. The device 100 includes an n-type crystalline silicon (c-Si) wafer 102 as a substrate which includes a first side 104 and a second side 106. Being an n-type wafer, it is electron carrier biased. The wafer is fabricated using the Czochralski (CZ) or epitaxial process of growing silicon crystals. In an example embodiment, wafers with an initial thickness of 145 m were thinned down to 50 m via alkaline wet etching, followed by wet chemical cleaning. The device 100 includes an SHS solar cell architecture that includes a first layered structure 108 deposited on the first side 104 of the c-Si wafer 102 and a second layered structure 110 deposited on the second 106 of the silicon wafer 102. The first layered structure 108 includes a passivation layer formed by intrinsic (unbiased) hydrogenated amorphous silicon (a-Si:H(i)), though other passivation materials such as silicon oxide, aluminum oxide, silicon carbide, or similar may be used in other embodiments. First layered structure 108 includes a first layer of a-Si:H(i) 112 that forms a SHS with side 104 of the c-Si wafer 102 substrate. In an example embodiment, the SHS was formed using plasma enhanced chemical vapor deposition (PECVD) to grow a 15 nm thick layer of a-Si:H(i), though this may be grown to other thicknesses in other embodiments. The intrinsic layer 112 was grown in three steps: first a thinner intrinsic layer (5 nm) was grown, followed by hydrogen plasma treatment (HPT), and finally a thicker layer of 10 nm was grown on top. The hydrogen plasma treatment process increases the passivation performance of the a-Si:H (i), though may not be necessary in all embodiments. The performance increase when HPT is applied is due to improved carrier lifetime by a diffusion of hydrogen atoms to the interface of the a-Si:H(i) 112 layer and side 104 of c-silicon wafer 102 substrate. This diffusion provides improved chemical passivation due to dangling bond saturation. A thinner intrinsic layer was grown first in order to promote a proper diffusion of the hydrogen to the a-Si:H(i) 112/c-Si-interface 104 interface. A second layer in the first layered structure 108 is a p-doped (hole biased) hydrogenated amorphous silicon layer (a-Si:H (p+)) 114. Exemplary embodiments will have a thickness of 7-10 nm for the p-doped a-Si:H (p+) layer 114. A third layer in the first layered structure 108 is a transparent conductive material layer. In a preferred embodiment, a third layer includes a first indium tin oxide (ITO) layer 116 that is sputter deposited. ITO is an optically transparent, electrically conductive oxide composition that improves mobility of charge carriers from metal contacts 124 to a-Si layers, though one skilled in the arts would understand a number of conductive materials with transparent properties such as indium zinc oxide, hydrogenated indium oxide, zirconium doped indium oxide, zinc oxide, or similar may be used in alternate embodiments. ITO has anti-reflective properties and serves to enable more light to be absorbed by the underlying layers by decreasing the reflectivity of silicon. The front ITO layer 116 is kept thin enough to act as an anti-reflective coating; exemplary embodiments may have a thickness of 80 nm, though the thickness may be optimized for specific wavelengths of light as the reflectivity is wavelength-dependent. The front of the cell is where carriers are generated by light incident on the cell, and that is where most of the absorption should occur by underlying layers. Applying a front transparent conducting layer, such as an ITO layer, improves current generation and improves the efficiency and performance of the cell. The second layered structure 110 includes a first layer of a second passivation material 118, such as a-Si:H (i) in a preferred embodiment depicted in FIG. 1, that is grown on the second side 106 of the silicon wafer 102 substrate in a manner like a-Si:H (i) passivation layer 112. A second layer in the second layered structure 110 is an n-doped hydrogenated amorphous silicon layer (a-Si:H (n+)) 120. A third layer in the second layered structure 110 is a second indium tin oxide (ITO) layer 122 that is sputter deposited. A layer of ITO 122 is on the rear provides improved charge collection as a result of increased carrier mobility, which results in higher V.sub.oc.

(14) To collect the charges from the solar cell, and to connect multiple cells to create a module, metallization of the cell is required. Metallization provides a contact where charge from the photovoltaic functionality can be collected, such as by a battery or electric grid. An energy storage component 130 may be configured to store energy generated by the cell when operated in a first mode that comprises converting light to electric energy, and may be configured to release energy to the cell when operated in a second mode that comprises converting electric energy to emit light. A controller 132 may switch between the first mode and the second mode. The metallization also provides conductive contacts where external current can be applied to cause the cell to emit light as an LED. Screen printing metal is a popular method of metallization when manufacturing solar cells. In example embodiment 100, metallization parameters are different for the front and the rear of the solar cell. Front contacts 124 are silver (Ag) paste screen printed on the surface in a square grid pattern. The rear contact 126 is sputtered Ag giving full coverage of the rear surface, providing large contact surface as well as reflective properties to reflect photons back into the semiconductive silicon layer, improving the efficiency of the photovoltaic functionality. It is noted that a variety of conductive metals may be used in alternate embodiments, such as copper, and that the orientation of the metallization may be changed depending on how the cell may be used. For example, some commercial solar or electric companies have infrastructure supporting bifacial screen printed metallization as depicted in FIG. 1. Other embodiments may be metallized using interdigitized back contact, where all conductive contacts are applied only to the rear of the cell. This may reduce shading losses introduced by the non-transparent metal on the front face of the cell.

(15) Turning now to FIG. 2, an alternate embodiment of a device 200 is depicted. The device 200 includes the same components and symmetrical layers as those of the device 100 of FIG. 1, except that the device 200 is configured in a rear junction configuration. The device 200 includes an SHS comprising a first layered structure 208 on a first side 204 of a silicon wafer substrate 202 (i.e., the side of the substrate 202 that faces front contacts 224). The first layered structure 208 includes: a first passivation layer 212, a-Si:H (i) in this embodiment, that is grown on the first side 204 of the silicon wafer 202 substrate; a a-Si:H (n+) layer 220 deposited over the silicon layer 212; and, a first transparent conductive layer 216 of indium tin oxide (ITO) layer 216 that is sputter deposited over the silicon layer 220. Front contacts 224 of, e.g., silver (Ag) paste are screen printed onto the first layered structure 208. A second layered structure 210 on the second side 206 of the wafer substrate 202 forms a second SHS, and includes: a second passivation layer 218 of a-Si:H (i) that is grown on the second side 206; a a-Si:H (p+) layer 214 positioned over the silicon layer 218; and, a second transparent conductive layer 222 of ITO that is sputter deposited over the silicon layer 214. A rear reflector 226, which may be sputtered Ag, is deposited over the second layered structure 210. Device 200 is configured with the p-doped layer 214 and the n-doped layer 220 reversed, in comparison to the device 100 of FIG. 1, thus placing the junction adjacent the second side 206 of the silicon wafer substrate 202. An energy storage component 230 may be configured to store energy generated by the cell when operated in a first mode that comprises converting light to electric energy, and may be configured to release energy to the cell when operated in a second mode that comprises converting electric energy to emit light. A controller 232 may switch between the first mode and the second mode. The remaining components and layers may remain the same.

(16) It is contemplated that low power hydrogen plasma treatments may be used on the first and second passivation layers (in the example embodiment, intrinsic hydrogenated amorphous silicon layers a-Si:H (i) 112, 118) to improve surface passivation. Further, the second transparent conductive layer is contemplated to be much thicker than the first transparent conductive layer. In the example embodiment, ITO layer 122 is thicker than ITO layer 116. In some embodiments the second transparent conductive layer 122 may be about 280 nanometers (nm) thick. One having ordinary skill in the art will understand that by simply switching the deposition of the thicker second transparent conductive ITO layer 122 and rear reflector 126 with the first transparent conductive ITO layer 116 and front contacts 124, the device 100 is converted to the device 200.

(17) Further, one having ordinary skill in the art would understand how the structures depicted in FIGS. 1 and 2 may be scaled up in size to form a large area solar cell that can also function as a light emitting diode. Further, the flexibility of the device can be determined by the thickness of the silicon wafer 102 substrate. Due to the symmetry of devices 100 and 200 they exhibit similar electrical performance with either the a-Si:H (n+) or a-Si:H (p+) layer on the front of the cell. This enables the cells to be connected in series in a front-to-front and back-to-back orientation to form larger module. FIG. 3 depicts a schematic of side view of an example embodiment of these connections. Four SHS solar cell/light emitters 301 are connected in series. Each cell 301 has n-type 311 and p-type 309 layers, and cells are connected adjacently with every other cell flipped over, so alternating n-type and p-type layers face the front 313. In this example embodiment, indium coated wires 307 connect the metalized contacts on the front face of each cell. In other embodiments, metallic ribbons may be soldered or adhesively applied to metal contacts on each cell to connect them in series, or other similar methods of conductively connecting cells together. Rear connection 303 connects the back of adjacent cells in series connection. FIG. 4 is a top view of the connection scheme depicted in the FIG. 3, looking at the front face 313 from above. Here SHS cells with n-type layer 401 facing front are connected to adjacent cells with p-type layer 403 facing front. Indium coated wired 405 are used to connect the metal contacts on the front face of each cell, and rear connection 407 connects the back of each adjacent cell. The alternating cells enables more reliable and easier assembly of the devices. Additionally, it reduces the stress on the cells when they are mechanically flexed.

(18) Silicon solar cells were fabricated to form devices on a silicon wafer substrates that are between 40 and 75 micrometers thick. Specifically, optimal flexibility was observed when wafers were less than 70 micrometers thick. Such thin cells was possible through high quality passivation layers and the SHS structure. The thin silicon wafers make it possible to push the open-circuit voltages near the Auger and surface recombination limits; the solar cells as fabricated have V.sub.oc between 730 mV and 750 mV, and efficiencies greater than eighteen percent (>18%). The best LEDs are typically constructed from direct bandgap materials like gallium arsenide, and indirect bandgap materials are typically reserved for other semiconductor applications. The outer limits of other forms of recombination generally limit the radiative recombination possible in indirect bandgap materials. Because of the operating characteristics of the current device, these solar cells are near the out limits of these other recombination processes, and are able to exhibit radiative emission in the infrared spectrum and can function as large area light emitting diodes, a novel device using an indirect bandgap material like silicon. When current is applied to the metal contacts on the photovoltaic cell, photons are emitted through radiative emission. Operation of the current photovoltaic cell as an LED is controlled by the application of electric current; when current is applied light is emitted, and ceases when current is removed. The intensity of the emitted light is proportional to the current amplitude. By changing the applied current the intensity of light can be altered without the need to fully turn off the light, and the cell responds very quickly to current changes. This enables the cell to be used for Morse code or as a flashing rescue beacon, for example.

(19) In an example embodiment, a solar cell approximately 153 cm.sup.2 was able to emit light that was detected at over 40 meters, though it is to be understood by those skilled in the arts that this size and range can be scaled in size. The cell was operated in the flexed position without compromising performance, indicating the flexible nature of the device. At the thickness of 70 m, the radius of curvature was a significant fraction (approximately one-half or more) of the length of the device.

(20) It is contemplated that this technology has numerous applications in communications, illumination, and with the military. The technology required to create the devices incorporates standard silicon device processing technology that is low cost and scalable with high manufacturing output. The design described herein enables a device that may be scalable between a few square centimeters up to several square meters in size. The LED technology enables LEDs with large areas without significant effort or changes to processing. The LED in this example has an emission predominantly between 1100 and 1200 nm at room temperature (300K), an LED that is flexible and also operates as a solar cell is produced that may have significant industrial applications. One non-limiting embodiment may include an IR LED that can be located remotely and does not need a separate component to charge batteries, thus saving cost and device complications.

(21) This invention demonstrates bandgap-voltage offsets in crystalline silicon devices comparable with the best reported for direct bandgap materials such as GaAs and GaInP, which have higher bandgaps and voltages. By utilizing 50 m-thick Czochralski silicon wafers, high quality a-Si surface passivation, and a low surface damage sputtering process it was possible to preserve the initial high minority-carrier lifetime and surpass the hurdle of a 760 mV open-circuit voltage.

(22) Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as illustrative forms of implementing the claims.

(23) One skilled in the art will realize that a virtually unlimited number of variations to the above descriptions are possible, and that the examples and the accompanying figures are merely to illustrate one or more examples of implementations.

(24) It will be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from claimed subject matter. Additionally, many modifications may be made to adapt a particular situation to the teachings of claimed subject matter without departing from the central concept described herein. Therefore, it is intended that claimed subject matter not be limited to the particular embodiments disclosed, but that such claimed subject matter may also include all embodiments falling within the scope of the appended claims, and equivalents thereof.

(25) In the detailed description above, numerous specific details are set forth to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, methods, apparatuses, or systems that would be known by one of ordinary skill have not been described in detail so as not to obscure claimed subject matter.

(26) Reference throughout this specification to one embodiment or an embodiment may mean that a particular feature, structure, or characteristic described in connection with a particular embodiment may be included in at least one embodiment of claimed subject matter. Thus, appearances of the phrase in one embodiment or an embodiment in various places throughout this specification is not necessarily intended to refer to the same embodiment or to any one particular embodiment described. Furthermore, it is to be understood that particular features, structures, or characteristics described may be combined in various ways in one or more embodiments. In general, of course, these and other issues may vary with the particular context of usage. Therefore, the particular context of the description or the usage of these terms may provide helpful guidance regarding inferences to be drawn for that context.