HIGH-GAIN AMPLIFIER BASED ON DUAL-GAIN BOOSTING

Abstract

Provided is a high-gain amplifier based on double-gain boosting including a first gain amplification unit including a first amplifier, a second amplifier, and a an interstage matching network connected between the first amplifier and the second amplifier and performing primary amplification; and a second gain amplification unit connected in parallel with the first gain amplification unit and performing secondary boosting.

Claims

1. A high-gain amplifier based on double-gain boosting, comprising: a first gain amplification unit including a first amplifier, a second amplifier, and a an interstage matching network connected between the first amplifier and the second amplifier and performing primary amplification; and a second gain amplification unit connected in parallel with the first gain amplification unit and performing secondary boosting.

2. The high-gain amplifier of claim 1, wherein the first amplifier and the second amplifier include: a first transmission line; a transistor connected to a rear end of the first transmission line; a second transmission line connected to a rear end of the transistor; and a third transmission line connected to a front end of the first transmission line and a rear end of the second transmission line and connected in parallel with the first transmission line, the transistor, and the second transmission line.

3. The high-gain amplifier of claim 1, wherein the second gain amplification unit includes: a fourth transmission line connected between a front end of the first amplifier and an input terminal; a fifth transmission line connected between a rear end of the second amplifier and an output terminal; and a sixth transmission line connected between a front end of the fourth transmission line and a rear end of the fifth transmission line.

4. The high-gain amplifier of claim 1, further comprising: a second matching unit connected to a rear end of the second amplifier; and a third amplifier connected between a rear end of the second matching unit and the second gain amplification unit.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0011] FIG. 1 is a diagram illustrating a high-gain amplifier based on double-gain boosting according to an embodiment of the present invention.

[0012] FIG. 2 is a schematic of n-stage cascaded Gmax cores with matching networks.

[0013] FIG. 3a, FIG. 3b, FIG. 3c and FIG. 3d are design procedure of two-stage double-Gmax core.

[0014] FIG. 4 is final general structure of the proposed two-stage double-Gmax core.

[0015] FIG. 5 is behavior of Gmax cas 2 as a function of ks and _s, from (17) and (18), in comparison with Gmax_tr2.

[0016] FIG. 6a and FIG. 6b is design of a single-transistor Gmax core with three passive elements.

[0017] FIG. 7a and FIG. 7b is design of single-transistor Gmax core considering the size of series connected transmission line TLISML for the interstage matching.

[0018] FIG. 8 is simulated Gma_s, ks and θs of the single-transistor Gmax core as a function of frequency.

[0019] FIG. 9a, FIG. 9b and FIG. 9c is cascade of two single-transistor Gmax cores.

[0020] FIG. 10a and FIG. 10b shows the design of double-G.sub.max core which is implemented with three passive elements as in single-transistor Gmax core.

[0021] FIG. 11 is reactance of TL6 as a function of physical length in degree.

[0022] FIG. 12a, FIG. 12b and FIG. 12c is Proposed 250 GHz two-stage double-Gmax core.

[0023] FIG. 13 shows the circuit schematics of the 250 GHz amplifier that adopts the double-Gmax core by adding the input and output matching networks.

DETAILED DESCRIPTION

[0024] Hereinafter, detailed contents for embodying the present invention will be described in detail with reference to the accompanying drawings.

[0025] FIG. 1 is a diagram illustrating a high-gain amplifier based on double-gain boosting according to an embodiment of the present invention.

[0026] Referring to FIG. 1, a high-gain amplification unit 100 based on double-gain boosting includes a first gain amplification unit 110 and a second gain amplification unit 120.

[0027] The first gain amplification unit 110 includes a first amplifier 111, a second amplifier 112, and an interstage matching network 113.

[0028] Each of the first and second amplifiers 111 and 112 includes a first transmission line Z1, a transistor M1, a second transmission line Z2, and a third transmission line Z3.

[0029] The first transmission line Z1 is connected to an input terminal, and may have a first reactance value capable of obtaining a maximum achievable gain at a set first frequency and a second reactance value capable of obtaining a maximum achievable gain at a second frequency.

[0030] The transistor 120 may be connected to a rear end of the first transmission line Z1.

[0031] The second transmission line Z2 is connected to a rear end and an output terminal of the transistor, and may have a third reactance value capable of obtaining a maximum achievable gain at a set first frequency and a fourth reactance value capable of obtaining a maximum achievable gain at a second frequency.

[0032] The third transmission line Z3 may be connected between the input terminal and the output terminal.

[0033] The third transmission line Z3 may be connected in parallel with the first transmission line Z1, the transistor 120, and the second transmission line Z2.

[0034] The third transmission line 140 is connected to an input terminal, and may have a fifth reactance value capable of obtaining a maximum achievable gain at set first frequency and a sixth reactance value capable of obtaining a maximum achievable gain at a second frequency.

[0035] The interstage matching network 113 may be connected between the first amplifier 111 and the second amplifier 112, and match both amplifiers.

[0036] The second gain amplification unit 120 is connected in parallel with the first gain amplification unit 110 and may perform secondary amplification.

[0037] The second gain amplification unit 120 may include a fourth transmission line Z4 connected between a front end of the first amplifier 111 and an input terminal, a fifth transmission line Z5 connected between a rear end of the second amplifier 112 and an output terminal, and a sixth transmission line Z6 connected between a front end Z4 of the fourth transmission line Z4 and a rear end Z5 of the fifth transmission line.

[0038] In addition, the high-gain amplifier 100 based on double-gain boosting may further include a second matching unit (not illustrated) connected to the rear end of the second amplifier 112, and a third amplifier (not illustrated) connected between the rear end of the second matching unit (not illustrated) and the second gain amplification unit. In this way, in the high-gain amplifier 100 based on double-gain boosting, N amplifiers and matching units may be arranged in cascade, and N may be variously selected according to circumstance.

[0039] FIG. 2 is a schematic of n-stage cascaded Gmax cores with matching networks.

[0040] Referring to FIG. 2, FIG. 2 shows the schematic of n-stage cascaded Gmax cores with matching networks, where all the transistors are identical and embedded into a linear, lossless, reciprocal (LLR) networks to achieve Gmax at the target frequency, that is, the transfer parameter ratio (As) of each Gmax core is given by [18], [21], [31]

[00001]$\begin{array}{cc}{A}_s=\frac{Y_{21s}}{Y_{{12}_s}}=-G_{\mathrm{max\_tr}},& \left(1\right)\end{array}$$\begin{array}{cc}{\theta }_2=\mathrm{phase}\left(A_z\right)=\pi & \left(2\right)\end{array}$$\begin{array}{cc}{k}_s=1.& \left(3\right)\end{array}$

[0041] In FIG. 2, Ys, Ycas_n, ks, kcas_n, .sup.θs, and .sup.θcas n represent Y-parameter, Rollet stability factor, and the phase of A for the Gmax core and the n-stage cascaded Gmax cores, respectively, and Gmax_tr represents the Gmax value of a transistor. Assuming that all passive components for the embedding and interstage matching networks are linear, lossless and reciprocal, Acas_n, .sup.θcas_n, and kcas_n of the n-stage Gmax cores are given by

[00002]$\begin{array}{cc}{A}_{\mathrm{ces}\_n}=\frac{Y_{21\mathrm{cas}\_n}}{Y_{12\mathrm{cas}\_n}}={\left(\frac{Y_{21s}}{Y_{12s}}\right)}^n={\left(-G_{\mathrm{max\_tr}}\right)}^n={\left(-1\right)}^n\times G_{\mathrm{max\_tr}}^n& \left(4\right)\end{array}$$\begin{array}{cc}{\theta }_{\mathrm{cas}\_n}={\theta }_s\times n=\pi \times n& \left(5\right)\end{array}$$\begin{array}{cc}{k}_{\mathrm{cas}\_n}=1.& \left(6\right)\end{array}$

[0042] respectively. By substituting Acas_n, kcas_n, and .sup.θcas_n into Gma and U equation [21], the maximum available gain

[0043] (Gma_cas_n) and unilateral gain (Ucas_n) of the n-stage cascaded Gmax cores can be given by

[00003]$\begin{array}{cc}{G}_{\mathrm{ma}\_\mathrm{cas}\_n}={.Math.\frac{Y_{21s}}{Y_{12s}}.Math.}^n{\left(k_s-\sqrt{k_z^2-1}\right)}^n={.Math.-G_{\mathrm{max\_tr}}.Math.}^n=G_{\mathrm{max\_tr}}^n,& \left(7\right)\end{array}$$\begin{array}{cc}{U}_{\mathrm{cas}\_n}=\frac{{.Math.A_{\mathrm{cas}\_n}-1.Math.}^2}{2k_{\mathrm{cas}\_n}.Math.A_{\mathrm{cas}\_n}.Math.-2\mathrm{Re}\left(A_{\mathrm{cas}\_n}\right)}=\frac{A_{\mathrm{cas}\_n}^2-2A_{{\mathrm{cas}}_n}+1}{2k_{\mathrm{cas}\_n}.Math.A_{\mathrm{cas}\_n}.Math.-2.Math.A_{\mathrm{cas}\_n}.Math.\cos \left({\theta }_{\mathrm{cas}\_n}\right)}& \left(8\right)\end{array}$

[0044] which leads to the maximum achievable gain (Gmax_cas_n) of the n-stage cascaded Gmax cores given by

G.sub.max_cas_n=(2U.sub.cas.sub.n−1)+2√{square root over (U.sub.cas_n(U.sub.cas_n−1))}.  (9)

[0045] Note that, as can be seen in (7), the overall gain of n-stage cascaded Gmax cores, Gma_cas_n, is limited to Gmax trn. To achieve Ucas_n and Gmax_cas_n, additional embedding networks have to be applied to the n-stage cascaded Gmax cores. As follows, the characteristics of Ucas_n and Gmax_cas_n show uniquely different behavior depends on whether the numbers of stages are odd or even.

[0046] In the case of odd number of cascaded Gmax cores, Ucas_n is given by

[00004]$\begin{array}{cc}{U}_{\mathrm{cas}\_n}=\frac{{.Math.-G_{\mathrm{max\_tr}}^n-1.Math.}^2}{2k_{\mathrm{cas}\_n}.Math.-G_{\mathrm{max\_tr}}^n.Math.-2\mathrm{Re}\left(-G_{\mathrm{max\_tr}}^n\right)}=\frac{G_{\mathrm{max\_tr}}^{2n}+2G_{\mathrm{max\_tr}}^n+1}{4G_{\mathrm{max\_tr}}^n}.& \left(10\right)\end{array}$

[0047] By substituting (10) into (9), Gmax_cas_n is given by

G.sub.max_cas_n=G.sub.max_tr.sup.n.  (11)

[0048] From (11), maximum achievable gain which is applied to an odd number of cascaded Gmax cores (Gmax_cas_n) is the same as the maximum available gain of the cascaded Gmax cores (Gmax_trn) as in (7). This means that the gain higher than Gmax trn cannot be achieved even with additional embedding network for Gmax, that is, double-Gmax.

[0049] However, in the case of even number of cascaded Gmax cores, Ucas_n is given by

[00005]$\begin{array}{cc}{U}_{\mathrm{cas}\_n}=\frac{{.Math.G_{\mathrm{max\_tr}}^n-1.Math.}^2}{2k_{\mathrm{cas}\_n}.Math.G_{\mathrm{max\_tr}}^n.Math.-2\mathrm{Re}\left(G_{\mathrm{max\_tr}}^n\right)}=\frac{G_{\mathrm{max\_tr}}^{2n}-2G_{\mathrm{max\_tr}}^n+1}{2\times 1\times G_{\mathrm{max\_tr}}^n-2G_{\mathrm{max\_tr}}^n}=\infty .& \left(12\right)\end{array}$

[0050] which leads to

G.sub.max_cas_n=∞.  (13)

[0051] As can be seen in (12) and (13), in principle, the unilateral (Ucas_n) and maximum achievable (Gmax_cas_n) gains,

[0052] implemented with an even number of cascaded Gmax cores can approach infinity. Note that, (12) and (13) are valid at fo<fmax since the Gmax of the single transistor is defined at fo<fmax.

[0053] Even though both Ucas_n and Gmax_cas_n in (12) and (13) can approach infinity at the target frequencies, Gmax_cas_n is

[0054] more realistic to be adopted for the amplifier design since achieving zero reverse gain for Ucas_n at high operating frequencies is not practical mainly due to the substrate coupling. The implementation of Gmax_cas_n is much easier and straightforward. It is to be noted, however, that (12) and (13) represents, by definition, the boundary condition for oscillation. However, the oscillation can be easily avoided by adjusting .sup.θcas_n while satisfying the unconditional stability. Therefore, by adopting the double-Gmax core, the amplifier can achieve much higher gain per stage than Gmax_tr with unconditional stability.

[0055] FIG. 3a, FIG. 3b, FIG. 3c and FIG. 3d are design procedure of two-stage double-Gmax core. Transistor, single-transistor Gmax core, cascade of two single-transistor Gmax cores, and double-Gmax core.

[0056] Referring to FIG. 3a, FIG. 3b, FIG. 3c and FIG. 3d, any even number of cascaded Gmax cores can satisfy (12) and (13), but a cascade of two single-transistor Gmax cores is chosen for the implementation of high gain amplifier as it requires minimum chip area and dc power consumption.

[0057] A step-by-step procedure which leads to double-Gmax core where all the passive components are assumed linear, lossless and reciprocal. In FIG. 3a, the characteristic of the transistor is represented by A.sub.tr, k.sub.tr, θ.sub.tr, G.sub.ma_tr/G.sub.ms_tr and G.sub.max_tr. The transistor are satisfied the condition G.sub.ma_tr/G.sub.ms_tr<G.sub.max_tr G.sub.max is equal to G.sub.max_tr

A.sub.tr

K.sub.tr,θ.sub.tr

G.sub.ma_tr/G.sub.ms_tr<G.sub.max_tr

G.sub.max=G.sub.max_tr

[0058] The single-transistor Gmax core can be realized by embedding the transistor into an LLR network, as shown in FIG. 3b, that satisfies the condition A.sub.s=−G.sub.max_tr, ks=1, θs=π, such that G.sub.ma_s=G.sub.max_tr. Due to the linear, lossless, and reciprocal nature of the embedding network, the Mason's Invariant Us of the single-transistor G.sub.max core is the same as that of the transistor, U.sub.tr. Hence, the G.sub.max of the single-transistor G.sub.max core is the same as G.sub.max_tr since G.sub.max_tr is only a function of Utr as in (9).

A.sub.s=−G.sub.max_tr

k.sub.s=1,θ.sub.s=π

G.sub.ma_s=G.sub.max_tr

G.sub.max=G.sub.max_s=G.sub.max_tr

[0059] For a cascade of two single-transistor Gmax cores with interstage matching network, shown in FIG. 3c, A_.sub.cas_2 is equal to G.sub.max_tr.sup.2, G.sub.ma_cas_2 is equal to G.sub.max_tr.sup.2, k.sub.cas_2=1, θ.sub.cas_2=2 π and G.sub.max, i.e., G.sub.max_cas_2 approaches 1 following (12) and (13), G.sub.max is equal to G.sub.max_cas_2, G.sub.max approaches infinity.

A.sub.cas_2=G.sub.max_tr.sup.2

k.sub.cas_2=1,θ.sub.cas_2=2π

G.sub.ma_cas_2=G.sub.max_tr.sup.2

G.sub.max=G.sub.max_cas_2=∞

[0060] FIG. 3d shows the schematic of the double-G.sub.max core where an additional LLR is adopted onto the cascade of two single-transistor G.sub.max cores and satisfies the condition of A.sub.d=−G.sub.max_cas_2, k.sub.d=1, θd=π, i.e., the values of k.sub.d and θ.sub.d of double-G.sub.max core are 1 and, respectively, such that the gain (G.sub.ma_d) approaches infinity.

[0061] FIG. 4 is final general structure of the proposed two-stage double-Gmax core.

[0062] Reffering to FIG. 4, the final general structure of the proposed two-stage double-G.sub.max core. The reactive components Z.sub.1, Z.sub.2 and Z.sub.3 are for the single-transistor G.sub.max core, and Z.sub.4, Z.sub.5 and Z.sub.6 are for the implementation of G.sub.max onto the cascade of two single-transistor G.sub.max cores.

[0063] The gain of double-G.sub.max core can be controlled by varying the values of k.sub.s and θ.sub.s. This section describes the behaviors of double-G.sub.max core as a function of k.sub.s and θ.sub.s.

[0064] For the cascade of two single-transistor G.sub.max cores shown in FIG. 3c, the k.sub.cas 2 and θ.sub.cas 2 can be given by

k.sub.cas_2=2k.sub.s.sup.2−1.  (14)

and

θ.sub.cas_2=2θ.sub.2  (15)

[0065] which become equal to 1 and 2π, respectively, when k.sub.s=1 and θ.sub.s=π. The derivation details of (14) is shown in Appendix A. Then, from (4) and the expression for G.sub.ma in [21], A.sub.cas_2 can be given by

[00006]$\begin{array}{cc}{A}_{\mathrm{ces}\_n}=\frac{Y_{21\mathrm{cas}\_n}}{Y_{12\mathrm{cas}\_n}}={\left(\frac{Y_{21s}}{Y_{12s}}\right)}^n={\left(\frac{G_{\mathrm{max\_tr}}}{k_s-\sqrt{k_s^2-1}}\right)}^2.& \left(16\right)\end{array}$

[0066] Substituting (14), (15) and (16) into the expression for the unilateral gain [21], the unilateral gain for the cascade of two single-transistor G.sub.max cores can be given by

[00007]$\begin{array}{cc}\begin{array}{c}{U}_{\mathrm{cas}\_z}=\frac{{.Math.A_{\mathrm{cas}\_2}-1.Math.}^2}{2k_{\mathrm{cas}\_2}.Math.A_{\mathrm{cas}\_2}.Math.-2\mathrm{Re}\left(A_{\mathrm{cas}\_2}\right)}\\ =\frac{{\left(\frac{G_{\mathrm{ma}s}}{k_s-\sqrt{k_s^2-1}}\right)}^4-2{\left(\frac{G_{{\mathrm{ma}}_s}}{k_s-\sqrt{k_s^2-1}}\right)}^2+1}{\begin{array}{c}\left(4k_z^2-2\right)\\ {\left(\frac{G_{{\mathrm{ma}}_s}}{k_z-\sqrt{k_z^2-1}}\right)}^2-2\end{array}{\left(\frac{G_{{\mathrm{ma}}_s}}{k_s-\sqrt{k_s^2-1}}\right)}^2\cos \left(2{\theta }_s\right)}\end{array}& \left(17\right)\end{array}$

[0067] and the maximum achievable gain of the cascade of two single transistor G.sub.max cores is given by

G.sub.max_cas_2=(2U.sub.cas_2−1)+2√{square root over (U.sub.cas_2(U.sub.cas_2−1))}.  (18)

[0068] FIG. 5 is behavior of Gmax cas 2 as a function of ks and _s, from (17) and (18), in comparison with Gmax_tr2.

[0069] Reffering to FIG. 5, the behavior of G.sub.max_cas_2 as a function of k.sub.s and θ.sub.s, from (17) and (18), in comparison with G.sub.max_tr.sup.2. Only k.sub.s>1 region is shown considering unconditional stability. The plane parallel to ks and θ.sub.s-axis (in pink) represents the theoretical maximum available gain (G.sub.max_tr.sup.2) that can be obtained from a cascade of two single-transistor G.sub.max cores. As can be seen in FIG. 5,

[0070] 1) G.sub.max_cas_2 approaches infinity when k.sub.s=1 and θ.sub.s=π,

[0071] 2) G.sub.max_cas_2 can have much higher values of gain than G.sub.max_tr.sup.2 as k.sub.s and θ.sub.s approach 1 and π, respectively.

[0072] 3) Contrary to the common perception, it is possible to obtain a gain higher than G.sub.max_tr per transistor stage while satisfying the unconditional stability.

[0073] Based on the analysis described in Section III, this section presents a practical implementation example of a 250 GHz two-stage double-G.sub.max core. An n-MOSFET having a channel length of 60 nm and a total width of 12 um with 20 fingers, same as the one in [21], is adopted for the design, which is biased at V.sub.GS=V.sub.DS=1 V with I.sub.DS=10.75 mA. The simulated f.sub.max of the given transistor with optimized layout is 395 GHz, where the interconnect metals and contacts up to the top signal metal line are included in the transistor layout, and G.sub.max_tr at 250 GHz is 9.95 dB.

[0074] FIG. 6a and FIG. 6b is design of a single-transistor Gmax core with three passive elements.

[0075] Reffering to FIG. 6a and FIG. 6b, to design a cascade of two single-transistor G.sub.max cores, a single-transistor G.sub.max core should be designed in advance, which is shown in FIG. 6a and FIG. 6b, where a three passive elements based embedding network is chosen as it allows infinite combinations of embedding network for gain-boosting [18], [21], [22]. In FIG. 5(a), Y.sub.in and Y.sub.out represent input and output admittances of the G.sub.max core, respectively. The single-transistor G.sub.max core is designed in terms of minimizing the chip area and passive component loss as in [18] except that the θ.sub.s value has been shifted to 195° which makes the gain (G.sub.max_cas_2) to be less susceptible to the PVT variations by reducing the gain, considering the sharp increase in G.sub.max_cas_2 at the values of k.sub.s and θ.sub.s's near 1 and π as shown in FIG. 5. The target power gain of the double-G.sub.max core is set to be around 10 dB higher than that of the cascade of two single-transistor G.sub.max cores. The ks of implemented single-transistor G.sub.max core will increase slightly higher than 1 due to the passive component losses even though the design point of ks is set to 1. Under this condition, G.sub.max_cas_2 shows around 10 dB higher gain than that of the cascade of two single-transistor G.sub.max cores (G.sub.max_tr.sup.2) when θ.sub.s=195°. Therefore, k.sub.s=1 and θ.sub.s=195° are chosen as a design point considering both target power gain and abrupt PVT variation. FIG. 5 (b) shows the values of X.sub.3, X.sub.1, Real (Y.sub.in) and Real (Y.sub.out) as a function of X.sub.2 that satisfies k.sub.s=1 and θ.sub.s=195° conditions at 250 GHz. As shown in FIG. 6b, the input (Real (Y.sub.in)) and output (Real (Y.sub.out)) conductances of the single-transistor G.sub.max core vary over the X.sub.1, X.sub.2 and X.sub.3 combinations. Utilizing this property, the loss and chip area of the interstage matching network can be minimized [18] as follows.

[0076] FIG. 7a and FIG. 7b is design of single-transistor Gmax core considering the size of series connected transmission line TLISML for the interstage matching.

[0077] Reffering to FIG. 7a and FIG. 7b, FIG. 6 shows the details of how the values of LLR embedding network for the single-transistor G.sub.max core are determined considering the size of series connected transmission line TL.sub.ISML for the interstage matching. As shown in FIG. 7a, transmission lines (TLs) with characteristic impedance (Z.sub.o) of 50 are used for Z.sub.1, Z.sub.2 and Z.sub.3 and the wavelength (λ) of the TLs at 250 GHz is assumed 653 um. FIG. 7b shows the physical length of the TL.sub.1, TL.sub.3 and TL.sub.ISML as a function of the length of TL.sub.2 that satisfies the G.sub.max condition. Generally, a shorter interstage series matching element is advantageous in terms of the insertion loss [32]. Even though the interstage matching for the real part between the two G.sub.max cores can be achieved by adjusting the value of embedding network without TL.sub.ISML, the adoption of TL.sub.ISML, 30 um as a minimum, not only minimizes the insertion loss of interstage matching network but also helps prevent the unwanted coupling between the two G.sub.max cores as explained in [18], [33].

[0078] FIG. 8 is simulated Gma_s, ks and .sup.θs of the single-transistor Gmax core as a function of frequency.

[0079] Reffering to FIG. 8, The final values of TL.sub.1, TL.sub.2, and TL.sub.2 for the single-transistor G.sub.max core are 24, 18, and 117 um, respectively, which leads to TL.sub.ISML=30 um. FIG. 8 shows the simulated G.sub.ma_s, k.sub.s and θ.sub.s of the single-transistor G.sub.max core as a function of frequency, where their values at 250 GHz are 9.5 dB, 1.02 and 195°, respectively. Due to the loss of embedding network and the offset in θ.sub.s (1950), G.sub.ma_s is slightly reduced from the theoretical value of G.sub.max_tr (9.95 dB).

[0080] FIG. 9a, FIG. 9b and FIG. 9c is cascade of two single-transistor Gmax cores.

[0081] Reffering to FIG. 9a, FIG. 9b and FIG. 9c, The cascade of two single-transistor Gmax cores can be implemented with two single-transistor Gmax cores and the interstage matching network. FIG. 9a, FIG. 9b and FIG. 9c shows the schematic of the cascade of two single-transistor Gmax cores and its simulated kcas_2 and θcas_2, as well as the comparison of Gma_cas_2, Ucas_2 and Gmax_cas_2. In FIG. 9a, the two single-transistor Gmax cores are matched by the 30 um TLISML1 in combination with a shunted TLISML2. As shown in FIG. 9b, the values of kcas_2 and θcas_2 are 1.02 and 30° (=195°+195°), respectively. Note that, the interstage matching network does not affect the kcas 2 since it introduces the same amount of phase shifts in both forward and reverse directions, which compensate each other. The insertion losses of the embedding and interstage matching components lead to kcas_2 slightly higher than 1, which leads to Gma_cas_2, Ucas_2 and Gmax_cas_2 of 17.2, 22.2 and 28.3 dB, respectively, as shown in FIG. 9c.

[0082] FIG. 10a and FIG. 10b shows the design of double-G.sub.max core which is implemented with three passive elements as in single-transistor G.sub.max core. FIG. 10a and FIG. 10b shows the required reactance values of X.sub.6 and X.sub.4 as a function of X.sub.5 at 250 GHz, to meet k.sub.d=1 and θ.sub.d=180′ of G.sub.max. As shown in FIG. 10a and FIG. 10b, the lowest required reactance value of X.sub.6 is chosen for the design considering the limited implementable value caused by minimum metal width and the resulting insertion loss of the TL.sub.6. For the design simplicity, Z.sub.o of 50Ω is adopted for the TLs implementing Z.sub.4, Z.sub.5 and Z.sub.6.

[0083] FIG. 11 is reactance of TL.sub.6 as a function of physical length in degree.

[0084] Reffering to FIG. 11, shows the reactance of TL.sub.6 as a function of physical length in degree. As shown in FIG. 11, the reactance value of TL shows the periodic characteristic since the equivalent TL reactance value is Z.sub.o sin(β1), where β and l represent propagation constant and physical length of TL, respectively. The TL length of 84°, 96°, 444° and 456° meet the required reactance value of j49.7Ω in a one and half period. A long TL length of 444° is adopted for TL.sub.6, even though short line has advantage in terms of loss, to avoid the coupling between the outer and inner passive elements of the G.sub.max cores as well as the convenience of the measurement. A proper amount of spacing is required between the input and output pads of an amplifier for the on-wafer probing, therefore, mandates longer TL length than the minimum required size. The final sizes of TL.sub.4, TL.sub.5, and TL.sub.6 are 35, 92, and 805 um, respectively. If the double-G.sub.max core is implemented as a component of a bigger circuit, more compact layout would be feasible.

[0085] FIG. 12a, FIG. 12b and FIG. 12c is Proposed 250 GHz two-stage double-Gmax core.

[0086] Reffering to FIG. 12a, FIG. 12b and FIG. 12c, shows the final details of the proposed double-G.sub.max core and its simulated maximum available gain in comparison with those of the cascade of two single-transistor G.sub.max cores (G.sub.ma_cas_2) and the theoretical G.sub.max_tr.sup.2, and k-factor and |Δ|=1 S.sub.11S.sub.22-S.sub.12S.sub.21| as a function of frequency. In FIG. 12b, the values of gain for double-G.sub.max core (G.sub.ma_d), G.sub.ma_cas_2 and G.sub.max_tr.sup.2 are 26.5, 16.5 and 20 dB, respectively, at 250 GHz. Note that, G.sub.ma_cas_2 in FIG. 12b is lower than the ideal G.sub.max_tr.sup.2 by 3.5 dB due to the losses of the embedding and matching networks. In FIG. 12b, G.sub.ma_d shows a higher gain than G.sub.ma_cas_2 and G.sub.max_tr.sup.2 by 10 and 6.5 dB, respectively. As shown in FIG. 12c, the double-G.sub.max core shows unconditional stability (k.sub.d>1 and |Δ|<1). The embedding network loss increases the k.sub.d slightly higher than 1, which makes simultaneous conjugate input and output matching networks design possible. The simulated value of k.sub.d is 1.02 at 250 GHz. Due to the losses from TL.sub.4, TL.sub.5, and TL.sub.6, and overall k.sub.d of 1.02, the maximum available gain of double-G.sub.max core (26.5 dB) is lower than G.sub.max_cas_2 (28.3 dB) in FIG. 9c by 1.8 dB.

[0087] FIG. 13 shows the circuit schematics of the 250 GHz amplifier that adopts the double-Gmax core by adding the input and output matching networks.

[0088] Refering to FIG. 13, To demonstrate the feasibility of the proposed double-Gmax gain boosting technique, two-stage 250 GHz amplifiers are designed in a 65 nm CMOS process. FIG. 13 the circuit schematics of the 250 GHz amplifier that adopts the double-Gmax core described in Section IV by adding the input and output matching networks. The input and output admittances of the 250 GHz double-Gmax core for simultaneous conjugate matching were 0.022-j0.024 S and 0.028-j0.027 S, respectively. The input and output real part matching can be achieved by relatively short series TLs as shown in FIG. 13 since the input and output conductances are quite close to 0.02 S (= 1/50). Then, the input and output susceptances can be canceled by using open stub TLs. The simulated insertion losses of the input and output matching networks of the 250 GHz amplifier were 0.9 and 1.5 dB, respectively.

[0089] All or some of the respective exemplary embodiments may be selectively combined with each other so that the above-mentioned exemplary embodiments may be variously modified.

[0090] According to the disclosed invention, gain boosting is primarily performed, and then secondarily performed to obtain a greater gain than the existing maximum achievable gain Gmax.

[0091] In addition, it is to be noted that the exemplary embodiments are provided in order to describe the present invention rather than limiting the present invention. Further, it may be understood by those skilled in the art to which the present invention pertains that various exemplary embodiments are possible without departing from the spirit and scope of the present invention.