Power conversion devices and control methods therefor

Abstract

Power conversion devices with control algorithms that can solve the double frequency harmonic problem are provided, as are techniques for controlling power converters when the instantaneous values of input and output power are not the same.

Claims

1. A power conversion device comprising: input circuitry configured to be coupled to a power source or load, the input circuitry comprising at least one switching device or diode; an output switch bridge configured to be coupled to a load or power source, the output switch bridge comprising at least four controllable switching devices arranged in a bridge configuration to control current output; and a link stage comprising at least one reactive component configured for alternating current (AC) operation, wherein the input circuitry, output switch bridge and link stage are operative to regulate an input and an output currents and manage power mismatch between the power source and load; wherein the device is operative in at least three states in a switching cycle, including at least one state to charge the reactive component of the link stage from the power source, at least one state in which power is discharged from the link stage into the load, and a single state in which no power is transferred through the link stage and one or both of a link voltage remains constant and a link current is zero or remains constant.

2. The power conversion device of claim 1, wherein the device is operative to suppress a double frequency harmonic component at the input circuitry.

3. The device of claim 1, wherein switches in the input circuitry and output switch bridge are operative at a fixed switching frequency.

4. The device of claim 1, wherein the device is operative to control the input current to be about equal to a selected reference value.

5. The device of claim 1, wherein the input circuitry comprises an input switch bridge configured to be coupled to a direct current (DC) power source, the input switch bridge comprising at least one switching device controllable to regulate an input DC current with suppression of a double frequency harmonic component.

6. The device of claim 1, wherein the output switch bridge is configured to be coupled to an AC load, the output switch bridge comprising at least four controllable switching devices arranged in a bridge configuration to control current output to the load.

7. The device of claim 1, wherein the device is operative as a single phase inverter or rectifier.

8. The device of claim 1, wherein the device is operative to regulate the input current and the output current simultaneously.

9. The device of claim 1, wherein the link stage is arranged in series or in parallel with the input circuitry and the output switch bridge.

10. The device of claim 1, wherein the reactive component comprises a film capacitor, a ceramic capacitor, an electrolytic capacitor, or an inductive device.

11. The device of claim 1, wherein the device is operative to provide bidirectional flow of power.

12. The device of claim 1, wherein each of the switching devices of the output switch bridge comprises a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), or a metal-oxide-semiconductor field-effect transistor (MOSFET) with anti-parallel diode; and/or wherein the at least one the switching device of the input circuitry comprises a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), or a metal-oxide-semiconductor field-effect transistor (MOSFET) with anti-parallel diode.

13. The device of claim 1, further comprising circuitry that causes, and/or a controller comprising one or more processors, memory, and machine-readable instructions stored in the memory that, upon execution by the one or more processors, cause the device to carry out operations to control sequence and duration of each of the controllable switching devices.

14. The power conversion device of claim 1, wherein a voltage rating of the switching devices is about equal to a maximum link stage voltage.

15. The power conversion device of claim 1, wherein a maximum voltage of the link stage is selected based on a selected maximum link stage capacitance.

16. The power conversion device of claim 1, wherein the link stage comprises a plurality of capacitors, each capacitor in series with a bidirectional conducting bidirectional blocking controllable switching device, the plurality of capacitors arranged in series or in parallel with the input circuitry and the output switch bridge, and wherein each capacitor transfers power in at least two switching cycles over a load power cycle.

17. The power conversion device of claim 1, wherein the link stage comprises a plurality of series inductors, each inductor in parallel with a forward conducting bidirectional blocking controllable switching device, the plurality of inductors arranged in series or in parallel with the input circuitry and the output switch bridge.

18. A method of controlling a power conversion device, comprising: providing the power conversion device of claim 1; and operating the device to regulate the input and output currents with suppression of a double frequency harmonic component.

19. A method of controlling a power conversion device, comprising: providing the power conversion device of claim 1; and operating the device with a plurality of switching cycles, each switching cycle comprising at least one charging state, at least one discharging state, and at least one state during which no power is transferred.

20. The device of claim 1, wherein the device is operative in order such that the at least discharging state occurs in the switching cycle after the at least one charging state, and the single state in which no power is transferred through the link stage occurs in the switching cycle after the at least one charging state and the at least one discharging state.

Description

DESCRIPTION OF THE DRAWINGS

(1) The invention will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings in which:

(2) FIG. 1 is a circuit diagram of an embodiment of a bidirectional single-phase capacitive link inverter with series link (dcsingle-phase ac);

(3) FIG. 2 is a circuit diagram of an embodiment of a bidirectional single-phase capacitive link inverter with parallel link (dcsingle-phase ac);

(4) FIG. 3 is a circuit diagram of an embodiment of a dc-to-single phase ac capacitive link converter with series link (dc=>single-phase ac);

(5) FIG. 4 is a circuit diagram of an embodiment of a single-phase ac-to-dc capacitive link converter with series link (single-phase ac=>dc);

(6) FIG. 5 is a circuit diagram of an embodiment of a dc-to-single phase ac capacitive link converter with parallel link (dc=>single-phase ac);

(7) FIG. 6 is a circuit diagram of an embodiment of a single-phase ac-to-dc capacitive link converter with parallel link (single-phase ac=>dc);

(8) FIG. 7 is a circuit diagram of an embodiment of a bidirectional single-phase capacitive link inverter with galvanic isolation;

(9) FIG. 8 is a circuit diagram of an embodiment of a multi-port capacitive link-converter with series link;

(10) FIG. 9 is a circuit diagram of an embodiment of a multi-port capacitive link-converter with parallel link;

(11) FIG. 10 illustrates in panels (a), (b), and (c) circuit diagrams illustrating principles of the operation of an embodiment of a bidirectional single-phase capacitive link inverter with series link when power flows from dc-side to ac-side and load current (I_ac) is positive;

(12) FIG. 11 illustrates in panels (a), (b), and (c) circuit diagrams illustrating principles of the operation of a bidirectional single-phase capacitive link inverter with series link when power flows from ac-side to dc-side and load current (I_ac) is positive;

(13) FIG. 12 illustrates in panels (a), (b), and (c) circuit diagrams illustrating principles of operation of a bidirectional single-phase capacitive link inverter with parallel link when power flows from dc-side to ac-side and load current (I_ac) is positive;

(14) FIG. 13 illustrates in panels (a), (b), and (c) circuit diagrams illustrating principles of operation of a bidirectional single-phase capacitive link inverter with parallel link when power flows from ac-side to dc-side and load current (I_ac) is positive;

(15) FIG. 14 is a graph illustrating inherent double frequency harmonic in single phase inverters;

(16) FIG. 15 is a graph illustrating link voltage and current of a bidirectional single-phase capacitive link inverter when the instantaneous source power is higher than the instantaneous load power;

(17) FIG. 16 is a graph illustrating link voltage and current of a bidirectional single-phase capacitive link inverter when the instantaneous source power is lower than the instantaneous load power;

(18) FIG. 17 is a graph illustrating low frequency component of the link in a bidirectional single-phase capacitive link inverter;

(19) FIG. 18 is a graph illustrating maximum value of link capacitance vs. selected minimum value of the link voltage (V.sub.1(0)) for a 1 kW system

(20) $\left(V_m=200V,I_m=10A,V_{\mathrm{dc}}=50V,I_{\mathrm{dc}}=20A,f_s=6\mathrm{kHz},f_o=60\mathrm{Hz},{}_V=-\frac{}{4},\mathrm{and}{}_i=-\frac{}{4}\right);$

(21) FIG. 19 is a graph illustrating maximum value of link voltage vs. selected minimum value of the link voltage (V.sub.1(0)) for a 1 kW system

(22) $\left(V_m=200V,I_m=10A,V_{\mathrm{dc}}=50V,I_{\mathrm{dc}}=20A,f_s=6\mathrm{kHz},f_o=60\mathrm{Hz},{}_V=-\frac{}{4},\mathrm{and}{}_i=-\frac{}{4}\right);$

(23) FIG. 20 is a circuit diagram of an embodiment of a bidirectional single-phase capacitive link inverter using a series capacitor network (dcsingle-phase ac);

(24) FIG. 21 is a circuit diagram of an embodiment of a bidirectional single-phase capacitive link inverter using a parallel capacitor network (dcsingle-phase ac);

(25) FIG. 22 is a graph illustrating input and output power and the voltage across each capacitor when

(26) $\frac{f_s}{4f_o}$
number of capacitors are used in the proposed single-phase capacitive link inverter;

(27) FIG. 23 is a graph illustrating the voltage across an arbitrary capacitor when

(28) $\frac{f_s}{4f_o}$
number of capacitors are used in the proposed single-phase capacitive link inverter;

(29) FIG. 24 is a graph illustrating the voltage across an arbitrary capacitor (x.sup.th capacitor) when an optional number of capacitors are used in a single-phase capacitive link inverter;

(30) FIG. 25 is a graph illustrating maximum voltage across the switches/diodes vs. the number of capacitors used in as a capacitor network in a single-phase capacitive link inverter for a 1 kW system

(31) $\left(V_m=200V,I_m=10A,V_{\mathrm{dc}}=50V,I_{\mathrm{dc}}=20A,f_s=6\mathrm{kHz},f_o=60\mathrm{Hz},{}_V=-\frac{}{4},{}_i=-\frac{}{4},C=2.2\mathrm{.Math.F}\right);$

(32) FIG. 26 is a circuit diagram of an embodiment of a bidirectional single-phase ac-to-three-phase ac capacitive link converter with series link (single-phase acthree-phase ac);

(33) FIG. 27 is a circuit diagram of an embodiment of a bidirectional single-phase ac-to-three-phase ac capacitive link converter with parallel link (single-phase acthree-phase ac);

(34) FIG. 28 is a circuit diagram of an embodiment of a bidirectional single-phase ac-to-three-phase ac capacitive link converter with galvanic isolation (single-phase acthree-phase ac);

(35) FIG. 29 illustrates in panels (a), (b), (c), and (d) circuit diagrams illustrating principles of the operation of a bidirectional single-phase ac-to-three-phase ac capacitive link converter with series link when power flows from single-phase ac side to three-phase ac side;

(36) FIG. 30 illustrates in panels (a), (b), (c), and (d) circuit diagrams illustrating principles of the operation of a bidirectional single-phase ac-to-three-phase ac capacitive link converter with parallel link when power flows from single-phase ac side to three-phase ac side;

(37) FIG. 31 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to three-phase ac capacitive link converter using a series capacitor network (single-phase acthree-phase ac);

(38) FIG. 32 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to three-phase ac capacitive link converter using a parallel capacitor network (single-phase acthree-phase ac);

(39) FIG. 33 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to single-phase ac capacitive link converter with a series link (single-phase acsingle-phase ac);

(40) FIG. 34 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to single-phase ac capacitive link converter with a parallel link (single-phase acsingle-phase ac);

(41) FIG. 35 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to single-phase ac capacitive link converter with galvanic isolation (single-phase acsingle-phase ac);

(42) FIG. 36 is a graph illustrating low frequency component of the link voltage in a single-phase ac to single-phase ac capacitive link converter for a 1 kW system with f.sub.i=60 Hz and f.sub.0=120 Hz;

(43) FIG. 37 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to single-phase ac capacitive link converter using a series capacitor network (single-phase acsingle-phase ac);

(44) FIG. 38 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to single-phase ac capacitive link converter using a parallel capacitor network (single-phase acsingle-phase ac);

(45) FIG. 39 is a circuit diagram illustrating an embodiment of a bidirectional single-phase inductive-link inverter for positive dc-side current (dc<=>single-phase ac);

(46) FIG. 40 is a circuit diagram illustrating an embodiment of a bidirectional single-phase inductive-link inverter for positive and negative dc-side currents (dcsingle-phase ac);

(47) FIG. 41 is a circuit diagram illustrating an embodiment of a bidirectional single-phase inductive-link inverter for positive dc-side current with galvanic isolation (dc<=>single-phase ac);

(48) FIG. 42 is a circuit diagram illustrating an embodiment of a bidirectional single-phase inductive-link inverter for positive and negative dc-side currents with galvanic isolation (dcsingle-phase ac);

(49) FIG. 43 is a circuit diagram illustrating an embodiment of a multi-port single-phase inductive-link inverter;

(50) FIG. 44 illustrates in panels (a), (b), and (c) circuit diagrams illustrating principles of operation of a single-phase inductive-link inverter;

(51) FIG. 45 is a graph illustrating link inductor current in a single-phase inductive-link inverter;

(52) FIG. 46 is a circuit diagram illustrating an embodiment of a single-phase inductive-link inverter with inductor network;

(53) FIG. 47 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to three-phase ac inductive-link converter (single-phase acthree-phase ac);

(54) FIG. 48 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to three-phase ac inductive-link converter with galvanic isolation (single-phase acthree-phase ac);

(55) FIG. 49 illustrates in panels (a), (b), (c), and (d) circuit diagrams illustrating principles of operation of a bidirectional single-phase ac to three-phase ac inductive-link converter;

(56) FIG. 50 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to three-phase ac inductive-link converter with inductor network (single-phase acthree-phase ac);

(57) FIG. 51 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to single-phase ac inductive-link converter (single-phase acsingle-phase ac);

(58) FIG. 52 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to single-phase ac inductive-link converter with galvanic isolation (single-phase acsingle-phase ac);

(59) FIG. 53 is a circuit diagram illustrating an embodiment of a bidirectional single-phase ac to single-phase ac inductive-link converter with inductor network (single-phase acsingle-phase ac).

DETAILED DESCRIPTION OF THE INVENTION

(60) This application incorporates by reference the entire disclosure of U.S. Provisional Application No. 62/338,103, filed on May 18, 2016, entitled Sparse Capacitive Link Power Converter and Control Method Therefor.

(61) The invention relates to embodiments of power conversion devices having configurations as well as control schemes that regulate input and output currents and manage input and output power mismatches. Some embodiments are operable to suppress dc-side double frequency harmonic components. Some embodiments can operate without using electrolytic capacitors.

(62) In some embodiments, a power conversion device includes input circuitry configured to be coupled to a power source or load, and having at least one switching device or diode. An output switch bridge is configured to be coupled to a load or power source, the output switch bridge having at least four controllable switching devices arranged in a bridge configuration to control current output. A link stage includes at least one reactive component configured for alternating current (AC) operation and is operative to manage input and output of power mismatch between the input circuitry and the output switch bridge.

(63) In some embodiments, a power conversion device employs an additional switch, operates in discontinuous conduction mode (DCM), and uses fixed switching frequency. These features allow this inverter to suppress the double frequency harmonic. In some embodiments, the power conversion device includes an input switch bridge configured to be coupled to a direct current (DC) power source. The input switch bridge includes at least one switching device controllable to regulate an input DC current with suppression of a double frequency harmonic component. A link stage includes at least one reactive component configured for alternating current (AC) operation. The device includes an output switch bridge configured to be coupled to an AC load. The output switch bridge includes at least four controllable switching devices arranged in a bridge configuration to control current output to the load.

(64) 1. Capacitive-Link Converters

(65) 1.1 Capacitive-Link Inverter (dcSingle-Phase ac)

(66) FIG. 1 shows an embodiment of a capacitive-link inverter 10 having a first topology that is used for interfacing a dc source (or load) 11 and a single-phase ac load (or source) 17. This bidirectional inverter is single-stage, and transfers power from input towards output through the link capacitor (C) 14, which is placed in series with the input switch 12 and the output switch bridge 16. As shown in FIG. 2, the link capacitor 14 can also be placed in parallel with the input switch 12 and output switch-bridge 16 while changing the polarity of the output-side switches. In FIGS. 1 and 2 the dc-side voltage is positive (top terminal has positive voltage); however, the dc-side current can be positive (from left to right) or negative (from right to left). Depending on the polarity of the dc-side current the power can flow from dc-side towards ac-side or from ac-side towards dc side. For unidirectional power flow from dc-side to ac-side or from ac-side to dc-side, a switch and/or a diode can be eliminated from each of these topologies, as shown in FIGS. 3-6.

(67) In some embodiments; of converters, galvanic isolation can be provided by a high frequency transformer 15 added to the link 14, as shown in FIG. 7. In some embodiments, this inverter is capable of interfacing several sources (DC1, DC2, DCn) and loads (AC1, AC2, . . . ACm) as depicted in FIGS. 8 and 9.

(68) 1.1.1 Principles of Operation of the Bidirectional Capacitive-Link Inverter

(69) Regardless of the direction of the power flow, this converter has three states (mode) in each switching cycle. FIG. 10 shows the behavior of the first topology when the power flows from dc side to the ac side.

(70) 1) State 1charging the link capacitor through the source: during this state, switch S0 is off. If the load current (I_ac) is positive (right to left), switch S4 and diodes D3 and D1 provide paths for input and output currents. If the load current is negative, switch S3 and diodes D2 and D4 are conducting. During this state, the link current is equal to the dc-side current and it is positive. Therefore, the voltage across the link increases.

(71) 2) State 2discharging the link capacitor into the load: during this state, switch S0 is on to provide a path for the input current and the load current. Switches S1 and S4, if the load current is positive, and switches S2 and S3, if the load current is negative, provide a path for the load current. During this state, the magnitude of the link current is equal to that of the output current and its polarity is negative. Therefore, the voltage across the link decreases.

(72) 3) State 3no power transfer: during this state switch S0 is on to provide a path for input current. If the load current is positive, switch S4 and diode D3 provide a path for the load current. If load current is negative, switch S3 and diode D4 are conducting instead of S4 and D3. During this state the link current is zero, and the link voltage remains constant.

(73) Duration of state 1 is determined such that input current meets its reference, and duration of state 2 is controlled such that the load current meets its reference. State 3 is needed due to the mismatch of input and output power, and its duration depends on the difference between input and output power. In this manner, double frequency harmonic components can be suppressed.

(74) The behavior of the first topology when the power flows from the ac side to the dc side is shown in FIG. 11. In this figure it is assumed I_ac is positive. As seen in this figure, during the first state, diodes D2 and D3 allow I_ac to charge the link capacitor while D0 provides a path for dc-side current and ac-side current. In the second state, dc-side current discharges the link capacitor, and switches S1 and S4 conduct. If the ac-side current is higher than the dc-side current, D3 conducts; otherwise, S3 conducts. During the third state link current is zero, and diodes D0 and D3 along with switch S4 provide paths for the dc-side and ac-side currents. If I_ac is negative D1 and D4 conduct instead of D2 and D3 during the 1st state. In the second state S2 and S3 along with S4 or D4, depending on the values of dc-side and ac-side currents, conduct while in the thirds state D0, S3 and D4 conduct, if I_ac is negative.

(75) The behavior of the second proposed topology (parallel link) when the power flows from dc-side to the ac-side is depicted in FIG. 12. In this figure I_ac is assumed to be positive. Similar to the first proposed topology, there are three states:

(76) 1) State 1charging the link capacitor through dc source: during this state, diode D1 conducts to allow the dc-side current to charge the link capacitor while S4 and D5 provide a path for the ac-side current. If I_ac is negative, S5 and D4 conduct instead of S4 and D5.

(77) 2) State 2discharging the link capacitor into the load: during this mode switch S0 conducts to provide a path for dc-side current. Switches S4 and S3 conduct and allow the link capacitor to be discharged into the load. For negative values of I_ac S2 and S5 will conduct instead of S3 and S4.

(78) 3) State 3no power transfer: during this mode switches S0 and S4 along with diode D5 provide paths for the dc-side and ac-side currents. For negative values of I_ac, switches S0 and S5 along with diode D4 are conducting.

(79) FIG. 13 depicts the behavior of the 2nd proposed topology when power transfers from the ac-side to the dc-side assuming I_ac is positive.

(80) 1.1.2 Analysis of Capacitive-Link Inverter

(81) The disclosed inverters are analyzed as follows, and the maximum voltage of the link capacitor as well as the required link capacitance are determined. The maximum voltage of the link capacitor determines the voltage stress of the switches and diodes.

(82) 1.1.2.1 Voltage Rating of the Switches/Diodes

(83) The output and input voltages and currents of a single-phase inverter are expressed in (1)-(4):
v.sub.o(t)=V.sub.m sin(t+.sub.V)=V.sub.m sin(2f.sub.ot+.sub.V)(1)
i.sub.o(t)=I.sub.m sin(t+.sub.I)=I.sub.m sin(2f.sub.ot+.sub.I)(2)
v.sub.in(t)=V.sub.dc(3)
i.sub.in(t)=I.sub.dc(4)

(84) Using (1)-(4), the output power and the input power, shown in FIG. 14, can be calculated as follows:

(85) $\begin{array}{cc}{P}_o\left(t\right)=\frac{I_m{V}_m}{2}\left\{\cos \left({}_V-{}_I\right)-\cos \left(2t+{}_V+{}_I\right)\right\}=\frac{I_m{V}_m}{2}\left\{\cos \left({}_V-{}_I\right)-\cos \left(4f_{o}t+{}_V+{}_I\right)\right\}& \left(5\right)\\ P_{\mathrm{in}}\left(t\right)=V_{\mathrm{dc}}{I}_{\mathrm{dc}}=\frac{I_m{V}_m}{2}\cos \left({}_V-{}_I\right)& \left(6\right)\end{array}$

(86) According to (5), the instantaneous output power has a dc component and an alternating component the frequency of which is twice the output voltage/current frequency (f.sub.o). The dc component of the output power is equal to the input power. The mismatch of input and output power values need to be managed by the link capacitor. Therefore, the instantaneous value of capacitor power is as follows:

(87) $\begin{array}{cc}{P}_c\left(t\right)=\frac{I_m{V}_m}{2}\cos \left(2t+{}_V+{}_I\right)=\frac{I_m{V}_m}{2}\cos \left(4f_{o}t+{}_V+{}_I\right)& \left(7\right)\end{array}$

(88) Assuming C, i.sub.c(t), and v.sub.c(t) are the link capacitance and low frequency components of the link capacitor current and voltage, the following expression needs to be met:

(89) $\begin{array}{cc}{P}_c\left(t\right)=v_c\left(t\right)i_c\left(t\right)=C{v}_c\left(t\right)\frac{d\left(v_c\left(t\right)\right)}{\mathrm{dt}}& \left(8\right)\end{array}$

(90) One of the possible solutions for (7) and (8) is as follows:

(91) $\begin{array}{cc}{v}_c\left(t\right)=\sqrt{\frac{I_m{V}_m}{C}}\sin \left(t+\frac{{}_V+{}_I}{2}+\frac{}{4}\right)0t+\frac{{}_V+{}_I}{2}+\frac{}{4}& \left(9\right)\\ v_c\left(t\right)=-\sqrt{\frac{I_m{V}_m}{C}}\sin \left(t+\frac{{}_V+{}_I}{2}+\frac{}{4}\right)t+\frac{{}_V+{}_I}{2}+\frac{}{4}2& \left(10\right)\\ i_c\left(t\right)=C\sqrt{\frac{I_m{V}_m}{C}}\cos \left(t+\frac{{}_V+{}_I}{2}+\frac{}{4}\right)0t+\frac{{}_V+{}_I}{2}+\frac{}{4}& \left(11\right)\\ i_c\left(t\right)=-C\sqrt{\frac{I_m{V}_m}{C}}\cos \left(t+\frac{{}_V+{}_I}{2}+\frac{}{4}\right)t+\frac{{}_V+{}_I}{2}+\frac{}{4}2& \left(12\right)\end{array}$

(92) The above response results in having a minimum link voltage of zero. It is also possible to determine the link capacitor voltage and current such that the minimum voltage of capacitor is above zero. One possible solution for this case is as follows:

(93) 0$\begin{array}{cc}{v}_c\left(t\right)=\sqrt{\frac{I_m{V}_m}{2C}\sin \left(2t+{}_V+{}_I\right)+V_0}& \left(13\right)\\ i_c\left(t\right)=\frac{I_m{V}_m\cos \left(2t+{}_V+{}_I\right)}{2\sqrt{\frac{I_m{V}_m}{2C}\sin \left(2t+{}_V+{}_I\right)+V_0}}& \left(14\right)\end{array}$

(94) In prior art techniques, only (13) and (14) are considered as the voltage and current across the link capacitor.

(95) As mentioned earlier, in any switching cycle, there are three states. The voltage of the link capacitor at the beginning of states 1 to 3 in any arbitrary cycle (i.sup.th cycle) is expressed as V.sub.1(i), V.sub.2(i), and V.sub.3(i), respectively. During the first state (charging mode), the input current passes the link capacitor and charges the capacitor. This results in an increase of the link voltage from V.sub.1(i) to V.sub.2(i). During the second state (discharging mode), the load current passes the link capacitor. However, the current of the link capacitor during this state (discharging mode) is negative. This results in a decrease of the link voltage from V.sub.2(i) to V.sub.3(i). As shown in FIGS. 15 and 16, if the instantaneous value of the input power is higher than the instantaneous value of the output power, V.sub.3(i) will be higher than V.sub.1(i); otherwise, V.sub.3(i) will be lower than V.sub.1(i). During the third state, no current passes the link capacitor, and the link voltage remains equal to V.sub.3(i). The voltage at the beginning of the next cycle ((i+1).sup.th cycle) will be equal to V.sub.3(i):
V.sub.1(i+1)=V.sub.3(i)(15)
If the input power is higher than the load power, V.sub.1(i+1) will be higher than V.sub.1(i). Assuming f.sub.s is the switching frequency, in each load power cycle, the duration of which is

(96) $\frac{1}{2f_o},$
there are

(97) $\frac{f_s}{2f_o}$
high frequency cycles. In half of these cycles the input power is higher than the load power, and in another half of these cycles, the input power is lower than the load power. FIG. 17 shows the low frequency component of the link capacitor voltage.

(98) Assuming the duration modes 1 to 3 in i.sup.th cycle are t.sub.1(i), t.sub.2(i), and t.sub.3(i), respectively, (16) to (18) describe the behavior of the circuit during the charging state of an arbitrary switching cycle (the i.sup.th cycle, where

(99) $1i\frac{f_s}{2f_o}):$

(100) $\begin{array}{cc}{i}_{\mathrm{in}}\left(i\right)=I_{\mathrm{dc}}=C\frac{V_2\left(i\right)-V_1\left(i\right)}{t_1\left(i\right)}& \left(16\right)\\ v_{\mathrm{in}}\left(i\right)=V_{\mathrm{dc}}=t_1\left(i\right)f_s\frac{V_2\left(i\right)+V_1\left(i\right)}{2}& \left(17\right)\\ P_{\mathrm{in}}\left(i\right)=I_{\mathrm{dc}}{V}_{\mathrm{dc}}=\frac{I_m{V}_m}{2}\cos \left({}_V-{}_I\right)=\frac{1}{2}{\mathrm{Cf}}_s\left(V_2^2\left(i\right)-V_1^2\left(i\right)\right)& \left(18\right)\end{array}$

(101) The behavior of the converter during the discharging state can be expressed through (19) to (21):

(102) $\begin{array}{cc}{i}_o\left(i\right)=I_m\sin \left(\frac{2f_o}{f_s}i+{}_I\right)=C\frac{V_2\left(i\right)-V_3\left(i\right)}{t_2\left(i\right)}& \left(19\right)\\ v_o\left(i\right)=V_m\sin \left(\frac{2f_o}{f_s}i+{}_V\right)=t_2\left(i\right)f_s\frac{V_2\left(i\right)+V_3\left(i\right)}{2}& \left(20\right)\\ P_o\left(t\right)=v_o\left(i\right)*i_o\left(i\right)=\frac{I_m{V}_m}{2}\left\{\cos \left({}_V-{}_I\right)-\cos \left(\frac{4f_o}{f_s}i+{}_V+{}_I\right)\right\}=\frac{1}{2}{\mathrm{Cf}}_s\left(V_2^2\left(i\right)-V_3^2\left(i\right)\right)=\frac{1}{2}{\mathrm{Cf}}_s\left(V_2^2\left(i\right)-V_1^2\left(i+1\right)\right)& \left(21\right)\end{array}$

(103) Using (18) and (21), V.sub.1(i+1) can be calculated:

(104) $\begin{array}{cc}{V}_1^2\left(i+1\right)=\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left(\frac{4f_o}{f_s}i+{}_V+{}_I\right)+V_1^2\left(i\right)\left(1i\frac{f_s}{2f_o}\right)& \left(22\right)\end{array}$

(105) Assuming the initial value of the link voltage across the link capacitor is V.sub.1(0), (22) can be simplified as follows:

(106) $\begin{array}{cc}{V}_1^2\left(i+1\right)=\underset{x=1}{\overset{i}{.Math.}}\left(\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left(\frac{4f_o}{f_s}x+{}_V+{}_I\right)\right)+V_1^2\left(0\right)& \left(23\right)\end{array}$

(107) The value of V.sub.1(i+1) can be determined as follows:

(108) $\begin{array}{cc}{V}_1\left(i+1\right)=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\frac{\sin \left(\frac{2f_o}{f_s}\left(i+1\right)\right)\cos \left(\frac{2f_o}{f_s}i+{}_V+{}_I\right)}{\sin \left(\frac{2f_o}{f_s}\right)}+V_1^2\left(0\right)}& \left(24\right)\end{array}$

(109) Using (24) and (18), V.sub.2(i) can be determined:

(110) $\begin{array}{cc}{V}_2\left(i\right)=\sqrt{\begin{array}{c}\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\frac{\sin \left(\frac{2f_o}{f_s}\left(i+1\right)\right)\cos \left(\frac{2f_o}{f_s}i+{}_V+{}_I\right)}{\sin \left(\frac{2f_o}{f_s}\right)}+\\ \frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left({}_V-{}_I\right)+V_1^2\left(0\right)\end{array}}& \left(25\right)\end{array}$

(111) It can be shown that the maximum value of V.sub.2 that occurs at

(112) 0$=\frac{f_s}{4f_o},$
and is equal to:

(113) $\begin{array}{cc}{V}_{2,\max }=\sqrt{-\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\frac{\cos \left(\frac{2f_o}{f_s}\right)\sin \left({}_V+{}_I\right)}{\sin \left(\frac{2f_o}{f_s}\right)}+\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left({}_V-{}_I\right)+V_1^2\left(0\right)}& \left(26\right)\end{array}$

(114) Assuming

(115) ${}_V={}_I=-\frac{}{4},$
the maximum value of V.sub.2 is is as follows:

(116) $\begin{array}{cc}{V}_{2,\max }=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\left(\frac{\cos \left(\frac{2f_o}{f_s}\right)}{\sin \left(\frac{2f_o}{f_s}\right)}+1\right)+V_1^2\left(0\right)}& \left(27\right)\end{array}$

(117) If f.sub.o<<f.sub.s, the maximum value of V.sub.2 can be determined by (28):

(118) $\begin{array}{cc}\begin{array}{c}{V}_{2,\max }=\sqrt{\frac{I_m{V}_m}{2f_{o}C}+\frac{I_m{V}_m}{{\mathrm{Cf}}_s}+V_1^2\left(0\right)}\sqrt{\frac{I_m{V}_m}{2f_{o}C}+V_1^2\left(0\right)}\end{array}& \left(28\right)\end{array}$

(119) The voltage rating of all the switches and diodes in the disclosed inverters are equal to V.sub.2,max. It should be noted that although the value of V.sub.1(0) is optional, it needs to be in the following range:

(120) $\begin{array}{cc}0V_1\left(0\right)\frac{V_m}{\sqrt{2}}+V_o& \left(29\right)\end{array}$
1.1.2.2 Maximum Capacitance

(121) To make sure this inverter has all the three states in each switching cycle, the following condition must be valid:

(122) $\begin{array}{cc}{t}_1\left(i\right)+t_2\left(i\right)<\frac{1}{f_s}& \left(30\right)\end{array}$
Using (17) and (20), (30) can be written as follows:

(123) $\begin{array}{cc}\frac{2V_{\mathrm{dc}}}{V_2\left(i\right)+V_1\left(i\right)}+\frac{2v_o\left(i\right)}{V_2\left(i\right)+V_1\left(i+1\right)}<1& \left(31\right)\end{array}$
It can be shown that the maximum value of t.sub.1(i)+t.sub.2(i) occurs at

(124) $i=\frac{f_s}{2f_o}.$
The values of V.sub.2 and V.sub.1 at this point can be calculated by (24) and (25):

(125) $\begin{array}{cc}{V}_1\left(\frac{f_s}{2f_o}\right)=V_1\left(\frac{f_s}{2f_o}+1\right)=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left({}_V+{}_I\right)+V_1^2\left(0\right)}& \left(32\right)\\ V_2\left(\frac{f_s}{2f_{\mathrm{in}}}\right)=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left({}_V+{}_I\right)+\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left({}_V-{}_1\right)+V_1^2\left(0\right)}& \left(33\right)\end{array}$

(126) Plugging (32) and (33) into (31) determines the maximum value of the link capacitance:

(127) 0$\begin{array}{cc}.Math.2V_m\sin \left(+{}_V\right).Math.+2V_{\mathrm{dc}}<\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left({}_V+{}_I\right)+V_1^2\left(0\right)}+\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left({}_V+{}_I\right)+\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left({}_V-{}_1\right)+V_1^2\left(0\right)}& \left(34\right)\end{array}$

(128) Assuming

(129) ${}_V={}_I=-\frac{}{4},$
proper values of V.sub.1(0), C, and f.sub.s can be selected such that:

(130) $\begin{array}{cc}{V}_m\sqrt{2}+2V_{\mathrm{dc}}<\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}+V_1^2\left(0\right)}+V_1\left(0\right)& \left(35\right)\end{array}$

(131) The maximum value of the link capacitance will be as follows:

(132) $\begin{array}{cc}C<\frac{l_m{V}_m}{f_s\left(V_m\sqrt{2}+2V_{\mathrm{dc}}\right)\left(V_m\sqrt{2}+2V_{\mathrm{dc}}-2V_1\left(0\right)\right)}& \left(36\right)\end{array}$

(133) A unique feature of the disclosed inverter is that it does not have any minimum requirement for the link capacitance; instead it has a maximum requirement.

(134) Plugging the maximum value of the capacitance achieved from (36) into (28), the voltage rating of the switches/diodes, which is equal to the maximum value of the link voltage, is determined as follows:

(135) $\begin{array}{cc}{V}_{2,\max }\sqrt{\left(\frac{f_s}{2f_o}\left(V_m\sqrt{2}+2V_{\mathrm{dc}}\right)\left(V_m\sqrt{2}+2V_{\mathrm{dc}}-2V_1\left(0\right)\right)\right)+V_1^2\left(0\right)}& \left(37\right)\end{array}$
1.1.3 Techniques for Reducing the Voltage Rating of the Switches

(136) According to (36) and (28), the link capacitance of the proposed inverter can be as small as the designer wishes; however, choosing a very small value for C increases the maximum value of the link voltage. Accordingly, a number of techniques for reducing the maximum value of the link voltage are described herein.

(137) 1.1.3.1 Choosing a Nonzero Value for Minimum Voltage of the Link Capacitor to Increase the Maximum Capacitance

(138) According to (36) and (28), choosing a nonzero value for V.sub.1(0) helps increase the maximum value of the link capacitance and reduces the voltage stress. The closer V.sub.1(0) is to its maximum value (determined by (29)) the lower the peak voltage of the capacitor is. As an example, FIG. 18 shows the maximum value of link capacitance for different values of V.sub.1(0), assuming

(139) $V_m=200V,I_m=10A,V_{\mathrm{dc}}=50V,I_{\mathrm{dc}}=20A,f_s=6\mathrm{kHz},f_o=60\mathrm{Hz}{}_V=-\frac{}{4},\mathrm{and}{}_i=\frac{}{4}.$
FIG. 19 depicts the maximum value of link voltage in this system for different values of V.sub.1(0), assuming the maximum link capacitance is selected.
1.1.3.2 Use of Multiple Capacitors (a Capacitor Network) for Reducing the Voltage Rating of the Switches/Diodes

(140) To minimize the voltage rating of the switches in the inverter, a capacitor network can be used instead of a single capacitor. The schematics of the embodiment of an inverter when a capacitor network is used instead of a single capacitor are illustrated in FIGS. 20 and 21.

(141) One approach is to use

(142) $\frac{f_s}{4f_o}$
number of capacitors such that each capacitor can be involved in transferring the power in two switching cycles (cycle i and cycle

(143) ${}^{}\frac{f_s}{4f_o}+i^{})$
over a load power cycle, the frequency of which is 2f.sub.o. The difference between the instantaneous values of the input power and output power in cycles i and

(144) ${}^{}\frac{f_s}{4f_{\mathrm{in}}}+i^{}$
are equal but they have opposite polarities. This implies that the net energy is zero, and the voltage of the capacitor at the beginning of cycle i is equal to the voltage of the capacitor at the end of cycle

(145) ${}^{}\frac{f_s}{4f_o}+i^{}.$
FIG. 22 shows this concept.

(146) It is also possible to use an arbitrary number of capacitors. In this case each capacitor will be involved in transferring the power in more than two switching cycles over a load power cycle, i.e. in i.sup.th cycle,

(147) 0${}^{}\frac{f_s}{4f_o}+i^{\mathrm{th}}$
cycle, and a number of consequent cycles after cycles i and

(148) $\frac{f_s}{4f_{\mathrm{in}}}+i.$

(149) Both approaches are discussed below.

(150) 1.1.3.2.1 Using

(151) $\frac{f_s}{4f_0}$
Number of Capacitors

(152) FIG. 23 shows the voltage of an arbitrary capacitor (x.sup.th capacitor) that transfers power in cycle x and cycle

(153) $\frac{f_s}{4f_{\mathrm{in}}}+x$
In cycle x the input power is higher than the load power; therefore, V.sub.c,x,3 (the voltage of x.sup.th capacitor at the end of x.sup.th cycle) will be higher than V.sub.c,x,1 (the voltage of x.sup.th capacitor at the beginning of x.sup.th cycle). In cycle

(154) $\frac{f_s}{4f_{\mathrm{in}}}+x$
the input power is lower than the load power; thus, the voltage of x.sup.th capacitor at the beginning this cycle, which is equal to V.sub.c,x,3, will be higher than its voltage at the end of this cycle. As mentioned earlier the difference between input and output power values are the same in these two cycles but they have opposite polarities. This implies that the voltage of the capacitor at the end of cycle

(155) $\frac{f_s}{4f_{\mathrm{in}}}+x$
will be equal to V.sub.c,x,1.

(156) The peak value of the voltage across x.sup.th capacitor in each of the two cycles, i.e. cycles x and

(157) $\frac{f_s}{4f_{\mathrm{in}}}+x,$
can be determined based on V.sub.C,x,1 and the instantaneous values of source power and load power. The values of V.sub.C,x,2 and V.sub.C,x,4 can be determined by (38) and (39):

(158) $\begin{array}{cc}{C}_{c,x,2}=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left({}_V-{}_I\right)+V_{C,x,1}^2}& \left(38\right)\\ V_{c,x,4}=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\left\{\cos \left({}_V-{}_I\right)-\cos \left(\frac{4f_o}{f_s}i+{}_V+{}_I\right)\right\}+V_{C,x,1}^2}& \left(39\right)\end{array}$
Assuming

(159) ${}_V={}_I=-\frac{}{4}\mathrm{and}$$V_{c,x,1}=0,V_{C,x,2}\mathrm{and}$$V_{C,x,4}$
will be as follows:

(160) $\begin{array}{cc}{V}_{c,x,2}=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}}& \left(40\right)\\ V_{c,x,4}=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\left\{1+\sin \left(4\frac{f_o}{f_s}x\right)\right\}}& \left(41\right)\end{array}$

(161) According to (40), V.sub.C,x,2 does not depend on the value of x; therefore, the peak value of the voltage across all the capacitors during the first half cycle of the load power is the same. However, the value of V.sub.C,x,4 depends on the value of x. To find the voltage stress of the switches/diodes, the maximum value of V.sub.C,x,4 needs to be determined. It should be noted that

(162) 0$1<x<\frac{f_s}{4f_o};$
therefore,

(163) $0<\sin \left(\frac{4f_{\mathrm{in}}}{f_s}x\right)<1.$
This implies that V.sub.C,x,4 varies in the following range:

(164) $\begin{array}{cc}\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}}<V_{C,x,4}<\sqrt{\frac{2I_m{V}_m}{{\mathrm{Cf}}_s}}& \left(42\right)\end{array}$

(165) The voltage rating of the switches/diodes, which is equal to the maximum value of V.sub.c,x,4, is as follows:

(166) $\begin{array}{cc}{V}_{\max }=\sqrt{\frac{{21}_m{V}_m}{{\mathrm{Cf}}_s}}& \left(43\right)\end{array}$

(167) If maximum value of capacitance, determined by (36), is used, the maximum value of the link voltage will be as follows:
V.sub.max=2(V.sub.m+{square root over (2)}V.sub.cd)(44)

(168) Assuming as an example

(169) $\begin{array}{cc}{V}_m=200V,I_m=10A,V_{\mathrm{dc}}=50V,I_{\mathrm{dc}}=20A,f_s=6\mathrm{kHz},f_o=60\mathrm{Hz},{}_V=-\frac{}{4},\mathrm{and}{}_i=-\frac{}{4},& \end{array}$
the maximum voltage stress of this inverter is 816V when 25 capacitors are used.
1.1.3.2.2 Using an Arbitrary Number of Capacitors

(170) As mentioned above, it is also possible to use each capacitor for more than two cycles. The voltage of an arbitrary link capacitor (x.sup.th capacitor) that transfers power during 2N switching cycles over the load power cycle is shown in FIG. 24. In this figure, the arbitrary capacitor (x.sup.th capacitor) is involved in transferring the power in cycles (x1)N+1 to xN and cycles

(171) $\frac{f_s}{4f_o}+\left(x-1\right)N+1\mathrm{to}\frac{f_s}{4f_o}+\mathrm{xN}.$
There are

(172) $M=\frac{f_s}{4N{f}_o}$
number of capacitors in this inverter, and x varies in the following range:

(173) $\begin{array}{cc}1x\frac{f_s}{4N{f}_o}& \left(45\right)\end{array}$
During cycles (x1)N+1 to xN, the input power is higher than the load power; therefore, the voltage across the capacitor at the end of each cycle is higher than that of beginning of that cycle. During cycles

(174) $\frac{f_s}{4f_o}+\left(x-1\right)N+1\mathrm{to}\frac{f_s}{4f_o}+xN$
the input power is lower than the output power; thus, the voltage of the capacitor at the end of each cycle is lower than the beginning of the cycle.

(175) The value of the link voltage at the beginning of each cycle (V.sub.C,x,2i+1) depends on its value at the beginning of the previous cycle (V.sub.C,x,2i1) and the alternating part of the load power in that cycle:

(176) $\begin{array}{cc}\frac{l_m{v}_m}{2}\cos \left(\frac{4f_o}{f_s}\left(\left(x-1\right)N+i\right)+{}_V+{}_I\right)=\frac{1}{2}{\mathrm{Cf}}_s\left(V_{C,x,2i+1}^2-V_{C,x,2i-1}^2\right)1iN& \left(46\right)\end{array}$
Assuming the initial voltage of the x.sup.th capacitor is V.sub.C,x,1, the voltage of this capacitor at the end of each cycle (cycle (x1)N+i) can be determined as follows:

(177) 0$\begin{array}{cc}{V}_{C,x,2i+1}=\sqrt{\underset{y=1}{\overset{i}{.Math.}}\left(\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left(\frac{4f_o}{\mathrm{fs}}\left(\left(x-1\right)N+y\right)+{}_V+{}_I\right)\right)+V_{C,x,1}^2}& \left(47\right)\end{array}$
The voltage of the capacitor at the end of (xN).sup.th cycle can be determined by (48):

(178) $\begin{array}{cc}{V}_{C,x,2N+1}=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\frac{\sin \left(\frac{4f_o}{f_s}\frac{N+1}{2}\right)\cos \left(\frac{4f_o}{f_s}\frac{N}{2}+\frac{4f_o}{\mathrm{fs}}\left(x-1\right)N+{}_V+{}_I\right)}{\sin \left(\frac{2f_o}{\mathrm{fs}}\right)}+V_{C,x,1}^2}& \left(48\right)\end{array}$
The peak value of the voltage across x.sup.th capacitor occurs in cycle

(179) $\frac{f_s}{4f_o}+\left(x-1\right)N+1,$
and it can be determined as follows:

(180) $\begin{array}{cc}{V}_{C,x,2N+2}=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\frac{\sin \left(\frac{4f_o}{f_s}\frac{N+1}{2}\right)\cos \left(\frac{4f_o}{f_s}\frac{2\mathrm{xN}-N}{2}+{}_V+{}_I\right)}{\sin \left(\frac{2f_o}{\mathrm{fs}}\right)}+\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\cos \left({}_V-{}_I\right)+V_{C,x,1}^2}& \left(49\right)\end{array}$
Assuming

(181) ${}_V={}_I=-\frac{}{4}\mathrm{and}{V}_{c,x,1}=0,$
(49) can be simplified as follows:

(182) $\begin{array}{cc}{V}_{C,x,2N+2}=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\left(\frac{\sin \left(\frac{2f_o}{f_s}\left(N+1\right)\right)\sin \left(\frac{2f_o}{f_s}\left(2\mathrm{xN}-N\right)\right)}{\sin \left(\frac{2f_o}{f_s}\right)}+1\right)}& \left(50\right)\end{array}$
V.sub.C,x,2N+2, which is calculated by (50), denotes the peak voltage of the x.sup.th capacitor. There are

(183) $\frac{f_s}{4N{f}_o}$
number of capacitors, and the capacitor, the peak voltage of which has the maximum value, determines the voltage rating of the switches/diodes. According to (50), V.sub.C,x,2N+2 will be maximum if the following condition is valid:

(184) $\begin{array}{cc}\frac{d\left(\sin \left(\frac{2f_o}{\mathrm{fs}}\left(2xN-N\right)\right)\right)}{\mathrm{dx}}=0.Math.\frac{2f_o}{f_s}\left(2\mathrm{xN}-N\right)=\frac{}{2}.Math.x=\frac{f_s}{8N{f}_o}+\frac{1}{2}& \left(51\right)\end{array}$

(185) The voltage stress of the switches and diodes when

(186) $x=\frac{f_s}{8N{f}_o}+\frac{1}{2}$
is equal to:

(187) $\begin{array}{cc}{V}_{C,\mathrm{MAX}}=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\left(\frac{\sin \left(\frac{2f_o}{f_s}\left(N+1\right)\right)}{\sin \left(\frac{2f_o}{f_s}\right)}+1\right)}\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\left(\frac{\sin \left(\frac{2f_o}{f_s}N\right)}{\sin \left(\frac{2f_o}{f_s}\right)}+1\right)}& \left(52\right)\end{array}$

(188) In (52) the voltage stress is expressed based on N. The voltage stress can also be calculated based on the number of capacitors, M, as follows:

(189) 0$\begin{array}{cc}{V}_{C,\mathrm{MAX}}=\sqrt{\frac{I_m{V}_m}{{\mathrm{Cf}}_s}\left(\frac{\sin \left(\frac{}{2M}\right)}{\sin \left(\frac{2f_o}{f_s}\right)}+1\right)}& \left(53\right)\\ M=\frac{f_s}{4N{f}_o}& \left(54\right)\end{array}$

(190) If the maximum allowable capacitance is used, (53) will be simplified as follows:

(191) $\begin{array}{cc}{V}_{C,\mathrm{MAX}}=\sqrt{2}\left(V_m+\sqrt{2}{V}_{\mathrm{dc}}\right)\sqrt{\frac{\sin \left(\frac{}{2M}\right)}{\sin \left(\frac{2f_o}{f_s}\right)}+1}& \left(55\right)\end{array}$

(192) According to (55) increasing the value of M decreases the voltage stress. The maximum value of M, as discussed in previous part is

(193) $\frac{f_s}{4f_o}.$

(194) Assuming

(195) $V_m=200V,I_m=10A,V_{\mathrm{dc}}=50V,I_{\mathrm{dc}}=20A,f_s=6\mathrm{kHz},f_o=60\mathrm{Hz},{}_V=-\frac{}{4},{}_i=-\frac{}{4},C=2.2F,$
FIG. 25 shows the maximum voltage across the switches/diodes of this inverter vs. the number of capacitors in the capacitor network.
1.1.3.3 Use of Transformer for Reducing Voltage Stress

(196) Another solution for reducing the voltage stress of the switches and diodes in the proposed inverter is to use a low frequency transformer at the load.

(197) By using a transformer, the maximum capacitance can be increased. Assuming the turn ratio of the transformer is a (a<1), the maximum required capacitance will be determined as follows:

(198) $\begin{array}{cc}C<\frac{I_m{V}_m}{{f_s\left(a{V}_m\sqrt{2}+2V_{\mathrm{dc}}\right)}^2}& \left(56\right)\end{array}$

(199) Using (56) and (28) the voltage stress can be determined:

(200) $\begin{array}{cc}{V}_{2,\max }=\sqrt{\frac{I_m{V}_m}{2f_{\mathrm{in}}C}}=\sqrt{2}\left(a{V}_m+\sqrt{2}{V}_{\mathrm{dc}}\right)\sqrt{\frac{f_s}{2f_o}}& \left(57\right)\end{array}$
1.2 Single-Phase ac to Three-Phase ac Capacitive Link Converter

(201) Unlike single-phase ac systems, the instantaneous power of a three-phase ac system (source or load) is a constant dc value. This implies that a three-phase ac to a single-phase ac or a single-phase ac to a three-phase ac converter will have the inherent double frequency harmonic problem. The single-phase inverter topology described above can be extended to be used in these systems. FIGS. 26 and 27 depict the bidirectional single-phase ac to three-phase ac converters with series and parallel link capacitors, respectively. Referring to FIG. 26, an input switch bridge 52, output switch bridge 56, and link state 54 are connected in series. A single phase AC source 51 and three-phase AC load 57 are provided. Galvanic isolation, as shown in FIG. 28, can be provided by adding a high frequency transformer to the link.

(202) 1.2.1 Analysis of Single-Phase ac to Three-Phase ac Capacitive Link Converter

(203) The single-phase ac-to-three phase ac converter has 4 states in each switching cycle. If the power flows from a single-phase ac source towards a three-phase ac load, there will be one charging state, two discharging states, and a state during which no power is transferred. FIG. 29 shows the behavior of the converter with series link capacitor in each of the states. During the time span shown in this figure, I.sub.in, I.sub.Ao, and I.sub.Co are positive (left to right), and I.sub.bo is negative (right to left). Also, for the case shown in FIG. 29, the voltage across the output phase pair BCo has the maximum line to line output voltage and it is negative. It is clear that the phase pair carrying the maximum line-to-line voltage and its polarity continuously change over a load/source cycle. Also, the polarity of the input and output currents change over a load/source cycle.

(204) In state 1, diodes D1 and D4 at the input side and diodes D5 and D8 along with switches S6 and S10 at the output-side conduct. The input current passes the link capacitor and charges it. In state 2, switches S2 and S4 will be turned on and diodes D8 and D4 stop conducting. During this state, the current of phase C passes the link capacitor, and since it is negative the link capacitor starts discharging. To end this state and initiate state 3, switch S8 is turned on. By turning on switch S8, diode D5 stops conducting, and the current of phase B passes the link capacitor. The link capacitor continues discharging. To end this state switches S6 and S4 will be tuned off, and diode D9 starts to conduct. During state 4, the link current is zero.

(205) The behavior of the converter with parallel link capacitor is shown in FIG. 30.

(206) The low frequency component of the link capacitor voltage will be similar to that of the single-phase inverter. Assuming the current and voltage of the single-phase source/load are:
v.sub.i(t)=V.sub.m sin(t+.sub.V)=V.sub.m sin(2ft+.sub.V)(58)
i.sub.i(t)=I.sub.m sin(t+.sub.I)=I.sub.m sin(2ft+.sub.I)(59)

(207) Two possible equations for low frequency component of the link voltage are as follows:

(208) $\begin{array}{cc}{v}_c\left(t\right)=.Math.\sqrt{\frac{I_m{v}_m}{c}}\sin \left(2\mathrm{ft}+\frac{{}_V+{}_I}{2}+\frac{}{4}\right).Math.& \left(60\right)\\ v_c\left(t\right)=\sqrt{\frac{I_m{V}_m}{2C}\sin \left(4\mathrm{ft}+{}_V+{}_I\right)+V_0}& \left(61\right)\end{array}$

(209) All techniques disclosed herein for reducing the link peak voltage of the single-phase inverter topologies can also be used in the single-phase ac to three-phase ac topologies. FIGS. 31 and 32 depict these topologies when a capacitor network is used instead of one capacitor.

(210) 1.3 Single-Phase ac to Single-Phase ac Capacitive Link Inverter

(211) In some embodiment, converters are provided for applications that have single-phase ac sources and single-phase ac loads; however, the voltage amplitude and/or frequency of the input and output are not necessarily the same. The proposed single-phase ac-ac converters are depicted in FIGS. 33 and 34. The isolated configuration is shown in FIG. 35.

(212) In single-phase ac-to-single-phase ac inverters the input and output power both have dc and alternating components. The alternating components of the input and output power are not necessarily the same. Therefore, there may be a mismatch of power that needs to be managed.

(213) The input and output voltages and currents are expressed in (62)-(65):
v.sub.i(t)=V.sub.mi sin(.sub.it+.sub.Vi)=V.sub.mi sin(2f.sub.it+.sub.Vi)(62)
i.sub.i(t)=I.sub.mi sin(.sub.it+.sub.Ii)=I.sub.mi sin(2f.sub.it+.sub.Ii)(63)
v.sub.o(t)=V.sub.mo sin(.sub.ot+.sub.Vo)=V.sub.mo sin(2f.sub.ot+.sub.Vo)(64)
i.sub.o(t)=I.sub.mo sin(.sub.ot+.sub.Io)=I.sub.mo sin(2f.sub.ot+.sub.Io)(65)
Using (62)-(65), the input and output power, will be calculated as follows:

(214) $\begin{array}{cc}{P}_i\left(t\right)=\frac{I_{\mathrm{mi}}{V}_{\mathrm{mi}}}{2}\left\{\cos \left({}_{\mathrm{Vi}}-{}_{\mathrm{Ii}}\right)-\cos \left(2{}_{i}t+{}_{\mathrm{Vi}}+{}_{Ii}\right)\right\}=\frac{I_{\mathrm{mi}}{V}_{\mathrm{mi}}}{2}\left\{\cos \left\{{}_{\mathrm{Vi}}-{}_{Ii}\right)-\cos \left(4f_{i}t+{}_{Vi}+{}_{Ii}\right)\right\}& \left(66\right)\\ P_o\left(t\right)=\frac{I_{\mathrm{mo}}{V}_{\mathrm{mo}}}{2}\left\{\cos \left({}_{\mathrm{Vo}}-{}_{\mathrm{Io}}\right)-\cos \left(2{}_{o}t+{}_{\mathrm{Vo}}+{}_{Io}\right)\right\}=\frac{I_{\mathrm{mo}}{V}_{\mathrm{mo}}}{2}\left\{\cos \left\{{}_{\mathrm{Vo}}-{}_{Io}\right)-\cos \left(4f_{o}t+{}_{Vo}+{}_{Io}\right)\right\}& \left(67\right)\end{array}$
The average values of input and output power need to be equal:

(215) $\begin{array}{cc}\frac{I_{\mathrm{mi}}{V}_{\mathrm{mi}}}{2}\cos \left({}_{\mathrm{Vi}}-{}_{\mathrm{Ii}}\right)=\frac{I_{mo}{V}_{\mathrm{mo}}}{2}\cos \left({}_{\mathrm{Vo}}-{}_{Io}\right)& \left(68\right)\end{array}$
The mismatch of input and output power values need to be managed by the link capacitor. Therefore, the instantaneous value of the link capacitor power is as follows:

(216) $\begin{array}{cc}{P}_c\left(t\right)=\frac{I_{\mathrm{mo}}{V}_{\mathrm{mo}}}{2}\cos \left(2{}_{o}t+{}_{Vo}+{}_{\mathrm{Io}}\right)-\frac{I_{\mathrm{mi}}{V}_{\mathrm{mi}}}{2}\cos \left(2{}_{i}t+{}_{Vi}+{}_{\mathrm{Ii}}\right)& \left(69\right)\end{array}$
Assuming C, i.sub.c(t), and v.sub.c(t) are the link capacitance and low frequency components of the link capacitor current and voltage, the following expression needs to be met:

(217) 0$\begin{array}{cc}{P}_c\left(t\right)=v_c\left(t\right)i_c\left(t\right)=C{v}_c\left(t\right)\frac{d\left(v_c\left(t\right)\right)}{\mathrm{dt}}& \left(70\right)\end{array}$

(218) One of the possible solutions for (69) and (70) is as follows:

(219) $\begin{array}{cc}{v}_c\left(t\right)=.Math.\sqrt{\frac{I_{\mathrm{mo}}{V}_{\mathrm{mo}}}{C{}_o}}\sin \left({}_{o}t+\frac{{}_{Vo}+{}_{Io}}{2}+\frac{}{4}\right)-\sqrt{\frac{I_{mi}{V}_{\mathrm{mi}}}{C{}_i}}\sin \left({}_{i}t+\frac{{}_{\mathrm{Vi}}+{}_{\mathrm{Ii}}}{2}+\frac{}{4}\right).Math.& \left(71\right)\end{array}$

(220) Another possible solution for (69) and (70), can be:

(221) $\begin{array}{cc}{v}_c\left(t\right)=\sqrt{\frac{I_{\mathrm{mo}}{V}_{\mathrm{mo}}}{2C{}_o}\sin \left(2{}_{o}t+{}_{Vo}+{}_{Io}\right)-\frac{I_{mi}{V}_{\mathrm{mi}}}{2C{}_i}\sin \left(2{}_{i}t+{}_{\mathrm{Vi}}+{}_{\mathrm{Ii}}\right)+V_0}& \left(72\right)\end{array}$