Gate driving circuit and display device

Abstract

The invention provides a gate driving circuit and a display device. The gate driving circuit is configured to drive a display panel of the display device, and includes shift registers and at least a dummy shift register. The shift registers are respectively configured to generate and output scan signals to scan lines of the display panel, the dummy shift register is configured to generate a dummy scan signal before the scan signals are generated. The dummy scan signal and the scan signals are sequentially generated.

Claims

1. A gate driving circuit for driving a display panel, the gate driving circuit comprising: 1.sup.st to 4.sup.th stage first dummy shift registers configured to respectively generate and output 1.sup.st to 4.sup.thstage first dummy scan signals, wherein the 1.sup.st to 4.sup.th stage first dummy shift registers are disposed at one side of the display panel; and 1.sup.st to N.sup.th stage first shift registers configured to respectively generate and output 1.sup.st to N.sup.th stage first scan signals to a plurality of scan lines of the display panel, wherein N is an integer; wherein the 1.sup.st to 4.sup.th stage first dummy scan signals are generated before theist stage first scan signal is generated, wherein time durations required for the 1.sup.st to 4.sup.th stage first dummy scan signals to rise from a low level to a high level are defined as 1.sup.st to 4.sup.th time durations, respectively, wherein each of the 1.sup.st and 2.sup.nd time durations is greater than each of the 3.sup.rd and 4.sup.th time durations.

2. The gate driving circuit of claim 1, wherein the 1.sup.st to N.sup.th stage first shift registers are disposed at the one side of the display panel, and the 1.sup.st to 4.sup.th stage first dummy shift registers are disposed prior to the 1.sup.st to N.sup.th stage first shift registers.

3. The gate driving circuit of claim 1, wherein a time duration required for the 1.sup.st stage first scan signal to rise from a low level to a high level is defined as a 5.sup.th time duration, wherein each of the 1.sup.st and 2.sup.nd time durations is greater than the 5.sup.th time duration.

4. The gate driving circuit of claim 1, wherein the 1.sup.st stage first dummy shift register is configured to generate the 1.sup.st stage first dummy scan signal according to a starting signal.

5. The gate driving circuit of claim 1, wherein the 1.sup.st stage first shift register is configured to generate the 1.sup.st stage first scan signal according to at least one of the 1.sup.st to 4.sup.th stage first dummy scan signals.

6. The gate driving circuit of claim 1, wherein the 1.sup.st to 4.sup.th stage first dummy scan signals are not inputted to the plurality of first scan lines.

7. The gate driving circuit of claim 1, wherein each of the 1.sup.st to N.sup.th stage first shift registers comprises: a precharge unit configured to receive a first input signal and a second input signal and to output a control signal via a first node; a first pull-down unit coupled to the first node and configured to receive a third input signal; an output unit configured to receive a fourth input signal and the control signal and to output one of the 1.sup.st to N.sup.th stage first scan signals via a second node; and a second pull-down unit coupled to the second node and configured to receive a fifth input signal; wherein the fourth input signal and the fifth input signal are respectively two of 1.sup.st to 4.sup.th clock signals.

8. The gate driving circuit of claim 7, wherein the precharge unit comprises: a first transistor coupled to the first node and configured to receive the first input signal; and a second transistor coupled to the first node and configured to receive the second input signal.

9. The gate driving circuit of claim 7, wherein the first pull-down unit comprises: a third transistor having a third gate, a third source and a third drain, wherein the third gate is configured to receive the third input signal, one of the third source and the third drain is configured to receive a reference voltage, and the other of the third source and the third drain is coupled to the first node.

10. The gate driving circuit of claim 9, wherein the first pull-down unit further comprises: a seventh transistor having a seventh gate, a seventh source and a seventh drain, wherein the seventh gate is configured to receive a starting signal, one of the seventh source and the seventh drain is configured to receive the reference signal, and the other of the seventh source and the seventh drain is coupled to the first node.

11. The gate driving circuit of claim 7, wherein the output unit comprises: a fourth transistor having a fourth gate, a fourth source and a fourth drain, wherein the fourth gate is coupled to the first node, one of the fourth source and the fourth drain is configured to receive the fourth input signal, and the other of the fourth source and the fourth drain is coupled to the second node.

12. The gate driving circuit of claim 11, wherein the output unit further comprises: a fifth transistor having a fifth gate, a fifth source and a fifth drain, wherein the fifth gate is coupled to the second node, one of the fifth source and the fifth drain is configured to receive the fourth input signal, and the other of the fifth source and the fifth drain is coupled to the second node.

13. The gate driving circuit of claim 7, wherein the second pull-down unit comprises: a sixth transistor having a sixth gate, a sixth source and a sixth drain, wherein the sixth gate is configured to receive the fifth input signal, one of the sixth source and the sixth drain is configured to receive a reference voltage, and the other of the sixth source and the sixth drain is coupled to the second node.

14. The gate driving circuit of claim 1, further comprising: 1.sup.st to 4.sup.th stage second dummy shift registers configured to respectively generate and output 1.sup.st to 4.sup.th stage second dummy scan signals; and 1.sup.st to N.sup.th stage second shift registers configured to respectively generate and output 1.sup.st to N.sup.th stage second scan signals to the plurality of scan lines of the display panel; wherein the 1.sup.st to 4.sup.th stage second dummy scan signals are generated before the 1.sup.st stage second scan signal is generated, the 1.sup.st to 4.sup.th stage second dummy scan signals respectively have substantially the same time sequences as those of the 1.sup.st to 4.sup.th stage first dummy scan signals, and the 1.sup.st to N.sup.th stage second scan signals respectively have substantially the same time sequences as those of the 1.sup.st to N.sup.th stage first scan signals.

15. The gate driving circuit of claim 14, wherein the 1.sup.st to 4.sup.th stage first dummy shift registers and the 1.sup.st to N.sup.th stage first shift registers are disposed at the one side of the display panel, and the 1.sup.st to 4.sup.th stage second dummy shift registers and the 1.sup.st to Nth stage second shift registers are disposed at another side of the display panel, wherein the one side and the another side of the display panel are opposite to each other.

16. A display device, comprising: a display panel having a first side and a second side opposite to each other; a gate driving circuit configured to drive the display panel, the gate driving circuit comprising: 1.sup.st to 4.sup.th stage first dummy shift registers configured to respectively generate and output 1.sup.st to 4.sup.th stage first dummy scan signals, wherein the 1.sup.st to 4.sup.th stage first dummy shift registers are disposed at the first side of the display panel; and 1.sup.st to N.sup.th stage first shift registers disposed at the first side of the display panel and configured to respectively generate and output 1.sup.st to N.sup.th stage first scan signals to a plurality of scan lines of the display panel, wherein N is an integer; wherein the 1.sup.st to 4.sup.th stage first dummy scan signals are generated before the 1.sup.st stage first scan signal is generated, wherein time durations required for the 1.sup.st to 4.sup.th stage first dummy scan signals to rise from a low level to a high level are defined as 1.sup.st to 4.sup.th time durations, respectively, wherein each of the 1.sup.st and 2.sup.nd time durations is greater than each of the 3.sup.rd and 4.sup.th time durations.

17. The display device of claim 16, wherein the display device is a system on glass (SOG) display device.

18. The display device of claim 16, wherein the gate driving circuit further comprises: 1.sup.st to 4.sup.th stage second dummy shift registers configured to respectively generate and output 1.sup.st to 4.sup.th stage second dummy scan signals, wherein the 1.sup.st to 4.sup.th stage second dummy shift registers are disposed at the second side of the display panel; and 1.sup.st to N.sup.th stage second shift registers configured to respectively generate and output 1.sup.st to N.sup.th stage second scan signals to the plurality of scan lines of the display panel, wherein the 1.sup.st to N.sup.th stage second shift registers are disposed at the second side of the display panel; wherein the 1.sup.st to 4.sup.th stage second dummy scan signals are generated before the 1.sup.st stage second scan signal is generated, the 1.sup.st to 4.sup.th stage second dummy scan signals respectively have substantially the same time sequences as those of the 1.sup.st to 4.sup.th stage first dummy scan signals, and the 1.sup.st to N.sup.th stage second scan signals respectively have substantially the same time sequences as those of the 1.sup.st to N.sup.th stage first scan signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings.

(2) FIG. 1 is a schematic diagram of a display device in accordance with some embodiments of the invention.

(3) FIG. 2 is a schematic diagram of the display panel and the gate driver shown in FIG. 1.

(4) FIGS. 3A and 3B are circuit diagrams of shift register circuits in accordance with some embodiments of the invention.

(5) FIG. 4 is a time sequential diagram of the signals outputted by the gate driver in FIG. 2.

(6) FIG. 5 is a schematic diagram of a display device in accordance with some embodiments of the invention.

DETAILED DESCRIPTION

(7) The detailed explanation of the invention is described as following. The described preferred embodiments are presented for purposes of illustrations and description, and they are not intended to limit the scope of the invention.

(8) Referring to FIG. 1, which is a schematic diagram of a display device 100. The display device 100 includes a display panel 110, a source driver 120 and a gate driver 130. The display panel 110 includes pixels arranged in a matrix for collectively displaying an image. The display panel 110 may be, for example, a liquid crystal display (LCD) panel of twisted nematic (TN) mode, in-plane switching (IPS) mode, fringe-field switching (FFS) mode, vertical alignment (VA) mode or other different modes, or an organic light-emitting diode (OLED) display panel, but is not limited thereto. The source driver 120 is electrically connected to the display panel 110, and is configured to convert image data into source driving signals and transmit the source driving signals to the display panel 110. The gate driver 130 is configured to generate and transmit gate driving signals to the display panel 110. The display panel 110 displays an image by the driving of the source driving signals and the gate driving signals.

(9) FIG. 2 is a schematic diagram of the display panel 110 and the gate driver 130 shown in FIG. 1. As shown in FIG. 2, the gate driver 130 includes dummy shift registers 132(1)-132(M) and shift registers 134(1)-134(N). The dummy shift registers 132(1)-132(M) and the shift registers 134(1)-134(N) are configured to respectively generate dummy scan signals DS(1)-DS(M) and scan signals S(1)-S(N) according to at least one of a starting signal STV, clock signals C1-C4 and a reset signal RST. The starting signal STV transitions to a high level at the beginning of a frame period, the clock signals C1-C4 sequentially transition to a high level and sequentially transition to a low level during the frame period, and the reset signal RST transitions to a high level at the end of the frame period. Furthermore, the shift registers 134(1)-134(N) are configured to respectively transmit the scan signals S(1)-S(N) to scan lines (not shown) of the display panel 110. For illustration, the 1.sup.st stage shift register 134(1) is configured to generate and transmit the 1.sup.st stage scan signal S(1) to a first scan line of the scan lines, the 2.sup.nd stage shift register 134(2) is configured to generate and transmit the 2.sup.nd stage scan signal S(2) to a second scan line of the scan lines, and so on.

(10) In the invention, the dummy shift registers 132(1)-132(M) are disposed prior to the shift registers 134(1)-134(N), and the dummy scan signals DS(1)-DS(M) generated by the dummy shift registers 132(1)-132(M) are not inputted to the scan lines of the display panel 110. In addition, the dummy scan signals DS(1)-DS(M) are generated and outputted before the scan signals S(1)-S(N) are generated, and the dummy scan signals DS(1)-DS(M) and the scan signals S(1)-S(N) are sequentially generated and outputted.

(11) For facilitating description of FIGS. 3A and 3B, in the following, the dummy shift registers 132(1)-132(M) and the shift registers 134(1)-134(N) shown in FIG. 2 are respectively represented by shift registers SR(1)-SR(M+N), and the dummy scan signals DS(1)-DS(M) and the scan signals S(1)-S(N) are respectively represented by scan signals SC(1)-SC(M+N).

(12) FIGS. 3A and 3B are circuit diagrams of the shift register circuits 300A and 300B in accordance with some embodiments of the invention, respectively. The shift register circuit 300A may be a circuit in each of the shift registers SR(1)-SR(3), and the shift register circuit 300B may be a circuit in each of the shift registers SR(4)-SR(M+N).

(13) As shown in FIG. 3A, the shift register circuit 300A includes a precharge unit 310A, a first pull-down unit 320A, an output unit 330A and a second pull-down unit 340A. The precharge unit 310A is configured to receive the input signal IN1-IN2 and to output a control signal CTRL via a node X1. The first pull-down unit 320A is coupled to the precharge unit 310A, and is configured to receive the input signal IN3 and pull-down the voltage level of the node X1. The output unit 330A is coupled to the precharge unit 310A, and is configured to receive the control signal CTRL and the input signal IN4 and to output a scan signal OUT via a node X2. The second pull-down unit 340A is coupled to the first pull-down unit 320A and the output unit 330A, and is configured to receive the input signal IN5 and to reset the scan signal OUT.

(14) The precharge unit 310A includes transistors T1 and T2. The first terminal and second terminal of the transistor T1 are configured to receive an input signal IN1, and the third terminal of the transistor T1 is coupled to a node X1. The first terminal and second terminal of the transistor T2 are configured to receive an input signal IN2, and the third terminal of the transistor T2 is coupled to a node X1. In this embodiment, for each of the transistors T1-T7, the first terminal is the gate, the second terminal of the transistor is one of the source and the drain, and the third terminal of the transistor is the other of the source and the drain.

(15) The first pull-down unit 320A includes a transistor T3. The first terminal of the transistor T3 is configured to receive the input signal IN3, the second terminal of the transistor T3 is configured to receive a reference voltage Vss, and the third terminal of the transistor T3 is coupled to the node X1.

(16) The output unit 330A includes a capacitor Cx and transistors T4 and T5. The first and second terminal of the capacitor Cx are coupled to the nodes X1 and X2, respectively. The first terminal of the transistor T4 is coupled to the node X1, the second terminal of the transistor T4 is configured to receive the input signal IN4, and the third terminal of the transistor T4 is coupled to the node X2. The first terminal and third terminal of the transistor T5 are coupled to the node X2, and the second terminal of the transistor T5 is configured to receive the input signal IN4.

(17) The second pull-down unit 340A includes a transistor T6. The first terminal of the transistor T6 is configured to receive the input signal IN5, the second terminal of the transistor T6 is configured to receive the reference voltage Vss, and the third terminal of the transistor T6 is coupled to the node X2.

(18) If the shift register circuit 300A is a circuit in the shift register SR(1), the input signal IN1-IN5 are the starting signal STV, the starting signal STV, the scan signal SC(3) and the clock signals C1 and C3, respectively, and the output signal OUT is the scan signal SC(1). If the shift register circuit 300A is a circuit in the shift register SR(2), the input signal IN1-IN5 are the scan signal SC(1), the starting signal STV, the scan signal SC(4) and the clock signals C2 and C4, respectively, and the output signal OUT is the scan signal SC(2). If the shift register circuit 300A is a circuit in the shift register SR(3), the input signal IN1-IN5 are the scan signals SC(2), SC(1) and SC(5) and the clock signals C3 and C1, respectively, and the output signal OUT is the scan signal SC(3).

(19) As shown in FIG. 3B, the shift register circuit 300B includes a precharge unit 310B, a first pull-down unit 320B, an output unit 330B and a second pull-down unit 340B. The precharge unit 310B, the output unit 330B and the second pull-down unit 340B are respectively similar to the precharge unit 310A, the output unit 330A and the second pull-down unit 340A in FIG. 3A, and the description is not repeated herein.

(20) The first pull-down unit 320A includes transistors T3 and T7. The first terminal of the transistor T3 is configured to receive the input signal IN3, the second terminal of the transistor T3 is configured to receive the reference voltage Vss, and the third terminal of the transistor T3 is coupled to the node X1. The first terminal of the transistor T7 is configured to receive the input signal IN6, the second terminal of the transistor T7 is configured to receive the reference voltage Vss, and the third terminal of the transistor T7 is coupled to the node X1.

(21) If the shift register circuit 300B is a circuit in the shift register SR(i) and i is an integer greater than or equal to 4 and less than or equal to (M+N2), the input signals IN1-IN3 and IN6 are the scan signals SC(i1), SC(i2) and SC(i+2) and the starting signal STV, respectively. The input signal IN4 of the shift registers SR(4)-SR(M+N2) are in a sequential order of the clock signals C4, C1, C2 and C3, and the input signal IN5 of the shift registers SR(4)-SR(M+N2) are in a sequential order of the clock signals C2, C3, C4 and C1. For example, if (M+N2) is an integer greater than 11, the input signal IN4 of the shift registers SR(4)-SR(M+N2) are respectively C4, C1, C2, C3, C4, C1, C2, C3 . . . , and the input signal IN5 of the shift registers SR(4)-SR(M+N2) are respectively C2, C3, C4, C1, C2, C3, C4, C1 . . . Taking (M+N) being multiple of 4 as an example, if the shift register circuit 300B is a circuit in the shift register SR(M+N1), the input signal IN1-IN6 are the scan signals SC(M+N2) and SC(M+N3), the reset signal RST, the clock signals C3 and C1 and the starting signal STV, respectively. If the shift register circuit 300B is a circuit in the shift register SR(M+N), the input signal IN1-IN6 are the scan signals SC(M+N1) and SC(M+N2), the reset signal RST, the clock signals C4 and C2 and the starting signal STV, respectively. In the shift registers SR(M+N1) and SR(M+N), the clock signals corresponding to the input signals IN4 and IN5 are associated with the value of (M+N), and the relation between the input signals IN4 and IN5 and (M+N) can be known from the above description and is not repeated herein.

(22) In some embodiments, the display device 100 of the invention is a system on glass (SOG) display device; that is, the gate driver 130 is fabricated on a substrate (not shown) of the display device 100. As such, the electrical elements in the gate driver 130 (e.g. the transistor T1-T7 and/or the capacitor Cx in FIGS. 3A and 3B) and the electrical elements in the display panel 110 can be fabricated by using the same processes.

(23) FIG. 4 is a time sequential diagram of the signals outputted by the gate driver 130 in FIG. 2. The number of dummy shift registers 132(1)-132(M) is exemplified by 4 (i.e. M is equal to 4), and for simplifying description, FIG. 4 only illustrates the time sequences of the 1.sup.st stage scan signal S(1) but omits the time sequences of the 2.sup.nd-N.sup.th stage scan signals S(2)-S(N). In FIG. 4, the dummy scan signals DS(1)-DS(4) and the 1.sup.st stage scan signal S(1) sequentially start to transition from a low level to a high level at times t0-t4, and sequentially start to transition from a high level to a low level at times t2-t6. The time durations required for the dummy scan signals DS(1)-DS(4) and the 1.sup.st stage scan signal S(1) to transition from a low level to a high level are respectively t.sub.DS1, t.sub.DS2, t.sub.DS3, t.sub.DS4 and t.sub.S1, which respectively represent resistive-capacitive delays of the dummy scan signals DS(1)-DS(4) and the 1.sup.st stage scan signal S(1), where any of the time durations t.sub.DS1 and t.sub.DS2 is longer than any of the time durations t.sub.DS3 and t.sub.DS4, and any of the time durations t.sub.DS3 and t.sub.DS4 is longer than the time duration t.sub.S1.

(24) As can be seen from the time sequential diagram of FIG. 4, the time durations required for the dummy scan signals DS(1)-DS(4) and the 1.sup.st stage scan signal S(1) to transition from a low level to a high level are gradually reduced. Because the dummy scan signals DS(1)-DS(4) are not inputted to the scan lines of the display panel 110, regardless of the relationship between the time durations t.sub.DS1, t.sub.DS2, t.sub.DS3 and t.sub.DS4 and a threshold resistive-capacitive delay, if the time duration t.sub.S1 is shorter than the threshold resistive-capacitive delay, the display panel 110 is assured to be prevented from being affected by the scan signals S(1)-S(N) to display an error image.

(25) As can be seen from the above, in the invention, the design of dummy shift registers can reduce resistive-capacitive delays of scan signals inputted to a display panel, so as to prevent the display panel from displaying an error image due to overlong resistive-capacitive delays of the scan signals, thereby ensuring its image display quality and stability.

(26) It is noted that the number of dummy shift registers of the invention may be one or more and may be determined according to practical product requirements. For example, in some embodiments, the number of dummy shift registers may be even (i.e. multiple of 2); in some embodiments, the number of dummy shift registers may be 3 or more than 3; in some embodiments, the number of dummy shift registers is 4. In addition, the circuit of the dummy shift registers and the shift registers of the invention may be correspondingly designed according to practical product requirements and are not limited to those shown in FIGS. 3A and 3B.

(27) The designs of dummy shift registers in the abovementioned embodiments may also be applied to a display device with bi-directional driving. Please refer to FIG. 5, which is a schematic diagram of a display device 500. The display device 500 includes a display panel 510, a source driver 520 and gate drivers 530A and 530B. The display device 500 is similar to the display device 100 of FIG. 1. The difference between the display devices 100 and 500 is that the display device 500 includes two gate drivers (i.e. the gate drivers 530A and 530B). As shown in FIG. 5, the gate drivers 530A and 530B are disposed at the left and right sides of the display panel 510, respectively, and collectively transmit gate driving signals to the display panel 510. In another embodiment, the designs of the gate drivers 530A and 530B may be adjusted in accordance with various design requirements. The gate drivers 530A and 530B may include the same number of dummy shift registers, and the time sequences of the dummy scan signals outputted by the gate drivers 530A are respectively the same as those of the dummy scan signals outputted by the gate drivers 530B. In addition, The gate drivers 530A and 530B may include the same number of shift register and/or the same number of dummy shift registers, and the time sequences of the scan signals and/or the time sequences of the dummy scan signals outputted by the gate drivers 530A are respectively the same as those of the scan signals and/or those of the dummy scan signals outputted by the gate drivers 530B. In some embodiments, each of the gate drivers 530A and 530B includes the dummy shift registers 132(1)-132(M) and the shift registers 134(1)-134(N) shown in FIG. 2. The display panel 510 and the source driver 520 are similar to the display panel 110 and the source driver 120 of FIG. 1, respectively, and the description is not described again herein.

(28) It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims.