Optical synapse

Abstract

An integrated optical circuit for an optical neural network is provided. The integrated optical circuit is configured to process a phase-encoded optical input signal and to provide a phase-encoded output signal depending on the phase-encoded optical input signal. The phase-encoded output signal emulates a synapse functionality with respect to the phase-encoded optical input signal. A related method and a related design structure are further provided.

Claims

1. An integrated optical circuit for an optical neural network, the optical circuit being configured: to process a phase-encoded optical input signal; and to provide a phase-encoded optical output signal depending on the phase-encoded optical input signal, the phase-encoded optical output signal emulating a synapse functionality with respect to the phase-encoded optical input signal, further comprising: a reference waveguide configured to carry an optical reference signal; an input waveguide configured to receive the phase-encoded optical input signal, wherein a phase difference between the optical reference signal and the optical input signal represents the phase of the phase encoded optical input signal; an output waveguide; an optical interferometer configured to convert the optical reference signal and the optical input signal into an interference signal by superimposition; a tunable attenuator configured to perform a weighting of the interference signal into a weighted interference signal; and a phase-shifting device configured to convert the weighted interference signal into the phase-encoded optical output signal by inducing a phase shift in the optical reference signal in dependence on the weighted interference signal.

2. The integrated optical circuit according to claim 1, wherein the integrated optical circuit is configured: to convert the phase-encoded optical input signal into an amplitude-encoded signal; to perform a weighting of the amplitude-encoded signal; and to convert the weighted amplitude-encoded signal into the phase-encoded optical output signal.

3. The integrated optical circuit according to claim 1, wherein the phase-encoded optical output signal comprises a phase shift within a predefined range relative to the optical reference signal.

4. The integrated optical circuit according to claim 3, wherein the predefined range is a range between 0° and 180°.

5. The integrated optical circuit according to claim 1, wherein the optical circuit is configured to perform a variable phase shift as a function of a weighting factor of the synapse.

6. The integrated optical circuit according to claim 1, comprising a power normalization unit configured to perform a normalization of the output power of the phase-encoded optical output signal.

7. The integrated optical circuit according to claim 6, wherein the power normalization unit comprises an amplifier and a saturated absorber.

8. The integrated optical circuit according to claim 1, wherein the tunable attenuator is implemented as a tunable absorber.

9. The integrated optical circuit according to claim 1, wherein the optical interferometer comprises a single-mode interferometer or a multi-mode interferometer.

10. The integrated optical circuit according to claim 1, wherein the phase-shifting device comprises a non-linear optical material with a non-linear power-to-refractive-index conversion.

11. The integrated optical circuit according to claim 10, wherein the nonlinear material is selected from the group consisting of: BaTiO3, LiNbO3, ferroelectric perovskites, polymers with non-linear optical properties, chalcogenides and III-V compound semiconductors.

12. The integrated optical circuit according to claim 1, wherein the phase-shifting device comprises a phase change material.

13. The integrated optical circuit according to claim 12, wherein the phase change material is selected from the group consisting of: VO2, V4O7, V6O11, V2O3, V6O13, V5O9, VO, V8O15, NbO2, Ti2O3, LaCoO3, Ti3O5, SmNiO3, NdNiO3, PrNiO3, Fe3O4 and chalcogenides.

14. The integrated optical circuit according to claim 1, wherein the phase-shifting device is a plasma dispersion modulator.

15. The integrated optical circuit according to claim 1, wherein the phase-shifting device comprises: an optical cavity comprising a non-linear material; and a gate waveguide coupled to the optical cavity and configured to guide the weighted interference signal to the optical cavity and to change the refractive index of the non-linear material in dependence on the optical power of the weighted interference signal; wherein the optical cavity is configured: to receive the optical reference signal; to induce a phase shift in the optical reference signal; and to provide the phase-encoded optical output signal.

16. A method for emulating a synapse functionality, the method comprising: providing an integrated optical circuit; processing, by the integrated optical circuit, a phase-encoded optical input signal; emulating, by the integrated optical circuit, a synapse functionality with respect to the phase-encoded optical input signal; and providing, by the integrated optical circuit, a phase-encoded optical output signal, the method further comprising: carrying, by a reference waveguide, an optical reference signal; receiving, by an input waveguide, the phase-encoded optical input signal, wherein a phase difference between the optical reference signal and the optical input signal represents the phase of the phase encoded input signal; converting, by an optical interferometer, the optical reference signal and the optical input signal into an interference signal by superimposition; weighting, by a tunable attenuator, the interference signal, thereby converting it into a weighted interference signal; and converting, by a phase-shifting device, the weighted interference signal into the phase-encoded optical output signal by inducing a phase shift in the optical reference signal in dependence on the weighted interference signal.

17. The method according to claim 16, the method comprising: converting the phase-encoded optical input signal into an amplitude-encoded signal; performing a weighting of the amplitude-encoded signal; and converting the weighted amplitude-encoded signal into the phase-encoded optical output signal.

18. A design structure tangibly embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit, the design structure comprising: an optical circuit configured: to process a phase-encoded optical input signal; and to provide a phase-encoded optical output signal, the phase-encoded output signal emulating a synapse functionality with respect to the phase-encoded optical input signal, wherein the optical circuit uses a phase to encode information in an optical domain, the design structure comprising: a reference waveguide configured to carry an optical reference signal; an input waveguide configured to receive the phase-encoded optical input signal, wherein a phase difference between the optical reference signal and the optical input signal represents the phase of the phase-encoded optical input signal; an output waveguide; an optical interferometer configured to convert the optical reference signal and the optical input signal into an interference signal by superimposition; a tunable attenuator configured to perform a weighting of the interference signal into a weighted interference signal; and a phase-shifting device configured to convert the weighted interference signal into the phase-encoded optical output signal by inducing a phase shift in the optical reference signal as a function of the weighted interference signal.

19. An optical neural network, comprising: a plurality of integrated optical circuits as synapses, each of at least a subset of the integrated optical circuits being configured: to process a phase-encoded optical input signal; and to provide a phase-encoded optical output signal depending on the phase-encoded optical input signal, the phase-encoded optical output signal emulating a synapse functionality with respect to the phase-encoded optical input signal, wherein the integrated optical circuit uses a phase to encode information in an optical domain, further comprising a plurality of further integrated optical circuits as neuron circuits, each of at least a subset of the neuron circuits being configured: to process a plurality of phase-encoded optical input signals; and to provide a phase-encoded optical output signal, the phase-encoded optical output signal emulating a neuron functionality with respect to the plurality of phase-encoded optical input signals, each of at least a subset of the neuron circuits comprising: a reference waveguide configured to carry an optical reference signal; a plurality of input waveguides configured to receive the plurality of phase-encoded optical input signals, wherein phase differences between the optical reference signal and the optical input signals represent the respective phase of the respective phase encoded input signal; an output waveguide; an optical interferometer system configured: to superimpose the plurality of optical input signals and the optical reference signal into a plurality of first interference signals; to superimpose the plurality of first interference signals into a second interference signal; and a phase-shifting device configured to provide the phase-encoded optical output signal as a function of the second interference signal.

20. The optical neural network according to claim 19, each of at least a subset of the neuron circuits being configured: to convert the plurality of phase-encoded optical input signals into a plurality of amplitude-encoded signals; to combine the plurality of amplitude-encoded signals into a summation signal; and to perform a non-linear conversion of the summation signal into the phase-encoded optical output signal.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) FIG. 1 shows an optical neural network according to an embodiment of the invention;

(2) FIG. 2 shows a schematic diagram of an information encoding scheme according to an embodiment of the invention;

(3) FIG. 3 shows an enlarged view of a section of an optical neural network according to an embodiment of the invention;

(4) FIG. 4 shows an enlarged and more detailed view of the components of the neuron circuit according to an embodiment of the invention;

(5) FIG. 5 shows an enlarged and more detailed view of the components of a synapse circuit according to an embodiment of the invention;

(6) FIG. 6 illustrates schematically an example of a plurality of optical input signals as well as a corresponding reference signal;

(7) FIG. 7 illustrates schematically the superimposition of the plurality of optical input signals with the reference signal;

(8) FIG. 8 shows an enlarged and more detailed view of an embodiment of a phase shifting device of a neuron circuit according to an embodiment of the invention;

(9) FIG. 9 shows an enlarged and more detailed view of an embodiment of a phase shifting device of a synapse circuit according to an embodiment of the invention;

(10) FIG. 10 shows a block diagram of an exemplary design flow used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture; and

(11) FIG. 11 shows method steps of a method for emulating a synapse functionality.

DETAILED DESCRIPTION

(12) FIG. 1 shows an optical neural network 100 according to an embodiment of the invention. The optical neural network 100 comprises an input layer 110, a hidden layer 120 and an output layer 130. The input layer 110 comprises a plurality of input nodes 111, which are configured to receive phase encoded optical input signals and to provide the optical input signals to the hidden layer 120. The output layer 130 comprises a plurality of output nodes 131 which are configured to provide phase encoded optical output signals.

(13) The hidden layer 120 comprises a plurality of integrated optical circuits. More particularly, the hidden layer 120 comprises integrated optical circuits 10 and integrated optical circuits 20. The integrated optical circuits 10 are embodied as neurons and may be in the following also denoted as neuron circuits 10. The integrated optical circuits 20 are embodied as synapses and may be in the following also denoted as synapse circuits 20.

(14) The integrated optical circuits 10 are configured to process a plurality of phase-encoded optical input signals and to provide a phase-encoded optical output signal. The phase-encoded optical output signal emulates a neuron functionality with respect to the plurality of phase-encoded optical input signals.

(15) The integrated optical circuits 20 are configured to process a phase-encoded optical input signal and to provide a phase-encoded optical output signal. The phase-encoded optical output signal emulates a synapse functionality with respect to the phase-encoded optical input signal.

(16) Accordingly, the optical neural network 100 operates in the phase domain.

(17) This offers advantages in terms of signal restoration. In particular, the phase is decoupled from propagation losses and remains constant. Furthermore, a reduced amplitude of optical mode decays due to propagation losses can be amplified again to restore the signal.

(18) According to embodiments, weights of the synapse circuits 20 of the optical neural network 100 may be trained with a training process. The adjustment of the weights of the optical synapse circuits 20 may be done in software or hardware according to embodiments.

(19) FIG. 2 shows a schematic diagram of an information encoding scheme according to an embodiment of the invention. The x-axis denotes the phase of the phase-encoded optical input signals and the phase of the phase-encoded optical output signals of the neuron circuits 10 and of the synapse circuits 20. The y-axis denotes a corresponding information value. The phase of the phase-encoded optical input and output signals operates in a predefined range between 0° and 180° and the corresponding information value is in a range between 0 and 1.

(20) FIG. 3 shows schematically an enlarged view 300 of a section of an optical neural network according to an embodiment of the invention, e.g. of the optical neural network 100. The enlarged view 300 shows 3 synapse circuits 20 and a neuron circuit 10. The neuron circuit 10 comprises or is coupled to a reference waveguide 11. The reference waveguide 11 is configured to carry an optical reference signal S.sub.r providing a reference phase φ.sub.r. The neuron circuit 10 further comprises a plurality of input waveguides 12 configured to receive a plurality of phase-encoded optical input signals, in this example the neuron input signals N.sub.in1, N.sub.in2 and N.sub.in3. The phase difference between the optical reference signal S.sub.r and the neuron input signals N.sub.in1, N.sub.in2 and N.sub.in3 represent the respective phase of the phase encoded optical input signals. More particularly, the neuron input signals N.sub.in1, N.sub.in2 and N.sub.in3 have a phase φ.sub.n1, φ.sub.n2 and φ.sub.n3 respectively with respect to the phase φ.sub.r of the reference signal S.sub.r.

(21) The neuron circuit 10 processes the neuron input signals N.sub.in1, N.sub.in2 and N.sub.in3 and the reference signal S.sub.r and provides a phase encoded optical output signal N.sub.out having a phase φ.sub.nout.

(22) FIG. 4 shows an enlarged and more detailed view of the components of the neuron circuit 10 according to an embodiment of the invention.

(23) The neuron circuit 10 comprises an optical interferometer system 14. The optical interferometer system 14 comprises a plurality of first interferometers 14a. Each of the first interferometers 14a is configured to receive the optical reference signal S.sub.r and one of the plurality of optical input signals N.sub.in1, N.sub.in2 and N.sub.in3 and to superimpose the optical reference signal S.sub.r and one of the respective optical input signals N.sub.in1, N.sub.in2 and N.sub.in3 into a plurality of first interference signals I.sub.1, I.sub.2 and I.sub.3 respectively. The plurality of first interference signals I.sub.1, I.sub.2 and I.sub.3 form a plurality of amplitude-encoded signals. In other words, the respective amplitude of the first interference signals I.sub.1, I.sub.2 and I.sub.3 represents the information of the first interference signals I.sub.1, I.sub.2 and I.sub.3.

(24) In addition, the optical interferometer system 14 comprises a device 14b for a further processing of the first interference signals I.sub.1, I.sub.2 and I.sub.3. According to an embodiment, the device 14b may be implemented as second interferometer 14b. According to such an embodiment the second interferometer 14b is configured to receive the plurality of first interference signals I.sub.1, I.sub.2 and I.sub.3 and to superimpose the plurality of first interference signals I.sub.1, I.sub.2 and I.sub.3 into a second interference signal I.sub.4. According to another embodiment, the device 14b may be implemented as amplitude-integration device, e.g. as a photodetector. According to such an embodiment, the amplitude-integration device 14b performs an integration/summation of the plurality of first interference signals, in this example of the first interference signals I.sub.1, I.sub.2 and I.sub.3 and provides a summation signal I.sub.4 that emulates a summation/integration of the plurality of first interference signals I.sub.1, I.sub.2 and I.sub.3.

(25) The neuron circuit 10 further comprises a phase-shifting device 15 configured to provide a phase-encoded optical output signal N.sub.out in dependence on the second interference signal I.sub.4. According to embodiments, the phase shifting device 15 performs a non-linear conversion of the second interference signal I.sub.4 into the phase-encoded optical output signal N.sub.out.

(26) The phase shifting device 15 may comprise a non-linear material providing a non-linear power-to-refractive-index conversion. According to embodiments, the nonlinear material may be in particular BaTiO.sub.3. According to yet other embodiments, the phase shifting device 15 may comprise a phase change material such as VO.sub.2 or chalcogenide-based materials. According to yet other embodiments, the phase shifting device 15 may be embodied as a plasma dispersion modulator.

(27) The neuron circuit 10 further comprises a power normalization unit 16 configured to perform a normalization of the output power of the phase-encoded optical output signal N.sub.out.

(28) According to embodiments, the power normalization unit 16 comprises an amplifier 16a and a saturated absorber 16b.

(29) FIG. 5 shows an enlarged and more detailed view of the components of a synapse circuit 20 according to an embodiment of the invention.

(30) The synapse circuit 20 comprises a reference waveguide 21 configured to carry an optical reference signal S.sub.r and an input waveguide 22 configured to receive a phase-encoded optical input signal S.sub.in. A phase difference φ.sub.in between the phase φ.sub.r of the optical reference signal and the phase of the optical input signal represents the phase φ.sub.in of the phase encoded optical input signal S.sub.in. In addition, the synapse circuit 20 comprises an output waveguide 23 and an optical interferometer 24. The optical interferometer 24 is configured to convert the optical reference signal S.sub.r and the optical input signal S.sub.in into an interference signal I by superimposition. The interference signal I forms an amplitude-encoded signal. In other words, the amplitude of the interference signal I carries the information. Furthermore, the synapse circuit 20 comprises a tunable attenuator 27 configured to perform a weighting of the interference signal I into a weighted interference signal IW. The weighted interference signal IW may also be denoted as weighted amplitude-encoded signal. A phase-shifting device 25 is configured to convert the weighted interference signal IW into a phase-encoded optical output signal S.sub.out. More particularly, the phase-shifting device 25 induces a phase shift in the optical reference signal S.sub.r in dependence on the weighted interference signal IW. The induced phase shift may have a linear or a non-linear dependence on the weighted interference signal IW.

(31) The synapse circuit 20 further comprises a power normalization unit 26 configured to perform a normalization of the output power of the phase-encoded optical output signal S.sub.out.

(32) The power normalization unit 26 comprises an amplifier 26a and a saturated absorber 26b.

(33) The phase shifting device 25 may comprise a non-linear material providing a non-linear power-to-refractive-index conversion. According to embodiments, the nonlinear material may be in particular BaTiO.sub.3. According to yet other embodiments, the phase shifting device 25 may comprise a phase change material such as VO.sub.2 or chalcogenide based-materials. According to yet other embodiments, the phase shifting device 25 may be embodied as a plasma dispersion modulator.

(34) FIG. 6 illustrates schematically an example of a plurality of optical input signals as well as a corresponding reference signal. More particularly, FIG. 6 shows optical input signals N.sub.in1, N.sub.in2 and N.sub.in3 of the neuron circuit 10 as illustrated in FIG. 4 and optical input signals S.sub.in1, S.sub.in2 and S.sub.in3 of the synapse circuit 20 as illustrated in FIG. 5. In addition, a corresponding reference signal S.sub.r is shown and illustrated with a dotted line.

(35) The input signals N.sub.in3, S.sub.in3 are in phase with the reference signal S.sub.r, corresponding to an input phase φ=0°. The input signals N.sub.in2, S.sub.in2 have a 90 degree phase shift with respect to the reference signal S.sub.r and hence an input phase φ=90°. The input signals N.sub.in1, S.sub.in1 have a 180° degree phase shift with respect to the reference signal S.sub.r and hence an input phase φ=180°.

(36) FIG. 7 illustrates schematically the superimposition of the plurality of optical input signals N.sub.in1, N.sub.in2 and N.sub.in3 and S.sub.in1, S.sub.in2 and S.sub.in3 respectively with the reference signal S.sub.r.

(37) This results in a set of interference signals, namely in this example in the set comprising the interference signals I.sub.1, I.sub.2 and I.sub.3.

(38) The interference signal I.sub.3 of the input signals N.sub.in3, S.sub.in3 and the reference signal S.sub.r has the highest amplitude A3 as both superimposed signals are in-phase. The interference signal I.sub.2 of the input signals N.sub.in2, S.sub.in2 and the reference signal S.sub.r has a medium amplitude A2. The interference signal I.sub.1 of the input signals N.sub.in1, S.sub.in1 and the reference signal S.sub.r has a zero amplitude due to the opposite phase of the input signals N.sub.in1, S.sub.in1 and the reference signal S.sub.r.

(39) According to an embodiment, the phase difference of 180 degree may be mapped to an information value V=“0”, the phase difference of 90 degree to an information value V=“0.5” and the phase difference of 0 degree to an information value of V=“1”.

(40) According to another example, the phase difference of 180 degree may be mapped to an information value V=“1”, the phase difference of 90 degree to an information value V=“0.5” and the phase difference of 0 degree to an information value V=“0”.

(41) FIG. 8 shows an enlarged and more detailed view of an embodiment of a phase shifting device 15 of the neuron circuit 10 according to an embodiment of the invention.

(42) The phase shifting device 15 comprises according to this embodiment an optical cavity 801 comprising a non-linear optical material 802. The optical cavity 801 is formed by a plurality of reflectors 803. Furthermore, a gate waveguide 804 is provided and coupled to the optical cavity 801. The phase shifting device 15 is configured to guide the second interference signal 14 of the output of the second interferometer 14b via the gate waveguide 804 to the optical cavity 801. The phase shifting device 15 is further configured to change the refractive index of the non-linear material 802 in dependence on the optical power of the second interference signal 14. More particularly, the optical cavity 801 is configured to receive the optical reference signal S.sub.r via a waveguide 805 and to induce a phase shift in the optical reference signal S.sub.r. As a result, the phase shifting device 15 provides the phase-encoded optical output signal S.sub.out having a phase φ.sub.out at an output waveguide 806.

(43) FIG. 9 shows an enlarged and more detailed view of an embodiment of a phase shifting device 25 of the synapse circuit 20 according to an embodiment of the invention.

(44) The phase shifting device 25 comprises an optical cavity 901 comprising a non-linear optical material 902. The optical cavity 901 is formed by a plurality of reflectors 903. Furthermore, a gate waveguide 904 is provided and coupled to the optical cavity 901. The phase shifting device 25 is configured to guide the weighted interference signal IW from the tunable attenuator 27 (see FIG. 5) via the gate waveguide 904 to the optical cavity 901. The phase shifting device 25 is further configured to change the refractive index of the non-linear material 902 in dependence on the optical power of the weighted interference signal IW. More particularly, the optical cavity 901 is configured to receive the weighted interference signal IW and to induce a phase shift in the optical reference signal S.sub.r. As a result, the phase shifting device 25 provides the phase-encoded optical output signal S.sub.out having a phase φ.sub.out at an output waveguide 906.

(45) FIG. 10 shows a block diagram of an exemplary design flow 1000 used for example, in semiconductor IC logic design, simulation, test, layout, and manufacture. Design flow 1000 includes processes, machines and/or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and/or devices described above and shown e.g. in FIGS. 3 to 5. The design structures processed and/or generated by design flow 1000 may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).

(46) Design flow 1000 may vary depending on the type of representation being designed. For example, a design flow 1000 for building an application specific IC (ASIC) may differ from a design flow 1000 for designing a standard component or from a design flow 1000 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.

(47) FIG. 10 illustrates multiple such design structures including an input design structure 1020 that is preferably processed by a design process 1010. Design structure 1020 may be a logical simulation design structure generated and processed by design process 1010 to produce a logically equivalent functional representation of a hardware device. Design structure 1020 may also or alternatively comprise data and/or program instructions that when processed by design process 1010, generate a functional representation of the physical structure of a hardware device. Whether representing functional and/or structural design features, design structure 1020 may be generated using electronic computer-aided design (ECAD) such as implemented by a core developer/designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure 1020 may be accessed and processed by one or more hardware and/or software modules within design process 1010 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, or system such as those shown in FIGS. 3 to 5. As such, design structure 1020 may comprise files or other data structures including human and/or machine-readable source code, compiled structures, and computer-executable code structures that when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other levels of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++.

(48) Design process 1010 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown in FIGS. 1-8 to generate a Netlist 1080 which may contain design structures such as design structure 1020. Netlist 1080 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist 1080 may be synthesized using an iterative process in which netlist 1080 is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist 1080 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials on which data packets may be transmitted and intermediately stored via the Internet, or other networking suitable means.

(49) Design process 1010 may include hardware and software modules for processing a variety of input data structure types including Netlist 1080. Such data structure types may reside, for example, within library elements 1030 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 1040, characterization data 1050, verification data 1060, design rules 1070, and test data files 1085 which may include input test patterns, output test results, and other testing information. Design process 1010 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 1010 without deviating from the scope and spirit of the invention. Design process 1010 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.

(50) Design process 1010 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 1020 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 1090. Design structure 1090 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 1020, design structure 1090 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in FIGS. 3 to 5. In one embodiment, design structure 1090 may comprise a compiled, executable HDL simulation model that functionally simulates the devices shown in FIGS. 3 to 5.

(51) Design structure 1090 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 1090 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in FIGS. 1 to 8. Design structure 1090 may then proceed to a stage 1095 where, for example, design structure 1090: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.

(52) FIG. 11 shows method steps of a method for emulating a synapse functionality. The method provides an integrated optical circuit. The integrated optical circuit processes a phase-encoded optical input signal, emulates a synapse functionality with respect to the phase-encoded optical input signal and provides a phase-encoded optical output signal.

(53) More particularly, the method starts at a step 1110.

(54) At a step 1120, a reference waveguide carries an optical reference signal.

(55) At a step 1130, an input waveguide receives the phase-encoded optical input signal.

(56) At a step 1140, an optical interferometer converts the optical reference signal and the optical input signal into an interference signal by superimposition.

(57) At a step 1150, a tunable attenuator weights the interference signal and converts it into a weighted interference signal.

(58) And at a step 1160, a phase-shifting device converts the weighted interference signal into the phase-encoded optical output signal by inducing a phase shift in the optical reference signal in dependence on the weighted interference signal.

(59) The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.