Hybrid phase locked loop having wide locking range

Abstract

A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at an output signal frequency, and a phase comparator configured to compare the output signal or a signal derived from the output signal, with a reference signal at a reference signal frequency or a signal derived from the reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator. A frequency error measuring circuit produces a frequency error signal that directly represents a frequency difference between the output signal frequency and the reference signal frequency. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and providing the combined control signals to the digital controlled oscillator.

Claims

1. A digital phased lock loop comprising: a digital controlled oscillator generating an output signal at an output signal frequency or at a frequency derived from the output signal frequency; a phase comparator coupled to the digital controlled oscillator and to a reference signal at a reference signal frequency or a signal derived from the reference signal and generating a phase error signal derived from output signal and the reference signal; a first loop filter configured to produce a first control signal for the digital controlled oscillator from an output of the phase comparator; a frequency error measuring circuit coupled to the output of the phase comparator to produce a frequency error signal that directly represents a frequency difference between the output signal frequency and the reference signal frequency; a second loop filter generating a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit; and a circuit for combining the first and second control signals and providing the combined control signals to the digital controlled oscillator.

2. The digital phased lock loop of claim 1, wherein: the first loop filter comprises a proportional part producing a proportional component of the control signal, an integral part producing an integral component of the control signal, and an adder configured to receive the respective proportional and integral components at first and second inputs thereof to produce the control signal, the integral part including a delayed feedback loop normally configured to accept the integral component at an input thereof; and the second loop filter comprises a proportional part producing a proportional component of the control signal, an integral part producing an integral component of the control signal, and an adder configured to receive the respective proportional and integral components at first and second inputs thereof to produce the control signal, the integral part including a delayed feedback loop normally configured to accept the integral component at an input thereof.

3. The digital phase locked loop of claim 1, wherein: the delayed feedback loop in the first and second loop filters each comprise a unit delay memory.

4. The digital phase locked loop of claim 1, wherein: the frequency error measuring circuit is configured to count the number of phase transitions n in a fixed time window having an interval t, the frequency error signal being equal to n/t.

5. The digital phase locked loop of claim 1, wherein: the frequency error measuring circuit is configured to determine the periodicity of the phase difference between the output signal and the reference signal, the frequency error signal being equal to the inverse of the determined periodicity.

6. A method of reducing the convergence time in a digital phase locked loop, comprising: generating an output signal from a digitally controlled oscillator; comparing the output signal or a signal derived from the output signal with a reference signal or a signal derived from the reference signal to produce a phase error signal; filtering the phase error signal in a first loop filter having a proportional part producing a proportional component and an integral part producing an integral component, the integral part including a delayed feedback loop normally receiving at an input thereof the integral component; applying the proportional and integral components to respective first and second inputs of an adder to produce a first control signal; comparing the frequency of the output signal with the frequency of the reference signal, or a signal derived therefrom to produce a frequency error signal that directly represents frequency difference between the output signal frequency and the reference signal frequency; filtering the frequency error signal in a second loop filter having a proportional part producing a proportional component and a integral part producing an integral component, the integral part including a delayed feedback loop normally receiving at an input thereof the integral component; and combining the first and second control signals and providing the combined control signals to the digital controlled oscillator.

7. The method of claim 6 wherein comparing the frequency of the output signal with the frequency of the reference signal, or a signal derived therefrom comprises: counting the number of phase transitions n in a fixed time window having an interval t; and setting the frequency error signal equal to n/t.

8. The method of claim 6 wherein comparing the frequency of the output signal with the frequency of the reference signal, or a signal derived therefrom comprises: determining the periodicity of the phase difference between the output signal and the reference signal; and setting the frequency error signal being equal to the inverse of the determined periodicity.

Description

DRAWINGS

(1) These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:

(2) FIG. 1 is a block diagram of a typical prior-art DPLL;

(3) FIG. 2 is a block diagram of a typical loop filter used in the phase correction loop of a DPLL of the prior art;

(4) FIG. 3 is a block diagram of a phase locked loop in accordance with the principles of the present invention;

(5) FIG. 4 is a diagram of the DPLL of FIG. 3, showing the loop filters in more detail;

(6) FIGS. 5A, 5B, and 5C are diagrams explaining the measurement of frequency from phase in accordance with one aspect of the present invention.

DESCRIPTION

(7) Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

(8) A particular embodiment of the present invention is shown in FIG. 3, a block diagram of an illustrative DPLL 40 in accordance with the principles of the present invention. Certain ones of the components of DPLL 40 are similar in form and function to components in the prior-art DPLL 10 depicted in FIG. 1. These components will be referred to using the same reference numerals used to designate their counterparts in FIG. 1.

(9) DPLL 40 includes a phase comparator 12, a phase loop filter 14, and a digital controlled oscillator (DCO) 16. Phase comparator 12 compares the phase of a reference clock ref (or a reference clock divided by 1/M in frequency divider 18) and the output of the local DCO 16 or some derivative thereof, for example, a fraction thereof (through 1/N frequency divider 20), potentially with some preset offset, with the phase error err being the output of phase comparator 12. It will be understood that the whole circuit operates under the control of a system clock (not shown).

(10) Phase loop filter 14 includes a P component 14-22 and I component 14-24 similar to those depicted in FIG. 2, or any other prior art DPLL arrangement, including the DPLL taught in U.S. Pat. No. 6,236,343 issued May 22, 2001 to Patapoutian, entitled Loop Latency Compensated PLL Filter, the entire contents of which is incorporated herein by reference. Irrespective of arrangement, the output of phase loop filter 14 comprises a signal which in the prior art is fed to DCO 16 to lock the output of DCO 16 to the reference signal.

(11) Referring now to FIG. 4, in the P component of phase loop filter 14, multiplier 14-26 multiplies the output err of the phase comparator that comprises phase error measurement element 12 by the scaling factor K.sub.P. The phase error signal err is further provided to the I component 14-24 including multiplier 14-28 having the integral factor K.sub.I as an input. An integrator consisting of adder 14-30 and memory 14-32 with a unit delay forms part of a delayed feedback loop. The multiplier 14-26 produces a phase compensation component dfp.sub.a and the multiplier 14-28 and integrator (adder 14-30 and memory 14-32) produce an integral component dfi.sub.a, representing a phase offset relative to the reference clock ref. The components dfp.sub.a and dfi.sub.a are further summed in adder 14-34 to produce a first control signal df.sub.a which is arranged to set the frequency of the DCO 14 so that it becomes locked in phase to the reference clock ref.

(12) The memory 14-32 stores the value of the frequency component dfi.sub.a for one cycle so that the current input dfi.sub.a to the adder 14-34 is (previous cycle dfi.sub.a)+K.sub.I*dfp.sub.a (current cycle). Consequently the first control signal dfa at the output of the adder 14-34 is given by df.sub.a=dfp.sub.a (current cycle)+dfi.sub.a (previous cycle)+K.sub.I*dfp.sub.a (current cycle).

(13) The loop bandwidth for phase loop filter 14 is generally set by user and is determined by the scaling factor K.sub.P, which is typically set to be: K.sub.P=2f/fsys, where f is the phase loop bandwidth and fsys is the system clock for the DPLL phase loop. The multiplier 14-22 will give an instantaneous PLL update value dfp. The scaling factor K.sub.I, which is input to the multiplier 14-28, maintains the filter integral part at a very low rate in relation to the instantaneous PLL update value dfp.sub.a and in general: K.sub.I=K.sub.P/D, where D>>1 is a damping factor.

(14) According to one aspect of the present invention, a second control loop for the DPLL 40 including frequency error measurement element 42 and frequency loop filter 44 corrects for frequency offset. Adder 46 combines the outputs of loop filter 16 and loop filter 42. The second control loop cooperates to improve locking when the frequency difference is larger than the phase loop bandwidth.

(15) Frequency loop filter 44 includes a P component 44-22 and I component 44-24 similar to those of phase loop filter 14. In the P component of frequency loop filter 44, multiplier 44-26 multiplies the output of the frequency error measurement 42 by the scaling factor K.sub.P. The frequency error signal is provided to the I component 44-24 including multiplier 44-28 having the integral factor K.sub.I as an input. An integrator consisting of adder 44-30 and memory 44-32 with a unit delay forms part of a delayed feedback loop. The multiplier 44-26 produces a frequency compensation component dfp.sub.b and the multiplier 44-28 and integrator (adder 44-30 and memory 44-32) produce an integral component dfi.sub.b, representing a frequency offset relative to the frequency of the reference clock ref. The components dfp.sub.b and dfi.sub.b are further summed in adder 44-34 to produce a second control signal df.sub.b which is arranged to set the frequency of the DCO 14 so that it becomes locked to the reference clock ref.

(16) The memory 44-32 stores the value of the frequency component dfi.sub.b for one cycle so that the current input dfi.sub.b to the adder 44-34 is (previous cycle dfi.sub.b)+K.sub.I*dfp.sub.b (current cycle). Consequently the second control signal df.sub.b at the output of the adder 44-34 is given by df.sub.b=dfp.sub.b (current cycle)+dfi.sub.b (previous cycle)+K.sub.I*dfp.sub.b (current cycle).

(17) The loop bandwidth for frequency loop filter 44 is generally set by user and is determined by the integral factor K.sub.Ip. The multiplier 44-26 will give an instantaneous PLL update value dfp. The integral factor K.sub.I, which is input to the multiplier 44-28, maintains the filter integral part at a very low rate in relation to the instantaneous PLL update value dfp and in general: K.sub.I=K.sub.P/D, where D>>1 is a damping factor.

(18) The outputs of phase loop filter 14 and frequency loop filter 44 are summed in adder 46, to provide a combined control signal for DCO 14. The addition of second control signal dfb from frequency loop filter 44 allows the system to lock over a wider frequency range than would be possible if only phase loop filter 14 was used.

(19) Referring now to FIGS. 5A, 5B, and 5C, diagrams explain the measurement of frequency from phase in accordance with one aspect of the present invention, as performed by frequency error measurement element 42. The upper trace in both FIGS. 5A and 5B show the reference frequency signal and the DCO output signal superimposed, the reference signal being the trace shown lower on the y-axis in the upper portions of FIGS. 5A and 5B. The lower of the two superimposed traces in both FIGS. 5A and 5B shows the phase difference between the reference frequency signal and the DCO output signal.

(20) The phase difference between the reference signal and the feedback signal from the DCO is measured by counting the number of system clock cycles between the rising edge of the reference signal and the rising edge of the feedback signal. The measurement is performed after the optional frequency dividers 18 and 20. The phase difference measured this way has a different pattern when the feedback signal frequency is lower than that of reference signal (FIG. 5A) and when feedback signal frequency is higher than that of reference signal (FIG. 5B).

(21) The periodicity of phase difference (number of cycles per second) directly represents the frequency difference between the reference clock signal ref and the feedback signal. The frequency difference can be computed by measuring T as shown in FIG. 5A and calculating 1/T. This process involves a division which is resource and time consuming.

(22) The frequency difference can also be found by counting the number of phase transitions in a fixed time window as shown in FIG. 5C. If the measuring window is 10 milliseconds and number of phase transitions are 8 then the frequency is 8/0.01=800, where 1/0.01 is a fixed factor and hence division is not required because both numerator and denominator can be multiplied by a number that makes the denominator equal to 1.

(23) One way to find if the frequency difference is positive or negative is to find the difference between the present value of phase difference and the most immediately previous value of phase difference. If the difference is positive (except at transitions where difference value is too large and is not considered) then the frequency difference is positive. If the difference is negative, then the frequency difference is negative.

(24) The addition of a loop filter for frequency raises the challenge of tuning two closed loop controllers to control a single system. However, by properly tuning the loop filters of the phase loop and the frequency loops the locking range of the PLL is increased by many times compared to the PLL of the prior art. The phase loop is preferably tuned such that the locking frequency range of the phase loop is equal to, or greater than, the frequency resolution (minimum frequency change that can be measured) of the error measurement element 42. Also the dynamic response of the frequency loop filter 44 should be slower than that of phase loop filter 14. The integrator in the frequency loop filter 44 plays a major role in defining its dynamics.

(25) Although the present invention has been discussed in considerable detail with reference to certain preferred embodiments, other embodiments are possible. Therefore, the scope of the appended claims should not be limited to the description of preferred embodiments contained in this disclosure.