Nanowire device having graphene top and bottom electrodes and method of making such a device

Abstract

A composition of matter comprising a plurality of nanowires on a substrate, said nanowires having been grown epitaxially on said substrate in the presence of a metal catalyst such that a catalyst deposit is located at the top of at least some of said nanowires, wherein said nanowires comprise at least one group III-V compound or at least one group II-VI compound or comprises at least one non carbon group IV element; and wherein a graphitic layer is in contact with at least some of the catalyst deposits on top of said nanowires.

Claims

1. A device, comprising: a plurality of epitaxial nanowires on a substrate, the plurality of epitaxial nanowires having been grown epitaxially on the substrate in the presence of a metal catalyst such that a catalyst deposit is located at the top of at least some of the plurality of epitaxial nanowires, wherein the plurality of epitaxial nanowires comprise at least one Group III-V compound; wherein the substrate comprises graphene, graphane, or graphene oxide; wherein the substrate has a thickness of 20 nm or less; wherein the plurality of epitaxial nanowires have been grown in the [111] or [0001] direction; and wherein a graphitic layer is in contact with at least some of the catalyst deposits on top of at least some of the plurality of epitaxial nanowires.

2. The device of claim 1, wherein the plurality of epitaxial nanowires comprise AlAs, AlN, GaSb, GaP, GaN, GaAs, InP, InN, InGaAs, InGaN, InAs, AlGaAs, AlGaN, or AlInGaN.

3. The device of claim 1, wherein the graphene, graphane, or graphene oxide comprises 10 or fewer atomic layers.

4. The device of claim 1, wherein the substrate and/or the graphitic layer is a laminated substrate exfoliated from a Kish graphite, a highly ordered pyrolytic graphite, or CVD-grown graphene layers on metallic films or foils.

5. The device of claim 1, wherein the substrate and/or the graphitic layer is a CVD-grown graphene layer on a Cu or Pt film.

6. The device of claim 1, wherein the substrate and/or the graphitic layer is flexible and transparent.

7. The device of claim 1, wherein the substrate's surface and/or the graphitic layer is modified with a plasma treatment with a gas of oxygen, hydrogen, NO, or their combinations.

8. The device of claim 1, wherein the substrate's surface and/or the graphitic layer is modified by doping using a solution of FeCl.sub.3, AuCl.sub.3, or GaCl.sub.3.

9. The device of claim 1, wherein the substrate's surface and/or the graphitic layer is doped by adsorption of organic or inorganic molecules.

10. The device of claim 9, wherein the substrate's surface and/or the graphitic layer is doped by adsorption of metal-chlorides, NO.sub.2, HNO.sub.3, aromatic molecules, or ammonia.

11. The device of claim 9, wherein the substrate's surface and/or the graphitic layer is doped by a substitutional doping method during its growth with incorporation of a dopant, wherein the dopant is B, N, S, or Si.

12. The device of claim 1, wherein the plurality of epitaxial nanowires are no more than 500 nm in diameter and have a length of up to 5 ?m.

13. The device of claim 1, wherein the plurality of epitaxial nanowires are substantially parallel to each other.

14. The device of claim 1, wherein the catalyst is Au or Ag.

15. The device of claim 1, wherein the graphitic layer is graphene.

16. The device of claim 1, wherein the graphitic layer is doped with doping ions and the plurality of epitaxial nanowires are doped with the same doping ions.

17. A process for the preparation of the device of claim 1, comprising: (I) providing Group III-V elements to a surface of the substrate using a molecular beam; (II) epitaxially growing the plurality of epitaxial nanowires from the surface of the substrate in the presence of the metal catalyst such that the catalyst deposit remains on top of at least some of the plurality of epitaxial nanowires; and (III) contacting the metal catalyst deposits with the graphitic layer such that the graphitic layer is in contact with at least some of the catalyst deposits on top of at least some of the plurality of epitaxial nanowires.

18. The process of claim 17, wherein the substrate is coated with a hole-patterned mask.

19. The process of claim 18, wherein the catalyst is introduced on to the substrate surface exposed via the hole pattern.

20. The process of claim 18, wherein the hole-patterned mask comprises at least one insulating material chosen from SiO.sub.2, Si.sub.3N.sub.4, HfO.sub.2, or ANO deposited by e-beam evaporation, CVD, PE-CVD, sputtering, or ALD.

21. The process of claim 18, wherein the surface of the substrate exposed through the hole pattern is modified with a plasma treatment with a gas of oxygen, hydrogen, NO.sub.2, or their combinations.

22. The process of claim 17, wherein the graphitic layer is subjected to a post-annealing process.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) FIG. 1a-d shows the atomic arrangements when atoms are placed on 1) H- and B-sites (FIGS. 1a, b, and d), and 2) H- or B-sites (FIG. 1c). In FIG. 1e the bandgap energies of the III-V semiconductors (as well as Si and ZnO) are plotted against their lattice constants. Vertical solid (dashed) coloured lines depict the lattice constant of an ideal crystal that would give perfect lattice match with graphene for a cubic (hexagonal) crystal with the four different atomic arrangements (FIG. 1a-d) with respect to graphene. The plot visualizes the vast possibilities for epitaxial growth of vertical semiconductor nanowires on graphitic substrates. In the case of some semiconductors, the lattice mismatch with graphene is very small (e.g. InAs, GaSb, and ZnO) for one suggested atomic configuration. For other semiconductors like GaAs, the lattice mismatch is quite large and in-between two different atomic configurations (as in FIG. 1b or FIG. 1c).

(2) FIG. 2 shows a MBE experimental set up.

(3) FIG. 3a is an idealised depiction of Ga (self) catalysed GaAs nanowires grown on graphite.

(4) FIG. 3b is a 45? tilted view SEM image of two vertical Ga assisted GaAs nanowires grown by MBE on a flake of Kish graphite. The spherical particles are Ga droplets.

(5) FIG. 3c is a cross sectional TEM image of the graphite/nanowire interface of a vertical Ga-assisted GaAs nanowire grown epitaxially on top of Kish graphite.

(6) FIG. 4 shows a depiction of a mask on the graphite surface, which has been etched with holes.

(7) FIG. 5a shows a schematic image of semiconducting nanowires grown by a metal catalyst-assisted vapour-liquid-solid (VLS) method. The substrate is graphene deposited on a SiO.sub.2 substrate.

(8) FIG. 5b shows a schematic image as in FIG. 5a but here with graphene as a top contact material. It can be also envisaged as a nanowire solar cell with the two graphene layers as the two terminals.

(9) FIG. 6a shows a tilted view SEM image of Ga-assisted GaAs nanowire arrays grown on a Si(111) substrate by MBE.

(10) FIG. 6b shows a SEM image of GaAs nanowire arrays covered with a graphene layer deposited on top. The nanowire arrays were grown as in FIG. 6a.

(11) FIG. 6c shows a magnified SEM image of GaAs nanowire arrays covered with a graphene layer partially deposited on top. The nanowire arrays were grown as in FIG. 6a.

EXAMPLE 1

Experimental Procedure for Growing Vertical Nanowires on Graphitic Substrates

(12) Nanowires were grown in a Varian Gen II Modular molecular beam epitaxy (MBE) system equipped with a Ga dual filament cell, an In SUMO dual filament cell, and an As valved cracker cell, allowing to fix the proportion of dimers and tetramers. In the present study, the major species of arsenic were As.sub.4. Growth of NWs is performed either on a Kish graphite flake or on a graphene film (1 to 7 monolayers thick) grown by a chemical vapor deposition (CVD) technique directly on a Ni or Pt film deposited on an oxidized silicon wafer. The samples were prepared using two different procedures. In the first procedure, the samples were cleaned by iso-propanol followed by a blow dry with nitrogen, and then In-bonded to the silicon wafer. In the second procedure, a ?30 nm thick SiO.sub.2 layer was deposited in an electron-beam evaporator chamber on the samples prepared using the first procedure where after holes of ?100 nm in diameter were fabricated in the SiO.sub.2 using electron-beam lithography and plasma etching.

(13) The samples were then loaded into the MBE system for the nanowire growth. The substrate temperature was then increased to a temperature suitable for GaAs/InAs nanowire growth: i.e. 610? C./450? C., respectively. The Ga/In flux was first supplied to the surface during a time interval typically in the range 5 s to 10 minutes, dependent on Ga/In flux and desired droplet size, while the As shutter was closed, to initiate the formation of Ga/In droplets on the surface. GaAs/InAs nanowire growth was initiated by simultaneously opening the shutter of the Ga/In effusion cell and the shutter and valve of the As effusion cell. The temperature of the Ga/In effusion cell was preset to yield a nominal planar growth rate of 0.1 ?m per hour. To form the GaAs nanowires, an As.sub.4 flux of 1.1?10.sup.?6 Torr is used, whereas the As.sub.4 flux is set to 4?10.sup.?6 Torr to form InAs nanowires.

EXAMPLE 2

Experimental Procedure for Growing Vertical GaAs Nanowires on GaAs (111)B or Si(111) Substrates

(14) For growing Au-catalyzed GaAs nanowires on GaAs (111)B substrates, the substrate surface was first deoxidized at 620? C. and then a 60 nm thick GaAs film was grown under growth conditions producing an atomically flat surface in the MBE system. It was transferred to an electron-beam evaporator for thin Au film deposition. The sample was then loaded into the MBE system again for nanowire growth. As.sub.4 was used as the major species for As source. Under an As.sub.4 flux of 6?10.sup.?6 Torr, the substrate temperature was increased to 540? C. for GaAs nanowire growth. At this stage, thin Au film turned into Au particles and alloyed with the Ga from the substrate forming AuGa liquid particles. GaAs nanowire growth was initiated by opening the shutter of the Ga effusion cell. The temperature of the Ga effusion cell was preset to yield a nominal planar GaAs growth rate of 0.7 MLs.sup.?1. Growth of GaAs nanowires was always terminated by shutting down the Ga and As fluxes, and immediately ramping down the substrate to room temperature.

(15) For the growth of Ga self-catalyzed GaAs nanowires on Si(111) substrates, the Si substrates were etched in HF (5%) for 10 sec to remove the native oxide, rinsed in deionized water for 1 min, dried by blowing N.sub.2 gas, and then directly loaded inside the MBE chamber. The major As specie used was As.sub.4. The substrates were ramped up to the growth temperature of 620? C. The GaAs nanowire growth started by opening the Ga and As shutters simultaneously. The GaAs nanowire growth was initiated by simultaneously opening the shutter of the Ga effusion cell and the shutter and valve of the As effusion cell.

EXAMPLE 3

Experimental Procedure for Transferring the Graphitic Layers on Top of Nanowire Arrays

(16) Graphitic layers (<5 layers) grown on Cu foils were used. Since graphitic layers are formed on both sides of Cu foil during CVD growth, the graphitic layers formed on one side were removed by oxygen plasma to expose the Cu for etching. This was then dipped in a dilute iron nitrate (Fe(NO.sub.3).sub.3) solution (<5%) to etch Cu away completely. After etching overnight (>8 hrs), the graphitic layers were floated on the etching solution, which were exchanged into deionised water. After further rinsing with deionised water several times, the graphitic layers were transferred on the nanowire arrays with deionised water. Deionised water was dried naturally in a clean room without any N.sub.2 blow.