Surge protection device and telecommunication equipment comprising the same

Abstract

The present disclosure provides a surge protection device comprising a surge arrestor and an arrestor assistor. The surge arrestor is arranged within a circuit branch connected in parallel with a load and adapted to clamp a load voltage to a clamping voltage not larger than a load voltage limit when the load voltage rises to a breakdown voltage of the surge arrestor, the breakdown voltage increasing with a rising rate of the load voltage. The arrestor assistor is connected in parallel with the surge arrestor within the circuit branch and adapted to make the load voltage rise to the breakdown voltage not larger than the load voltage limit. The present disclosure also provides a telecommunication equipment comprising the surge protection device.

Claims

1. A surge protection device, comprising: a surge arrestor, arranged within a circuit branch connected in parallel with a load, and adapted to clamp a load voltage (V.sub.load) to a clamping voltage (V.sub.clamp) not larger than a load voltage limit (V.sub.limit) when the load voltage (V.sub.load) rises to a breakdown voltage (V.sub.A1TH) of the surge arrestor, the breakdown voltage (V.sub.A1TH) increasing with a rising rate of the load voltage (V.sub.load); and an arrestor assistor, connected in parallel with the surge arrestor within the circuit branch, and adapted to allow the load voltage (Vload) to rise to the breakdown voltage (V.sub.A1TH) not larger than the load voltage limit (V.sub.limit), the arrestor assistor comprising: a transient voltage suppressor (TVS) diode having a clamping voltage (V.sub.CTVS) not larger than the load voltage limit (V.sub.limit) and a reverse breakdown voltage (V.sub.BRTVS) less than the clamping voltage (V.sub.CTVS), wherein the TVS diode prevents the load voltage (V.sub.load) from exceeding the clamping voltage (V.sub.CTVS) and thus suppresses the rising rate of the load voltage (V.sub.load) when the load voltage (V.sub.load) rises to the reverse breakdown voltage (V.sub.BRTVS); and a semiconductor switch connected in series with the TVS diode, wherein the semiconductor switch is turned off when the load voltage (V.sub.load) rises to the breakdown voltage (V.sub.A1TH) of the surge arrestor and is turned on when the load voltage (V.sub.load) drops to a normal operation voltage (V.sub.NORMAL) not larger than the clamping voltage (V.sub.clamp).

2. The surge protection device of claim 1, wherein the breakdown voltage (V.sub.A1TH) has a minimum value (V.sub.A1TH.sub._.sub.DC) not larger than the load voltage limit (V.sub.limit).

3. The surge protection device of claim 1, wherein the arrestor assistor is further adapted to cut off a current flowing through it when the load voltage (V.sub.load) rises to the breakdown voltage (V.sub.A1TH) of the surge arrestor.

4. The surge protection device of claim 1, wherein the arrestor assistor further comprises: a voltage monitor adapted to monitor the load voltage; and a switch driver adapted to turn off the semiconductor switch when the voltage monitor monitors that the load voltage (V.sub.load) rises to the breakdown voltage (V.sub.A1TH) of the surge arrestor and to turn on the semiconductor switch when the voltage monitor monitors that the load voltage (V.sub.load) drops to the normal operation voltage (V.sub.NORMAL) not larger than the clamping voltage (V.sub.clamp).

5. The surge protection device of claim 1, further comprising: another surge arrestor, having a breakdown value (V.sub.A2TH) being ignorable as compared with the breakdown value (V.sub.A1TH) of the surge arrestor and connected in series with the surge arrestor and the assistor within the circuit branch.

6. The surge protection device of claim 1, wherein the surge arrestor is a Gas Discharge Tube (GDT) or a spark gap.

7. The surge protection device of claim 5, wherein the other surge arrestor is a varistor.

8. The surge protection device of claim 1, wherein the semiconductor switch consists of at least one transistor.

9. The surge protection device of claim 8, wherein the transistor is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT) or a Bipolar Junction Transistor (BJT).

10. The surge protection device of claim 1, wherein a Surface Mount Technology (SMT) is used for mounting components of the arrestor assistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other objects, features, and advantages of the present disclosure will become apparent from the following descriptions on embodiments of the present disclosure with reference to the drawings, in which:

(2) FIG. 1 is a diagram illustrating an arrangement of a prior art two-stage SPD;

(3) FIG. 2 is a diagram illustrating a requirement for miniaturizing telecommunication equipments and an SPD dimension limitation;

(4) FIG. 3 is a diagram illustrating an arrangement of a prior art single-stage SPD;

(5) FIG. 4 is a plot illustrating different responses of the prior art single-stage SPD to gentle and steep voltage impulses;

(6) FIG. 5 is a plot illustrating a response of the prior art single-stage SPD to a steep voltage impulse;

(7) FIG. 6 is a plot illustrating how a peak load voltage and a triggering delay may change with a peak current level of a lightning strike for the prior art single-stage SPD;

(8) FIG. 7 is a diagram illustrating an arrangement of a single-stage SPD according to a first embodiment of the present disclosure;

(9) FIG. 8 is a plot illustrating a comparison between performances of the prior art single-stage SPD and the single-stage SPD according to the present disclosure responsive to a steep voltage impulse;

(10) FIG. 9 is a plot illustrating an improvement of the single-stage SPD according to the present disclosure in suppressing a peak load voltage as compared with the prior art single-stage SPD;

(11) FIG. 10 is a diagram illustrating an arrangement of a single-stage SPD according to a second embodiment of the present disclosure;

(12) FIG. 11 is a diagram illustrating an arrangement of a single-stage SPD according to a third embodiment of the present disclosure;

(13) FIG. 12 is a diagram illustrating an arrangement of a single-stage SPD according to a fourth embodiment of the present disclosure;

(14) FIG. 13 is a diagram illustrating an arrangement of a single-stage SPD according to a fifth embodiment of the present disclosure; and

(15) FIG. 14 is a diagram illustrating an arrangement of a telecommunication equipment according to the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

(16) Hereinafter, the present disclosure is described with reference to embodiments shown in the attached drawings. However, it is to be understood that those descriptions are just provided for illustrative purpose, rather than limiting the present disclosure. Further, in the following, descriptions of known structures and techniques are omitted so as not to unnecessarily obscure the concept of the present disclosure.

(17) Initially, a simply-structured single-stage SPD 700 according to a first embodiment of the disclosure will be described with respect to FIG. 7. As illustrated, the SPD 700 comprises a surge arrestor A1 and an arrestor assistor C1. The surge arrestor A1 is arranged within a circuit branch connected in parallel with a load and adapted to clamp a load voltage V.sub.load to a clamping voltage V.sub.clamp not larger than a load voltage limit V.sub.limit when the load voltage V.sub.load rises to a breakdown voltage V.sub.A1TH of the surge arrestor A1, the breakdown voltage V.sub.A1TH increasing with a rising rate of the load voltage V.sub.load. The arrestor assistor C1 is connected in parallel with the surge arrestor A1 within the circuit branch and adapted to make the load voltage V.sub.load rise to the breakdown voltage V.sub.A1TH not larger than the load voltage limit V.sub.limit.

(18) With the arrestor assistor C1 connected in parallel with the surge arrestor A1 and adapted to make the load voltage V.sub.load rise to the breakdown voltage V.sub.A1TH of the surge arrestor A1 under or at the load voltage limit V.sub.limit, the risk for the impulse breakdown voltage V.sub.ATH.sub._.sub.Imp and hence the load voltage V.sub.load to exceed the load voltage limit V.sub.limit can be thoroughly eliminated.

(19) Furthermore, since the arrestor assistor C1 directly acts on the load voltage V.sub.load to control its rising instead of indirectly instructing the surge arrestor A1 to clamp the load voltage V.sub.load via an external triggering signal, no communication occurs between the surge arrestor A1 and the arrestor assistor C1. Accordingly, the SPD 700 can be simply structured and reliable.

(20) For a performance comparison between the prior art single-stage SPD and the proposed single-stage SPD 700, FIG. 8 depicts responses of both single-stage SPDs to a steep voltage impulse. As illustrated by the dashed line in FIG. 8, the prior art single-stage SPD cannot clamp the load voltage V.sub.load to the clamping voltage V.sub.clamp until it rises to a peak value P1, which is much higher than the load voltage limit V.sub.limit and may cause damage to the load. In contrast, as illustrated by the solid line in FIG. 8, the proposed SPD 700 clamps the load voltage V.sub.load to the clamping voltage V.sub.clamp when it rises to a peak value P2 not larger than the load voltage limit V.sub.limit. As such, the load is free from overvoltage and damage caused thereby.

(21) According to the indication of the solid line in FIG. 9, the proposed SPD 700 can effectively keep the peak load voltage not higher than the load voltage limit (say 200V) for a wide range of peak lighting strike currents including those higher than 200 A. This is a significant improvement as compared with the prior art single-stage SPD, which can only handle a narrow range of peak lighting strike excluding those higher than 250 A as indicated by the dashed line in FIG. 9.

(22) As an illustrative rather than restrictive implementation, a Gas Discharge Tube GDT or a spark gap having a minimum breakdown voltage (i.e., DC breakdown voltage V.sub.A1TH.sub._.sub.DC) not larger than the load voltage limit V.sub.limit may be used as the surge arrestor A1. The arrestor assistor C1 may comprise a transient voltage suppressor TVS diode T1 having a clamping voltage V.sub.CTVS not larger than the load voltage limit V.sub.limit and a reverse breakdown voltage V.sub.BRTVS less than the clamping voltage V.sub.CTVS.

(23) With such a configuration, when the load voltage V.sub.load in response to a steep voltage impulse applied on the load rises to the reverse breakdown voltage V.sub.BRTVS (which is illustratively denoted in FIG. 8 as point b), the TVS diode T1 immediately acts on the load voltage V.sub.load to prevent the load voltage V.sub.load from exceeding the clamping voltage V.sub.CTVS. As a result, the rising rate of the load voltage V.sub.load is suppressed, and the breakdown voltage V.sub.A1TH of the surge arrestor A1 falls towards the DC breakdown voltage V.sub.A1TH.sub._.sub.DC. At a certain point (which is illustratively denoted in FIG. 8 as P2), the breakdown voltage V.sub.A1TH falls below the load V.sub.limit and the load voltage V.sub.load rises to the breakdown voltage V.sub.A1TH. Accordingly, the load voltage V.sub.load is clamped by the surge arrestor A1 to the clamping voltage V.sub.clamp which causes no damage to the load.

(24) In this regard, the transient voltage suppressor TVS diode T1 makes the load voltage V.sub.load rise to the breakdown voltage V.sub.A1TH under or at the load voltage limit V.sub.limit, by preventing the load voltage V.sub.load from exceeding the load voltage limit V.sub.limit and accordingly enabling the breakdown voltage V.sub.A1TH of the surge arrestor A1 to fall below the load voltage limit V.sub.limit.

(25) Further, as compared with using only one high-performance TVS diode to protect the load, the above solution of using an adequate TVS diode in combination with a GDT or a spark gap significantly lowers the manufacturing cost of the SPD.

(26) In one implementation, the arrestor assistor C1 may be further adapted to cut off a current flowing through it when the load voltage V.sub.load rises to the breakdown voltage V.sub.A1TH of the surge arrestor A1. In this manner, the work time of the arrestor assistor C1 may be shortened, the lifespan of the arrestor assistor C1 may be lengthened, and the performance requirements for the arrestor assistor C1 may be loosened.

(27) As an example of the above implementation, the arrestor assistor C1 may further comprise a semiconductor switch S1 connected in series with the TVS diode T1, according to a second embodiment of the present disclosure as illustrated in FIG. 10. The semiconductor switch S1 may be turned off when the load voltage V.sub.load rises to the breakdown voltage V.sub.A1TH of the surge arrestor A1 and may be turned on when the load voltage V.sub.load drops to a normal operation voltage V.sub.NORMAL not larger than the clamping voltage V.sub.clamp.

(28) According to a third embodiment of the present disclosure as illustrated in FIG. 11, the arrestor assistor C1 may further comprise a voltage monitor M1 and a switch driver D1. The voltage monitor M1 may be adapted to monitor the load voltage V.sub.load. The switch driver D1 may be adapted to turn off the semiconductor switch S1 when the voltage monitor M1 monitors that the load voltage V.sub.load rises to the breakdown voltage V.sub.A1TH of the surge arrestor A1 and to turn on the semiconductor switch S1 when the voltage monitor M1 monitors that the load voltage V.sub.load drops to a normal operation voltage V.sub.NORMAL not larger than the clamping voltage V.sub.clamp.

(29) According to a fourth embodiment of the present disclosure as illustrated in FIG. 12, the semiconductor switch S1 may consist of at least one transistor. The transistor may be a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT) or a Bipolar Junction Transistor (BJT).

(30) In practical implementation, the proposed SPD 700 may further comprise another surge arrestor A2 connected in series with the surge arrestor A1 and the assistor C1, as illustrated in FIG. 13. For the SPD to be able to handle a peak lighting strike current up to 4000 A, the surge arrestor A2 shall have a breakdown value V.sub.A2TH being ignorable as compared with the breakdown value V.sub.A1TH of the surge arrestor A1. In an embodiment, the surge arrestor A2 may be a varistor.

(31) In an embodiment, all components of the arrestor assistor C1 may be mounted on the opposite side of the Printed Circuit Board (PCB) of the SPD using the Surface Mount Technology (SMT), so that the dimension of the SPD can be kept as small as possible.

(32) Thanks to its small dimension and powerful capability, the proposed single-stage SPD 700 is highly suitable to be used with modern telecommunication equipments, such as RRUs, an RBSs or BTSs, which are increasingly subject to limitation on mechanical dimension. For illustration, FIG. 14 depicts a telecommunication equipment 1400 comprising the proposed single-stage SPD 700.

(33) The present disclosure has been described above with reference to the embodiments thereof. However, those embodiments are provided just for illustrative purpose, rather than limiting the present disclosure. The scope of the disclosure is defined by the attached claims as well as equivalents thereof. Those skilled in the art can make various alternations and modifications without departing from the scope of the disclosure, which all fall into the scope of the disclosure.