Flip-flop and driving method thereof

Abstract

A flip-flop includes a conditional boosting stage, a pulse generator and a latch. The conditional boosting stage includes a boosting capacitor, and is configured to pre-charge the boosting capacitor in accordance with a previous output signal and boost a node connected to the boosting capacitor upon a level the previous output signal being different from a level of a current input signal. The pulse generator is configured to generate a pulsed signal in accordance with transitions of a clock signal. The latch configured is to latch the current input signal to a current output signal in accordance with the pulsed signal.

Claims

1. A flip-flop, comprising: a conditional boosting stage comprising a boosting capacitor, and configured to pre-charge the boosting capacitor in accordance with a previous output signal and boost a node connected to the boosting capacitor upon a level of the previous output signal being different from a level of a current input signal; a pulse generator configured to generate a pulsed signal in accordance with transitions of a clock signal; and a latch configured to latch the current input signal to a current output signal in accordance with the pulsed signal.

2. The flip-flop according to claim 1, wherein the conditional boosting stage further comprises: a first transistor comprising a gate terminal, configured to receive the previous output signal, and one end connected to one end of the boosting capacitor; a second transistor comprising a gate terminal, configured to receive an inverted previous output signal, and one end connected to the other end of the boosting capacitor; a third transistor comprising a gate terminal, connected to one end of the boosting capacitor, one end connected to a first power supply voltage, and the other end connected to the other end of the boosting capacitor; and a fourth transistor comprising a gate terminal, connected to the other end of the boosting capacitor, one end connected to the first power supply voltage, and the other end connected to one end of the boosting capacitor.

3. The flip-flop according to claim 2, wherein the conditional boosting stage further comprises: a fifth transistor comprising a gate terminal, configured to receive the current input signal, and one end connected to one end of the boosting capacitor; and a sixth transistor comprising a gate terminal, configured to receive an inverted current input signal, and one end connected to the other end of the boosting capacitor.

4. The flip-flop according to claim 3, wherein the conditional boosting stage further comprises: a seventh transistor comprising a gate terminal, configured to receive a clock signal, one end is connected to the other end of the first transistor, and the other end is connected to a second power supply voltage; and an eighth transistor comprising a gate terminal, configured to receive the pulsed signal, one end connected to the other end of the fifth transistor, and the other end connected to the first power supply voltage.

5. The flip-flop according to claim 4, wherein the conditional boosting stage further comprises: a ninth transistor comprising a gate terminal, configured to receive the current input signal, and one end connected to the other end of the boosting capacitor; a tenth transistor comprising a gate terminal, configured to receive the pulsed signal, and one end connected to the other end of the ninth transistor; an eleventh transistor comprising a gate terminal, configured to receive the clock signal, one end connected to the other end of the tenth transistor and the other end connected to the second power supply voltage; a twelfth transistor in which one end is connected to the other end of the tenth transistor and the other end is connected to the second power supply voltage; and a first inverter in which one end is connected to the other end of the tenth transistor and the other end is connected to a gate terminal of the twelfth transistor.

6. The flip-flop according to claim 5, wherein the conditional boosting stage further comprises: a thirteenth transistor comprising a gate terminal, configured to receive the inverted current input signal, and one end connected to one end of the boosting capacitor; a fourteenth transistor comprising a gate terminal, configured to receive the pulsed signal, and one end connected to the other end of the thirteenth transistor; a fifteenth transistor comprising a gate terminal, configured to receive the clock signal, one end connected to the other end of the fourteenth transistor and the other end connected to the second power supply voltage; a sixteenth transistor in which one end is connected to the other end of the fourteenth transistor and the other end is connected to the second power supply voltage; and a second inverter in which one end is connected to the other end of the fourteenth transistor and the other end is connected to a gate terminal of the sixteenth transistor.

7. The flip-flop according to claim 6, wherein the latch comprises: a seventeenth transistor comprising a gate terminal, connected to the other end of the tenth transistor, and one end connected to the second power supply voltage; an eighteenth transistor comprising a gate terminal, connected to the gate terminal of the sixteenth transistor, one end connected to the other end of the seventeenth transistor, and the other end connected to the first power supply voltage; a nineteenth transistor comprising a gate terminal, connected to the other end of the fourteenth transistor, and one end connected to the second power supply voltage; and a twentieth transistor comprising a gate terminal, connected to the gate terminal of the twelfth transistor, one end connected to the other end of the nineteenth transistor, and the other end connected to the first power supply voltage.

8. The flip-flop according to claim 7, wherein the latch further comprises: a twenty-first transistor comprising a gate terminal, connected to the gate terminal of the sixteenth transistor, and one end connected to the second power supply voltage; a twenty-second transistor comprising a gate terminal, connected to the other end of the nineteenth transistor, one end connected to the other end of the twenty-first transistor, and the other end connected to the other end of the seventeenth transistor; a twenty-third transistor comprising a gate terminal, connected to the other end of the nineteenth transistor, and one end connected to the other end of the twenty-second transistor; and a twenty-fourth transistor comprising a gate terminal, connected to the other end of the tenth transistor, one end connected to the other end of the twenty-third transistor, and the other end connected to the first power supply voltage.

9. The flip-flop according to claim 8, wherein the latch further comprises: a twenty-fifth transistor comprising a gate terminal, connected to the gate terminal of the twelfth transistor, and one end connected to the second power supply voltage; a twenty-sixth transistor comprising a gate terminal, connected to the other end of the seventeenth transistor, one end connected to the other end of the twenty-fifth transistor, and the other end connected to the other end of the nineteenth transistor; a twenty-seventh transistor comprising a gate terminal, connected to the other end of the seventeenth transistor, and one end connected to the other end of the nineteenth transistor; and a twenty-eighth transistor comprising a gate terminal, connected to the other end of the fourteenth transistor, one end connected to the other end of the twenty-seventh transistor, and the other end connected to the first power supply voltage.

10. The flip-flop according to claim 6, wherein the pulse generator comprises: a third inverter in which one end is configured to receive the clock signal; a fourth inverter in which one end is connected to the other end of the third inverter; a fifth inverter in which one end is connected to the other end of the fourth inverter; a twenty-ninth transistor comprising a gate terminal, connected to the other end of the fifth inverter, and one end connected to the second power supply voltage; and a sixth inverter in which one end is connected to the other end of the twenty-ninth transistor and the pulsed signal is output through the other end.

11. The flip-flop according to claim 10, wherein the pulse generator further comprises: a thirtieth transistor comprising a gate terminal, connected to the other end of the fifth inverter, one end connected to the other end of the third inverter, and the other end connected to one end of the sixth inverter; and a thirty-first transistor comprising a gate terminal, connected to the other end of the fourth inverter, one end connected to the other end of the third inverter, and the other end connected to one end of the sixth inverter.

12. A driving method of a flip-flop, the driving method comprising: pre-charging a boosting capacitor in accordance with a previous output signal; boosting a node connected to the boosting capacitor upon a level of the previous output signal being different from a level of a current input signal; generating a pulsed signal in accordance with transitions of a clock signal; and latching the current input signal to a current output signal in accordance with the pulsed signal.

13. The driving method according to claim 12, wherein a node connected to the boosting capacitor is not boosted when the level of the previous output signal is the same as the level of a current input signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a view of an example of a flip-flop.

(2) FIG. 2 is a view of an example of a conditional boosting stage.

(3) FIG. 3 is a view of an example of a latch.

(4) FIG. 4 is a view of an example of a pulse generator.

(5) FIG. 5 is an example of a process of pre-charging a boosting capacitor based on a previous output signal.

(6) FIG. 6 is an example of a process of boosting a node connected to a boosting capacitor based on a previous output signal and a current input signal.

(7) FIG. 7 is an example of a table depicting a boosting condition.

(8) FIG. 8 is an example of a driving method of a flip-flop.

(9) FIG. 9 is an example of a simulated waveform of a flip-flop.

(10) FIG. 10 is an example of a simulation result for various supply voltages.

(11) FIG. 11 is an example of an EDP simulated for various switching conditions.

(12) FIG. 12 is an example of a simulated energy of a CBFF for various switching conditions.

(13) FIG. 13 is an example of a table for comparing performances of a flip-flop according to the present disclosure and a flip-flop of a related art.

(14) FIG. 14 is an example of a view for explaining a Monte Carlo simulation result for a DQ latency.

(15) Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

(16) The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known in the art may be omitted for increased clarity and conciseness.

(17) The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application.

(18) Throughout the specification, when an element, such as a layer, region, or substrate, is described as being on, connected to, or coupled to another element, it may be directly on, connected to, or coupled to the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being directly on, directly connected to, or directly coupled to another element, there can be no other elements intervening therebetween.

(19) As used herein, the term and/or includes any one and any combination of any two or more of the associated listed items.

(20) Although terms such as first, second, and third may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.

(21) Spatially relative terms such as above, upper, below, and lower may be used herein for ease of description to describe one element's relationship to another element as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being above or upper relative to another element will then be below or lower relative to the other element. Thus, the term above encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly.

(22) The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms comprises, includes, and has specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.

(23) Due to manufacturing techniques and/or tolerances, variations of the shapes shown in the drawings may occur. Thus, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shape that occur during manufacturing.

(24) The features of the examples described herein may be combined in various ways as will be apparent after an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the disclosure of this application.

(25) FIG. 1 is an example of a flip-flop according to the present disclosure.

(26) Referring to FIG. 1, a flip-flop 10 of the present disclosure includes a conditional boosting stage 100, a pulse generator 200, and a latch 300.

(27) The conditional boosting stage 100 includes a boosting capacitor and pre-charges the boosting capacitor in accordance with a previous output signal and boosts a node connected to the boosting capacitor when a level of a previous output signal is different from a level of a current input signal. The conditional boosting stage 100 will be described in more detail with reference to FIGS. 2, 5, 6, 7, and 8.

(28) The pulse generator 200 generates a pulsed signal in accordance with transition of a clock signal. The pulse generator 200 will be described in more detail with reference to FIGS. 4 and 8.

(29) The latch 300 latches the current input signal to a current output signal in accordance with the pulsed signal. The latch 300 will be described in more detail with reference to FIGS. 3 and 8.

(30) The flip-flop 10 according to the present disclosure may be referred to as a conditional boosting flip-flop (CBFF).

(31) FIG. 2 is a view for explaining a conditional boosting stage according to the present disclosure.

(32) Referring to FIG. 2, a conditional boosting stage 100 according to the present disclosure includes a boosting capacitor C.sub.BOOT, first to sixteenth transistors MP7, MP6, MN8, MN4, MN6, MN5, MP5, MN7, MN3, MN1, MP3, MP1, MN4, MN2, MP4, and MP2, a first inverter I1, and a second inverter I2.

(33) A previous output signal Q is applied to a gate terminal of the first transistor MP7 and one end of the first transistor MP7 is connected to one end of the boosting capacitor C.sub.BOOT.

(34) An inverted previous output signal QB is applied to a gate terminal of the second transistor MP6 and one end of the second transistor MP6 is connected to the other end of the boosting capacitor C.sub.BOOT.

(35) A gate terminal of the third transistor MN8 is connected to one end of the boosting capacitor C.sub.BOOT, one end is connected to a first power supply voltage VSS, and the other end is connected to the other end of the boosting capacitor C.sub.BOOT.

(36) A gate terminal of the fourth transistor MN9 is connected to the other end of the boosting capacitor C.sub.BOOT, one end is connected to the first power supply voltage VSS, and the other end is connected to one end of the boosting capacitor C.sub.BOOT.

(37) A current input signal D is applied to a gate terminal of the fifth transistor MN6 and one end of the fifth transistor MN6 is connected to one end of the boosting capacitor C.sub.BOOT.

(38) An inverted current input signal DB is applied to a gate terminal of the sixth transistor MN5 and one end of the sixth transistor MN5 is connected to the other end of the boosting capacitor C.sub.BOOT.

(39) A clock signal CLK is applied to a gate terminal of the seventh transistor MP5 and one end of the seventh transistor MP5 is connected to the other end of the first transistor MP7 and the other end is connected to a second power supply voltage VDD.

(40) A pulsed signal PS is applied to a gate terminal of the eighth transistor MN7 and one end of the eighth transistor MN7 is connected to the other end of the fifth transistor MN6 and the other end is connected to the first power supply voltage VSS.

(41) A current input signal D is applied to a gate terminal of the ninth transistor MN3 and one end of the ninth transistor MN3 is connected to the other end of the boosting capacitor C.sub.BOOT.

(42) A pulsed signal PS is applied to a gate terminal of the tenth transistor MN1 and one end of the tenth transistor MN1 is connected to the other end of the ninth transistor MN3.

(43) A clock signal CLK is applied to a gate terminal of the eleventh transistor MP3, one end of the eleventh transistor MP3 is connected to the other end of the tenth transistor MN1, and the other end is connected to the second power supply voltage VDD.

(44) One end of the twelfth transistor MP1 is connected to the other end of the tenth transistor MN1 and the other end is connected to the second power supply voltage VDD.

(45) One end of the first inverter I1 is connected to the other end of the tenth transistor MN1 and the other end is connected to the gate terminal of the twelfth transistor MP1.

(46) An inverted current input signal DB is applied to a gate terminal of the thirteenth transistor MN4 and one end of the thirteenth transistor MN4 is connected to one end of the boosting capacitor C.sub.BOOT.

(47) A pulsed signal PS is applied to a gate terminal of the fourteenth transistor MN2 and one end of the fourteenth transistor MN2 is connected to the other end of the thirteenth transistor MN4.

(48) A clock signal CLK is applied to a gate terminal of the fifteenth transistor MP4, one end of the fifteenth transistor MP4 is connected to the other end of the fourteenth transistor MN2 and the other end is connected to the second power supply voltage VDD.

(49) One end of the sixteenth transistor MP2 is connected to the other end of the fourteenth transistor MN2 and the other end is connected to the second power supply voltage VDD.

(50) One end of the second inverter I2 is connected to the other end of the fourteenth transistor MN2 and the other end is connected to a gate terminal of the sixteenth transistor MP2.

(51) The conditional boosting stage 100 is a conditional boosting differential stage and the transistors MP5, MP6, and MP7 and the transistors MN8 and MN9 may be used to implement an output-dependent presetting. In contrast, the transistors MN5, MN6, and MN7 may be used to implement an input-dependent boosting together with the boosting capacitor C.sub.BOOT. The output-dependent presetting and the input-dependent boosting will be described below with reference to FIGS. 5 and 6.

(52) FIG. 3 is an example of a latch according to the present disclosure.

(53) Referring to FIG. 3, the latch 300 according to the present disclosure may include seventeenth to twenty-eighth transistors MP8, MN10, MP9, MN11, MP19, MP12, MN14, MN12, MP11, MP13, MN15, and MN13.

(54) A gate terminal of the seventeenth transistor MP8 is connected to the other end of the tenth transistor MN1 and one end is connected to the second power supply voltage VDD.

(55) A gate terminal of the eighteenth transistor MN10 is connected to the gate terminal of the sixteenth transistor MP2, one end of the eighteenth transistor MN10 is connected to the other end of the seventeenth transistor MP8, and the other end is connected to the first power supply voltage VSS.

(56) A gate terminal of the nineteenth transistor MP9 is connected to the other end of the fourteenth transistor MN2 and one end is connected to the second power supply voltage VDD.

(57) A gate terminal of the twentieth transistor MN11 is connected to the gate terminal of the twelfth transistor MP1, one end is connected to the other end of the nineteenth transistor MP9, and the other end is connected to the first power supply voltage VSS.

(58) A gate terminal of the twenty-first transistor MP10 is connected to the gate terminal of the sixteenth transistor MP2 and one end is connected to the second power supply voltage VDD.

(59) A gate terminal of the twenty-second transistor MP12 is connected to the other end of the nineteenth transistor MP9, one end is connected to the other end of the twenty-first transistor MP10, and the other end is connected to the other end of the seventeenth transistor MP8.

(60) A gate terminal of the twenty-third transistor MN14 is connected to the other end of the nineteenth transistor MP9 and one end is connected to the other end of the twenty-second transistor MP12.

(61) A gate terminal of the twenty-fourth transistor MN12 is connected to the other end of the tenth transistor MN1, one end of the twenty-fourth transistor MN12 is connected to the other end of the twenty-third transistor MN14, and the other end is connected to the first power supply voltage VSS.

(62) A gate terminal of the twenty-fifth transistor MP11 is connected to the gate terminal of the twelfth transistor MP1 and one end is connected to the second power supply voltage VDD.

(63) A gate terminal of the twenty-sixth transistor MP13 is connected to the other end of the seventeenth transistor MP8, one end is connected to the other end of the twenty-fifth transistor MP11, and the other end is connected to the other end of the nineteenth transistor MP9.

(64) A gate terminal of the twenty-seventh transistor MN15 is connected to the other end of the seventeenth transistor MP8 and one end is connected to the other end of the nineteenth transistor MP9.

(65) A gate terminal of the twenty-eighth transistor MN13 is connected to the other end of the fourteenth transistor MN2, one end of the twenty-eighth transistor MN13 is connected to the other end of the twenty-seventh transistor MN15, and the other end is connected to the first power supply voltage VSS.

(66) The latch 300 may be a symmetric latch.

(67) FIG. 4 is an example of a pulse generator according to the present disclosure.

(68) Referring to FIG. 4, a pulse generator 200 according to the present disclosure may include third to sixth inverters I3, I4, I5, and I6 and twenty-ninth to thirty-first transistors MP14, MP16, and MP15.

(69) A clock signal CLK may be applied to one end of the third inverter I3.

(70) One end of the fourth inverter I4 is connected to the other end of the third inverter I3.

(71) One end of the fifth inverter I5 is connected to the other end of the fourth inverter I4.

(72) A gate terminal of the twenty-ninth transistor MP14 is connected to the other end of the fifth inverter 15 and one end is connected to the second power supply voltage VDD.

(73) One end of the sixth inverter I6 is connected to the other end of the twenty-ninth transistor MP14 and a pulsed signal PS is output through the other end of the sixth inverter I6.

(74) A gate terminal of the thirtieth transistor MN16 is connected to the other end of the fifth inverter I5, one end of the thirtieth transistor MN16 is connected to the other end of the third inverter I3, and the other end is connected to one end of the sixth inverter I6.

(75) A gate terminal of the thirty-first transistor MP15 is connected to the other end of the fourth inverter I4, one end of the thirty-first transistor MN15 is connected to the other end of the third inverter I3, and the other end is connected to one end of the sixth inverter I6.

(76) The pulse generator 200 is an explicit brief pulse generator and drives some transistors of the conditional boosting stage 100 with a pulsed signal PS.

(77) Differently from the pulse generator of the related art, the pulse generator 200 does not include a pMOS keeper and there is no signal contention during a pull-down of the inverted pulsed signal PSB, so that a higher speed and a lower power driving may be achieved.

(78) A role of the pMOS keeper, which is used to maintain a high level logic value of the inverted pulsed signal PSB, is performed by the thirty-first transistor MP15 which is added in parallel to the thirtieth transistor MN16. The thirty-first transistor MP15 helps fast pull-down of the inverted pulsed signal PSB.

(79) At a rising edge of the clock signal CLK, the inverted pulsed signal PSB is quickly discharged by the transistors MN16 and MP15 and the third inverter I3 to make the pulsed signal PS a high level. After the delay of the inverters I4 and I5, the inverted pulsed signal PSB is charged by the twenty-ninth transistor MP14 and thus the pulsed signal PS returns to a low level. A width of the pulsed signal PS is determined by a delay value of the inverters I4 and I5.

(80) When the clock signal CLK is a low level, the inverted pulsed signal PSB is maintained to be a high level by the thirty-first transistor MP15. In this case, the twenty-ninth transistor MP14 is turned off.

(81) According to a measurement evaluation, it was confirmed that energy is reduced up to 9% for the same slew rate and the same pulse width.

(82) FIG. 5 is an example of a process of pre-charging a boosting capacitor based on a previous output signal, FIG. 6 is an example of a process of boosting a node connected to a boosting capacitor based on a previous output signal and a current input signal, and FIG. 7 is an example of a table depicting a boosting condition.

(83) When FIGS. 5 to 7 are described, for the ease of description, it is assumed that the clock signal CLK is a low level and the pulsed signal PS is a high level. In this case, the seventh transistor MP5 and the eighth transistor MN7 are electrically conducted so that the seventh transistor MP5 and the eighth transistor MN7 are omitted in FIGS. 5 and 6.

(84) In order to implement conditional boosting by the differential flip-flop, four different scenarios for input data capture need to be considered. Four scenarios may be determined by logic states for input and output. Four scenarios will be described as follows:

(85) A first scenario is that with respect to a low level of a previous output signal Q, the boosting of a high level of a current input signal D needs to be triggered for quick capture of incoming data.

(86) A second scenario is that with respect to a low level of a previous output signal Q, it is not required to capture an input, so that the boosting of a low level of a current input signal D should not be triggered.

(87) A third scenario is that with respect to a high level of a previous output signal Q, it is required to quickly capture incoming data, boosting of a low level of a current input signal D needs to be triggered.

(88) A fourth scenario is that with respect to a high level of a previous output signal Q, boosting of a high level of a current input signal D should not be triggered.

(89) Such scenarios use a single boosting capacitor C.sub.BOOT by a combination of two operation principles to be embedded in a circuit topology.

(90) A first operation principle is that a voltage presetting at both ends of the boosting capacitor C.sub.BOOT needs to be determined by data (previous output data) stored at an output side (output-dependent presetting).

(91) A second operation principle is that the boosting operation needs to be conditional to input data (current input signal) given to the flip-flop 10 (input-dependent boosting).

(92) FIGS. 5 and 6 illustrate a conceptual circuit diagram for explaining the above-mentioned principles.

(93) For the first operation principle, preset voltages of capacitor terminals BNL and BNR need to be determined by a previous output signal Q and an inverted previous output signal QB. If the previous output signal Q is a low level and the inverted previous output signal QB is a high level, a node BNL is preset to a low level and a node BNR is preset to a high level (see a left side of FIG. 5). If the previous output signal Q is a high level and the inverted previous output signal QB is a low level, the node BNL is preset to a high level and the node BNR is preset to a low level (see a right side of FIG. 5).

(94) For the second operation principle, the current input signal D needs to be coupled to the node BNR through an nMOS transistor MN6. Further, the inverted current input signal DB needs to be coupled to the node BNL through the nMOS transistor MN5 (see FIG. 6).

(95) For example, when the low level data is stored in the flip-flop 10, the boosting capacitor C.sub.BOOT is preset as illustrated at the left side of FIG. 5 and the high level input pulls down the voltage of the node BNR to a ground level and boosts the voltage of the node BNL to a ()VDD level (see an upper-left side of FIG. 6).

(96) In contrast, the low level input connects the voltage of the node BNL to the ground. However, since the voltage of the node BNL is already preset to VSS, voltage change does not occur in the node BNR and the boosting operation does not occur (see a lower left side of FIG. 6).

(97) As another example, when high level data is stored in the flip-flop 10, the boosting capacitor C.sub.BOOT is preset as illustrated in the right side of FIG. 5, the low level input pulls down the voltage of the node BNL to a ground level so that the voltage of the node BNR is boosted to ()VDD by the capacitive coupling (see a lower right side of FIG. 6).

(98) In contrast, the high level input connects the voltage of the node BNR to the ground. However, since the voltage of the node BNR is already preset to VSS, voltage change does not occur at the node BNL so that the boosting operation does not occur (see an upper right side of FIG. 6).

(99) For easier understanding, the operations are summarized in Table 1 of FIG. 7.

(100) Redundant boosting is eliminated by the above-mentioned operations and specifically the power consumption may be drastically lowered by lower frequency switching.

(101) FIG. 8 is an example of a driving method of a flip-flop according to the present disclosure.

(102) A driving method of a flip-flop 10 according to the present disclosure includes a step of pre-charging a boosting capacitor C.sub.BOOT in accordance with a previous output signal Q, a step of boosting a node connected to the boosting capacitor C.sub.BOOT when a level of the previous output signal Q and a level of a current input signal D are different, a step of generating a pulsed signal PS corresponding to transition of a clock signal CLK, and a step of latching the current input signal D to the current output signal Q in accordance with the pulsed signal PS.

(103) Referring to FIG. 8, even though the previous output signal Q and the current output signal Q are denoted by the same referential character, the previous output signal and the current output signal may be distinguished as time periods with respect to the pulsed signal PS.

(104) According to the embodiment, when a level of the previous output signal Q and a level of the current input signal D are the same, a node connected to the boosting capacitor C.sub.BOOT may not be boosted.

(105) Hereinafter, a driving method of an exemplary flip-flop 10 will be described in detail with reference to an example of a timing diagram depicted in FIG. 8.

(106) Prior to describing the driving method of the exemplary flip-flop 10, it is assumed that when the clock signal CLK is a low level, an initial output signal Q is set to be a low level.

(107) Next, the node BNR is preset to a high level by turning on the transistors MP5 and MP7 and the node BNL is preset to a low level by turning on the transistor MN8 (output-dependent presetting). Now, when the pulsed signal PS becomes a high level after the rising edge of the clock signal CLK, the nodes BNL and BNR are connected to the nodes SB and RB or the first power supply voltage VSS in accordance with the input data.

(108) As illustrated in a first cycle of FIG. 3, the input signal D is a high level, which is different from that of the output signal Q. Therefore, the voltage of the node BNR is pulled down to the second power supply voltage VSS through the transistors MN6 and MN7. Further, the voltage of the node BNL connected to the node SB through the transistors MN1 and MN3 becomes lower than the second power supply voltage VSS due to the capacitive coupling through the boosting capacitor C.sub.BOOT (input-dependent boosting).

(109) Such an operation results in an improved driving force of the transistors MN1 and MN3 and fast pull-down of the node (SB) voltage. A slight forward body bias formed by a negative voltage at the node BNL reduces a threshold voltage V.sub.TH and improves a driving force.

(110) Moreover, a negatively boosted voltage which is transmitted to the node SB causes the pMOS transistor in the first inverter I1 and the transistor MP8 of the latch 300 to have an improved driving force, which causes fast pull-up of the output signal Q.

(111) Even though the boosted node SB is instantly floated after the pull-down of the pulsed signal PS, any possible rise of the node SB due to leakage does not cause output flipping. This is because the transistors MP13 and MN14 of the latch 300 are completely off. Due to this condition, this circuit is not appropriate for operating at a very low frequency.

(112) Since at a next falling edge of the clock signal CLK, the inverted output signal QB is a low level, the node BNL is preset to a high level through the transistors MP5 and MP6, which presets the voltage of the node BNR to a low level through the transistor MN9 (output-dependent presetting). The node SB is also precharged to a high level due to the transistor MP3.

(113) Now, an operation of a second cycle of FIG. 3 will be described. The input signal D is maintained to a high level, which is the same as the output signal Q.

(114) When the pulsed signal PS becomes a high level after the rising edge of the clock signal CLK, the node BNL is connected to the node SB and the node BNR is connected to the first power supply voltage VSS. However, the nodes BNL and BNR are already a high level and a low level, respectively so that the boosting operation does not occur (input-dependent boosting), which does not cause the output change. In order to suppress a possible change due to the leakage, the nodes SB and RB are maintained to a high level by the transistors MP1 and MP2.

(115) During a third cycle of FIG. 3, that is, while the output signal Q is a high level and the input signal D is a low level, the negative boosting is generated at the node BNR for fast pull-down of the output signal Q. In the meantime, during a fourth cycle when both the output signal Q and the input signal D are a low level, the boosting operation does not occur.

(116) FIG. 9 is an example of a simulated waveform of a flip-flop according to the present disclosure.

(117) Referring to FIG. 9, it is confirmed that high level input data is quickly captured by the flip-flop 10 by boosting the node BNL below the ground level.

(118) As seen from the above-described operation process, a latency of the proposed flip-flop 10 is considerably reduced by the voltage boosting which improves the driving force of the transistors. The enlarged gate-source voltage of the transistors located in timing-critical paths contributes to this feature. A slight forward source-body voltage is formed in some of transistors by boosting the source voltage below the ground level, which results in reducing the threshold voltage and further improving the driving force.

(119) The increased gate-source voltage and the reduced threshold voltage mean improved effective voltages so that there is little latency change even in process variation, and the degree of performance change is reduced. Moreover, based on the suggested output-dependent presetting and input-dependent boosting technique, only when the stored data and input data are different, the boosting is generated, which results in a conditional boosting operation. Therefore, a redundant boosting operation which consumes power is eliminated, which results in a substantially improved energy efficiency in low frequency switching operations.

(120) A soft-edge property provided by a pulsed operation improves a resistance against a clock skew and a clock jitter and enables time-borrowing. Since the pulse may be shared by a plurality of flip-flops, the energy consumed by the pulse generator 200 may be reduced.

(121) Even though the proposed flip-flop 10 is based on voltage boosting in which some internal node voltages exceed a supplied voltage, an overstress problem is not incurred. This is because an application target product targets a voltage action near the threshold, and the boosted maximum voltage still does not exceed 1 V.

(122) FIG. 10 is an example of a simulation result for various supplying voltages, FIG. 11 is an example of an EDP simulated for various switching conditions, and FIG. 12 is an example of a simulated energy of a CBFF for various switching conditions.

(123) A sense amplifier-based flip-flop (SAFF), a differential skew tolerant flip-flop (STFF-D), a static contention-free single-phase-clocked flip-flop (SCFF), an adaptive-coupling flip-flop (ACFF), and fully static topologically-compressed flip-flop (TCFF) which were flop flops of the related art were designed by 65-nm CMOS process and evaluated as well as the CBFF which was a proposed flip-flop 10.

(124) A CBFF with shared pulse generator (CBFF-SP) in which four proposed flip-flops 10 shared the pulse generator 200 was also designed and evaluated.

(125) A size of each of the flip-flops was individually optimized and the EDP is minimized at each supplied voltage. A 15 fF of capacitive load was attached to each flip-flop at each output. An MOM capacitor was used to implement a boosting capacitor. A pulse width of the proposed flip-flop was chosen to give a sufficient margin to guarantee data capture even under worst conditions.

(126) Referring to FIG. 10, a simulated data-to-output latency (DQ) and an energy-delay product (EDP) of the flip-flops at a supplied voltage of 0.5 to 0.7 V are illustrated.

(127) As illustrated in FIG. 10, the CBFF is up to 72% and 63% faster than the SAFF and STFF-D at 25% switching activity (see FIG. 10A) and has up to 53% and 47% lower EDP than that of the SAFF and STFF-D (see FIG. 10B). Further since the pulse generator 200 is shared by the plurality of flip-flops, the CBFF-SP shows up to 67% and 63% lower EDD than that of the SAFF and STFF-D. S.sup.2CFF, ACFF, and TCFF have considerably large DQ latency, which causes a poor performance in terms of EDP.

(128) Referring to FIG. 11, a simulated EDP of the flip-flops at a supply voltage of 0.5 V in accordance with an input switching activity is illustrated. Improved EDP of the CBFF and CBFF0SP with respect to the SAFF is up to 70% and 85%, respectively. This is caused by the conditional operation.

(129) In FIG. 12, the power consumption of the proposed flip-flop 10 is divided for every component and with reference to this, it is understood that as the switching activity is reduced by the conditional boosting, the switching power is reduced. At the zero switching activity, most of power is consumed by the clock circuit included in the pulse generator 200.

(130) FIG. 13 is a table for comparing performances of a flip-flop according to the present disclosure and a flip-flop of a related art and FIG. 14 is a view for explaining a Monte Carlo simulation result for a DQ latency.

(131) In FIG. 14, DQ latency changes of the flip-flops by 1000-point Monte Carlo simulation in a random process change are compared. Referring to this, it is understood that the DQ latencies of the CBFF and CBFF-SP are not sensitive to the process change in a near-threshold voltage region.

(132) Specifically, the CBFF has 75% and 85% lower DQ latency standard variations than that of the SAFF and STFF-D. Further, the CBFF-SP has 67% and 87% reduced EDP standard variations as compared with the SAFF and STFF-D.

(133) The performances of the flip-flops are summarized in Table 2 of FIG. 13. The proposed flip-flops use more devices and occupy a larger layout region. The S.sup.2CFF, ACFF, and TCFF are proposed for low power and thus consume lower energy, but have a larger DQ latency which causes poor EDP performance. The proposed flip-flop has a relatively high hold time due to the pulsed operation, which may require a buffer stage at an output side to avoid hold time violation. According to the evaluation, when a buffer stage for solving the above-mentioned issues is further included, approximately 7% EDP overhead may be caused at 25% switching activity.

(134) While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.