CLOCK DRIVING CIRCUIT RESISTANT TO SINGLE-EVENT TRANSIENT

Abstract

Disclosed in present invention is a clock driving circuit resistant to single-event transient. The clock driving circuit resistant to single-event transient consists of two kinds of inverters: double-input double-output (DIDO) inverter and double-input single-output (DISO) inverter, the specific number of the two kinds of inverters used, and the connection way thereof are determined by the complexity of a designed circuit and a clock design method used by the designed circuit. The DIDO inverter and DISO inverter both comprise two PMOS transistors and two NMOS transistors. In a clock distribution network based on double-input double-output and double-input single-output clock inverters, the probability that single-event transient pulses generated on the DIDO inverter are propagated to clock leaf nodes is zero. Therefore, the invention significantly improves the ability of the clock distribution network to resist single-event transient, effectively reducing the probability that the clock distribution network generates single-event transient pulses on the respective clock leaf nodes after being bombarded by radiation particles. Thus, the reinforced clock circuit resistant to single-event transient of the present invention is superior to a conventional unreinforced clock circuit in single-event transient resistance.

Claims

1. A clock driving circuit resistant to single-event transient, comprising: two types of inverters: a DIDO inverter and a DISO inverter, a specific number of the two types of inverters used, and a connection way thereof are determined by a complexity of a designed circuit and a clock design scheme used by the designed circuit; wherein the DIDO inverter includes a first input port, a second input port, a first output port and a second output port, wherein the DIDO inverter connects to a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein a gate of the first PMOS transistor is connected to the first input port of the DIDO inverter, a source of the first PMOS transistor is connected to a power supply, and a drain of the first PMOS transistor is connected to the first output port of the DIDO inverter, wherein a gate of the second PMOS transistor is connected to the second input port of the DIDO inverter, a source of the second PMOS transistor is connected to the power supply, and a drain of the second PMOS transistor is connected to the second output port of the DIDO inverter, wherein a gate of the first NMOS transistor is connected to the second input port of the DIDO inverter, a source of the first NMOS transistor is connected to the ground, and a drain of the first NMOS transistor is connected to the second output port of the DIDO inverter, wherein a gate of the second NMOS transistor is connected to the first input port of the DIDO inverter, a source of the second NMOS transistor is connected to the ground, and a drain of the second NMOS transistor is connected to the second output port of the DIDO inverter, wherein the DISO inverter includes a first input port, a second input and an output port, wherein the DISO inverter connects to a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor and a fourth NMOS transistor, wherein a gate of the third PMOS transistor is connected to the first input port of the DISO inverter, a source of the third PMOS transistor is connected to the power supply, and a drain of the third PMOS transistor is connected to a source of the fourth PMOS transistor, wherein a gate of the fourth PMOS transistor is connected to the second input port of the DISO inverter, the source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, and a drain of the fourth PMOS transistor is connected to the output port of the DISO inverter, wherein a gate of the third NMOS transistor is connected to the second input port of the DISO inverter, a source of the third NMOS transistor is connected to a drain of the fourth NMOS transistor, and a drain of the third NMOS transistor is connected to the output port of the DISO inverter, wherein a gate of the fourth NMOS transistor is connected to the first input port of the DISO inverter, a source of the fourth NMOS transistor is connected to the ground, and the drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor.

2. The clock driving circuit resistant to single-event transient according to claim 1, wherein a number of the DIDO inverters and the DISO inverters is n, wherein n is an integer, wherein n is larger than or equal to 3, wherein the connection way is a balanced tree structure, wherein a Level 1 inverter to Level (n1) inverters are the DIDO inverters, and last level inverters, i.e., Level n inverters, are the DISO inverters, wherein a first input port and a second input port of the Level 1 inverter are connected to a same clock signal, an first output port of the Level 1 inverter is connected to first input ports of Level 2 inverters, and an second output port of the Level 1 inverter is connected to second input ports of the Level 2 inverters, wherein first output ports of the two Level 2 inverters are respectively connected to first input ports of corresponding Level 3 inverters thereafter, and second output ports of the two Level 2 inverters are connected to second input ports of the Level 3 inverters respectively, wherein an first output port of a Level k inverter is connected to a first input port of a subsequent level inverter, and a second output port of a Level k inverter is connected to an second input port of a Level (k+1) inverter, wherein k and j are integers, 3kn2, and 1j4, wherein a first input and a second input of a Level n inverter thereof are respectively connected to a first output and a second output of the Level n1 inverter, and an output port of the Level n inverter is connected to a clock input port of a timing unit such as a trigger connected.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG. 1 is a logical structure diagram of a DIDO inverter according to the present invention.

[0021] FIG. 2 is a logical structure diagram of a DISO inverter according to the present invention.

[0022] FIG. 3 is a graphical diagram of the DIDO inverter according to the present invention.

[0023] FIG. 4 is a graphical diagram of the DISO inverter according to the present invention.

[0024] FIG. 5 is a schematic diagram of a reinforced clock circuit resistant to single-event transient, implemented using DIDO and DISO inverters.

[0025] FIG. 6 is a schematic diagram showing an eight-level inverter chain composed of unreinforced clock inverters CLKNVHSV4 in a standard cell library under a general 65 nm process and propagation of a SET transient pulse therein according to a specific embodiment.

[0026] FIG. 7 is a schematic diagram showing an eight-level inverter chain composed of reinforced DIDO inverters CLKNVHSV4_DIDO and a DISO inverter CLKNVHSV4 _DISO under a 65 nm process, and propagation of a SET transient pulse therein according to a specific embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

[0027] FIG. 1 is a logical structure diagram of a DIDO inverter according to the present invention. Compared with a common inverter composed of a PMOS transistor and an NMOS transistor, the DIDO inverter of the present invention includes two PMOS transistors denoted by a first PMOS transistor and a second PMOS transistor, and two NMOS transistors denoted by a first NMOS transistor and a second NMOS transistor. A gate Pg1_D of the first PMOS transistor is connected to an input port I1_D of the DIDO inverter, a source Ps1_D is connected to a power supply VDD, and a drain Pd1_D is connected to an output port ZN1_D of the DIDO inverter; a gate Pg2_D of the second PMOS transistor is connected to an input port I2_D of the DIDO inverter, a source Ps2_D is connected to the power supply VDD, and a drain Pd2_D is connected to an output port ZN2_D of the DIDO inverter; a gate Ng1_D of the first NMOS transistor is connected to an input port I2_D of the DIDO inverter, a source Ns1_D is connected to the ground VSS, and a drain Nd1_D is connected to the output port ZN1_D of the DIDO inverter; and a gate Ng2_D of the second NMOS transistor is connected to the input port I1_D of the DIDO inverter, a source Ns2_D is connected to the ground VSS, and a drain Nd2_D is connected to the output port ZN2_D of the DIDO inverter.

[0028] FIG. 2 is a logical structure diagram of a DIDO inverter according to the present invention. The DISO inverter of the present invention includes two PMOS transistors denoted by a third PMOS transistor and a fourth PMOS transistor, and two NMOS transistors denoted by a third NMOS transistor and a fourth NMOS transistor. A gate Pg3_S of the third PMOS transistor is connected to an input port I1_S of the DISO inverter, a source Ps3_S is connected to the power supply VDD, and a drain Pd3_S is connected to a source Ps4_S of the fourth PMOS transistor; a gate Pg4_S of the fourth PMOS transistor is connected to an input port I2_S of the DISO inverter, the source Ps4_S is connected to the drain Pd3_S of the third PMOS transistor, and a drain Pd4_S is connected to an output port ZN_S of the DISO inverter; a gate Ng3_S of the third NMOS transistor is connected to an input port I2_S of the DISO inverter, a source Ns3_S is connected to a drain Nd4_S of the fourth NMOS transistor, and a drain Nd3_S is connected to the output port ZN_S of the DISO inverter; and a gate Ng4_S of the fourth NMOS transistor is connected to the input port I1_S of the DISO inverter, a source Ns4_S is connected to the ground VSS, and the drain Nd4_S is connected to the source Ns3_S of the third NMOS transistor.

[0029] FIG. 3 shows a graphical diagram of the DIDO inverter according to the present invention. FIG. 4 shows a graphical diagram of the DISO inverter according to the present invention. The graphical diagrams of the DIDO and DISO inverters are connected in the reinforced clock circuit resistant to single-particle transient in FIG. 5.

[0030] FIG. 5 is a schematic diagram of a reinforced clock circuit resistant to single-event transient, implemented using DIDO and DISO units. In this embodiment, the clock driving circuit of the present invention is a clock network of a balanced tree structure composed of n levels of inverters. The Level 1 inverter to the Level (n1) inverter are DIDO inverters, and the last level inverter, i.e., the Level n inverter, is a DISO inverter, wherein n is an integer, and the value of n is detennined by the complexity of a designed circuit and a clock design scheme (including a topological structure of a clock distribution network) used by the designed circuit, n3. The two input ports of the Level 1 inverter are connected to the same clock signal clk, the output port ZN1_D_1 thereof is connected to the input ports I1_D_21 and I1_D_22 of the Level 2 inverter (in the Figure, two Level 2 inverters are connected as an example), and the output port ZN2_D_1 of the Level 1 inverter is connected to the input ports I2_D_21 and I2_D_22 of the Level 2 inverter; the output ports ZN1_D_21 and ZN1_D_22 of the two Level 2 inverters are respectively connected to the input ports I1_D_31, I1_D_32 and I1_D_33, I1_D_34 of the corresponding Level 3 inverters thereafter, and the output ports ZN2_D_21 and ZN2_D_22 thereof are connected to the input ports I2_D_31, I2_D_32 and I2_D_33, I2_D_34 of the third-stage inverters respectively. The output port ZN1_D_kj of the Level k inverter is connected to the input port I1_D_(k+1)j of the subsequent level inverter (i.e., the Level (k+1) inverter), and the output port ZN2_D_kj of the Level k inverter is connected to the input port I2_D_(k+1)j of the Level (k+1) inverter, wherein k and j are integers, 3kn2, and 1j4. The last level inverter (i.e., the clock inverter directly connected to a timing unit such as a trigger, the Level n inverter) in the clock circuit is a DISO clock inverter: the two inputs ports I1_S_j and I2_S_j thereof are respectively connected to the output ports ZN1_D (n1)j and ZN2_D (n1)j of the penultimate level inverter (i.e., the Level (n1) inverter), and the output port ZN_S_j thereof is connected to a clock input port of a timing unit such as a trigger connected.

[0031] FIG. 6 is a schematic diagram showing an eight-level inverter chain composed of unreinforced clock inverters CLKNVHSV4 in a standard cell library under a general 65 nm process and propagation of a SET transient pulse therein according to a specific embodiment. FIG. 6(a) shows an inverter chain composed of unreinforced inverters CLKNVHSV4 in a standard cell library under a general 65 nm process. The inverter chain is composed of eight clock inverters CLKNVHSV4 connected end to end, and the input and output ends of the inverter chain are I and Z, respectively. FIG. 6(b) is a schematic diagram showing propagation of a SET transient pulse in the inverter chain. The excitation of the SET pulse is applied to the input port I of the inverter chain. When the width of the applied SET pulse is small, the amplitude and width of the pulse are gradually reduced during propagation, and when the output end Z of the inverter chain is arrived at, the SET pulse cannot be captured. When the width of the applied SET pulse reaches about 35 ps, a rail-to-rail SET pulse signal can be captured at the output port Z.

[0032] FIG. 7 is a schematic diagram showing an eight-level inverter chain composed of reinforced DIDO inverters CLKNVHSV4_DIDO and a DISO inverter CLKNVHSV4_DISO under a 65 nm process, and propagation of a SET transient pulse therein according to a specific embodiment. FIG. 7(a) shows an inverter chain composed of two types of reinforced inverters connected end to end according to the present invention in a 65 nm process. The inverter chain includes seven DIDO inverters CLKNVHSV4_DIDO and a DISO inverter CLKNVHSV4_DISO. The input ports of the inverter chain are I and I0, and the output port is Z. FIG. 7(b) is a schematic diagram showing propagation of a SET transient pulse in the inverter chain. The input port I0 of the inverter chain is kept always 0, a SET pulse is added to the input port I, and propagation of the applied SET pulse in the inverter chain is learned by observing output waveforms of the output ends ZN* and ZN*0 (wherein *=1, 2 . . . 7) of each inverter and the output end Z of the inverter chain. When the width of the applied SET pulse reaches 500 ps, no significant transient pulse is observed at the output end of the Level 3 inverter, in fact, at the output end of the Level 1 inverter, the amplitude of the pulse is already less than of the amplitude of the applied SET pulse.

[0033] In order to illustrate the single-event transient resisting effect of the clock driving circuit resistant to single-event transient according to the present invention, a scalar memory controller decoding circuit is designed (including layout planning, clock tree synthesis, placement and routing, etc.) using the clock driving circuit of the present invention, an Encounter tool and a script; a detailed standard parasitic format (DSPF) file of the whole design is extracted using a parasitic parameter extraction tool StarRC; and a DSPF net list including resistance, capacitance and other detailed parasitic information is simulated using a Hspice tool.

[0034] Considering that the design of the scalar memory controller decoding circuit is mainly based on a trigger, simulation of radiation-induced clock race is mainly performed on the design in combination with the research results of N. Seifert et al. The injection position of the SET pulse traverses the output port of each DIDO inverter on the clock network during simulation; the injection time of the SET pulse is random (in a simulation time period, a random injection time is automatically generated using a shell script); the width of the SET pulse is random, and the width of the SET pulse is small than or equal to a maximum pulse width value (the maximum pulse width value is determined according to the test results of ground irradiation tests, and the pulse width is also generated automatically using a shell script). In the Spice net list, two identical decoding circuits are called; at the same time, the clock input port CK of the same timing unit (D trigger) in the two decoding circuits is connected to two input ports of an exclusive OR gate (i.e., the number of exclusive OR gates called during the simulation is equal to the total number of timing units in the decoding circuits). During the simulation, the SET pulse injection is traversed to the output ports of the DIDO inverters on the clock path in one decoding circuit, and propagation of the SET pulse on the clock path in the reinforced clock circuit resistant to single-event transient according to the present invention is researched by collecting statics on the number of high levels in exclusive OR gates (a group of exclusive OR gates connected to the CK end of the D trigger). The statistical results are shown in Table 1.

[0035] In order to verify the reinforcement effect of the reinforced clock circuit resistant to single-event transient according to the present invention more intuitively, clock tree synthesis is performed on the same design by using unreinforced clock inverters (CLKNVHSV1) having the same driving ability in the standard cell library to obtain an unreinforced clock distribution network. At the same time, traversal simulation is performed on the output ports of the inverters, corresponding to the respective DIDO inverters in the reinforced clock circuit resistant to single-event transient according to the present invention, on the unreinforced clock distribution network by using the simulation method described above. The simulation results are collected (the statistical results are shown in Table 1). Since a DISO inverter is adopted on the leaf node of the clock distribution network resistant to single-event transient according to the present invention, the output port ZN of such inverter bombarded also generates a SET pulse, and the pulse may be propagated to the trigger directly connected to the inverter. However, since the situation that the leaf node is bombarded and generates a SET pulse is similar to the situation of the leaf node on the unreinforced clock distribution network, it will not be simulated.

[0036] In order to make the verification result more sufficient, four traversal simulations are respectively performed on the output ports ZN1 of 31 DIDO inverters (CLKNVHSV1_DIDO) in the reinforced clock circuit resistant to single-event transient according to the present invention and the output ports ZN of 31 corresponding unreinforced common inverters (CLKNVHSV1) in the unreinforced clock distribution network. The design of a scalar memory controller decoding circuit includes 88 timing units (triggers), that is, the maximum number of SETs detected at the CK ports of the triggers is 88. Through the comparison of the statistical results in Table 1, it can be intuitively seen that the reinforced clock circuit resistant to single-event transient according to the present invention is obviously superior to a conventional unreinforced clock circuit in SET resistance, is suitable for a reinforced clock distribution network resistant to single-event transient, and therefore is applied in the fields of aviation, aerospace, etc.

TABLE-US-00001 TABLE 1 Clock driving circuit Number of SETs resistant to single- detected at CK Unreinforced event transient according ends of triggers clock circuit to the present invention 1-3 4 0 4-6 37 0 7-9 21 0 10-19 23 0 20-29 12 0 50-80 4 0 88 3 0