LOW-COMPLEXITY AMPLITUDE ERROR CORRECTION IN A WIRELESS COMMUNICATION CIRCUIT

Abstract

Low-complexity amplitude and phase (AM-PM) error correction in a transceiver circuit is provided. In embodiments disclosed herein, a transceiver circuit is configured to equalize an input vector to thereby correct an AM-AM error across a modulation bandwidth of the wireless communication circuit. Unlike conventional methods where complicated memory digital predistortion (mDPD) coefficients must be defined and calibrated for each modulation frequency within the modulation bandwidth, the transceiver circuit is configured herein to eliminate modulation frequency dependency of the AM-AM error. As a result, it is possible to correct the AM-AM error across the modulation bandwidth with reduced complexity to thereby improve efficiency and linearity of the wireless communication circuit.

Claims

1. A transceiver circuit comprising: a frequency equalization circuit configured to apply a frequency equalization filter to an input vector to linearize a gain error of the input vector in each of a plurality of modulation frequencies to thereby generate a frequency-equalized input vector; and a gain error correction circuit configured to: apply a complex filter to the frequency-equalized input vector to superimpose a respective linearized gain error in a selected modulation frequency among the plurality of modulation frequencies onto a respective linearized gain error in a reference modulation frequency among the plurality of modulation frequencies; determine a linearized gain error correction term in the selected modulation frequency based on the respective linearized gain error in the reference modulation frequency; and apply the determined linearized gain error correction term to the frequency-equalized input vector to thereby generate an equalized input vector in the selected modulation frequency.

2. The transceiver circuit of claim 1, wherein the gain error correction circuit comprises: an equalizer circuit configured to apply the complex filter to the frequency-equalized input vector to superimpose the respective linearized gain error in the selected modulation frequency onto the respective linearized gain error in the reference modulation frequency; a vector-to-real (V2R) converter configured to extract a real parameter from the superimposed frequency-equalized input vector, wherein the real parameter indicates an amount of shift that is required to superimpose the respective linearized gain error in the selected modulation frequency onto the respective linearized gain error in the reference modulation frequency; a scaler configured to scale the real parameter based on a scaling factor to thereby generate a scaled real parameter; a lookup table (LUT) circuit configured to determine a decibel gain error correction term in the reference modulation frequency based on the scaled real parameter; a converter circuit configured to convert the decibel gain error correction term into the linearized gain error correction term; and a multiplier circuit configured to multiply the linearized gain error correction term with the frequency-equalized input vector to thereby generate the equalized input vector.

3. The transceiver circuit of claim 1, further comprising a digital baseband circuit configured to generate the input vector in the selected modulation frequency.

4. The transceiver circuit of claim 1, further comprising a modulation circuit configured to convert the equalized input vector into a radio frequency (RF) signal and modulate the RF signal onto one of an intermediate frequency and a carrier frequency.

5. The transceiver circuit of claim 1, further comprising a memory digital predistortion (mDPD) circuit configured to correct a residual gain error in the equalized input vector.

6. The transceiver circuit of claim 1, further comprising a delay circuit configured to delay the frequency-equalized input vector to compensate for a group delay associated with the gain error correction circuit.

7. The transceiver circuit of claim 1, further comprising: a digital baseband circuit configured to generate the input vector in the selected modulation frequency; a modulation circuit configured to convert the equalized input vector into a radio frequency (RF) signal and modulate the RF signal onto one of an intermediate frequency and a carrier frequency; a memory digital predistortion (mDPD) circuit configured to correct a residual gain error in the equalized input vector; and a delay circuit configured to delay the frequency-equalized input vector to compensate for a group delay associated with the gain error correction circuit.

8. The transceiver circuit of claim 1, wherein the reference modulation frequency is a center modulation frequency among the plurality of modulation frequencies.

9. The transceiver circuit of claim 1, further comprising: an envelope detection circuit configured to detect a time-variant amplitude envelope of the input vector; and a target voltage circuit configured to generate a time-variant target voltage envelope that keeps track of the time-variant amplitude envelope of the input vector.

10. A wireless device comprising a transceiver circuit comprising: a frequency equalization circuit configured to apply a frequency equalization filter to an input vector to linearize a gain error of the input vector in each of a plurality of modulation frequencies to thereby generate a frequency-equalized input vector; and a gain error correction circuit configured to: apply a complex filter to the frequency-equalized input vector to superimpose a respective linearized gain error in a selected modulation frequency among the plurality of modulation frequencies onto a respective linearized gain error in a reference modulation frequency among the plurality of modulation frequencies; determine a linearized gain error correction term in the selected modulation frequency based on the respective linearized gain error in the reference modulation frequency; and apply the determined linearized gain error correction term to the frequency-equalized input vector to thereby generate an equalized input vector in the selected modulation frequency.

11. The wireless device of claim 10, wherein the gain error correction circuit comprises: an equalizer circuit configured to apply the complex filter to the frequency-equalized input vector to superimpose the respective linearized gain error in the selected modulation frequency onto the respective linearized gain error in the reference modulation frequency; a vector-to-real (V2R) converter configured to extract a real parameter from the superimposed frequency-equalized input vector, wherein the real parameter indicates an amount of shift that is required to superimpose the respective linearized gain error in the selected modulation frequency onto the respective linearized gain error in the reference modulation frequency; a scaler configured to scale the real parameter based on a scaling factor to thereby generate a scaled real parameter; a lookup table (LUT) circuit configured to determine a decibel gain error correction term in the reference modulation frequency based on the scaled real parameter; a converter circuit configured to convert the decibel gain error correction term into the linearized gain error correction term; and a multiplier circuit configured to multiply the linearized gain error correction term with the frequency-equalized input vector to thereby generate the equalized input vector.

12. The wireless device of claim 10, wherein the transceiver circuit further comprises a digital baseband circuit configured to generate the input vector in the selected modulation frequency.

13. The wireless device of claim 10, wherein the transceiver circuit further comprises a modulation circuit configured to convert the equalized input vector into a radio frequency (RF) signal and modulate the RF signal onto one of an intermediate frequency and a carrier frequency.

14. The wireless device of claim 10, wherein the transceiver circuit further comprises a memory digital predistortion (mDPD) circuit configured to correct a residual gain error in the equalized input vector.

15. The wireless device of claim 10, wherein the transceiver circuit further comprises a delay circuit configured to delay the frequency-equalized input vector to compensate for a group delay associated with the gain error correction circuit.

16. The wireless device of claim 10, wherein the transceiver circuit further comprises: a digital baseband circuit configured to generate the input vector in the selected modulation frequency; a modulation circuit configured to convert the equalized input vector into a radio frequency (RF) signal and modulate the RF signal onto one of an intermediate frequency and a carrier frequency; a memory digital predistortion (mDPD) circuit configured to correct a residual gain error in the equalized input vector; and a delay circuit configured to delay the frequency-equalized input vector to compensate for a group delay associated with the gain error correction circuit.

17. The wireless device of claim 16, wherein the transceiver circuit further comprises: an envelope detection circuit configured to detect a time-variant amplitude envelope of the input vector; and a target voltage circuit configured to generate a time-variant target voltage envelope that keeps track of the time-variant amplitude envelope of the input vector.

18. The wireless device of claim 17, further comprising: a power management integrated circuit (PMIC) configured to generate a modulated voltage having a time-variant modulated voltage envelope that tracks the time-variant target voltage envelope; and a power amplifier circuit configured to amplify the RF signal based on the modulated voltage.

19. The wireless device of claim 10, wherein the reference modulation frequency is a center modulation frequency among the plurality of modulation frequencies.

20. A method for correcting an amplitude error in a wireless device comprising: applying a frequency equalization filter to an input vector to linearize a gain error of the input vector in each of a plurality of modulation frequencies to thereby generate a frequency-equalized input vector; applying a complex filter to the frequency-equalized input vector to superimpose a respective linearized gain error in a selected modulation frequency among the plurality of modulation frequencies onto a respective linearized gain error in a reference modulation frequency among the plurality of modulation frequencies; determining a linearized gain error correction term in the selected modulation frequency based on the respective linearized gain error in the reference modulation frequency; and applying the determined linearized gain error correction term to the frequency-equalized input vector to thereby generate an equalized input vector in the selected modulation frequency.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0012] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0013] FIG. 1 is a schematic diagram of an exemplary wireless communication circuit, wherein an unwanted voltage distortion filter may cause an amplitude-amplitude (AM-AM) error in a power amplifier circuit when the power amplifier circuit is coupled to a radio frequency (RF) frontend circuit;

[0014] FIG. 2 is a graphic diagram illustrating a distribution of the AM-AM error across a modulation bandwidth of the wireless communication circuit of FIG. 1;

[0015] FIG. 3 is a graphic diagram illustrating a low-complexity AM-AM error correction scheme that can effectively correct the AM-AM error in the wireless communication circuit of FIG. 1;

[0016] FIG. 4 is a schematic diagram of an exemplary transceiver circuit configured to correct the AM-AM error in the wireless communication circuit based on the low-complexity AM-AM error correction scheme described in FIG. 3;

[0017] FIG. 5 is a schematic diagram of an exemplary user element (e.g., wireless device) wherein the transceiver circuit of FIG. 4 can be provided; and

[0018] FIG. 6 is a flowchart of an exemplary process for correcting an amplitude error in the user element of FIG. 5.

DETAILED DESCRIPTION

[0019] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0020] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

[0021] It will be understood that when an element such as a layer, region, or substrate is referred to as being on or extending onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or extending directly onto another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being over or extending over another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over or extending directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.

[0022] Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] Embodiments of the disclosure relate to low-complexity amplitude error correction in a wireless communication circuit. The wireless communication circuit includes a transceiver circuit, a power management integrated circuit (PMIC), and a power amplifier circuit(s). The transceiver circuit generates a radio frequency (RF) signal(s) from an input vector, the PMIC generates a modulated voltage, and the power amplifier circuit(s) amplifies the RF signal(s) based on the modulated voltage. When the power amplifier circuit(s) is coupled to an RF frontend circuit (e.g., filter/multiplexer), an output reflection coefficient (e.g., S.sub.22) of the power amplifier circuit(s) can interact with an input reflection coefficient (e.g., S.sub.11) of the RF frontend circuit to create a voltage distortion filter on an output stage of the power amplifier circuit(s), which can cause an unwanted amplitude-amplitude (AM-AM) error across a modulation bandwidth of the wireless communication circuit.

[0026] In this regard, in embodiments disclosed herein, the transceiver circuit is configured to equalize the input vector to thereby correct the AM-AM error across the modulation bandwidth. Unlike conventional methods where complicated memory digital predistortion (mDPD) coefficients must be defined and calibrated for each modulation frequency within the modulation bandwidth, the transceiver circuit is configured herein to eliminate modulation frequency dependency of the AM-AM error. As a result, it is possible to correct the AM-AM error across the modulation bandwidth with reduced complexity to thereby improve efficiency and linearity of the wireless communication circuit.

[0027] FIG. 1 is a schematic diagram of an exemplary wireless communication circuit 10 (a.k.a. wireless device), wherein an unwanted voltage distortion filter H.sub.IV(s) may cause an AM-AM error in a power amplifier circuit 12 when the power amplifier circuit 12 is coupled to a radio frequency (RF) frontend circuit 14. Notably, in the unwanted voltage distortion filter H.sub.IV(s), s is a notation of Laplace transform. The wireless communication circuit 10 includes a transceiver circuit 16, and a power management integrated circuit (PMIC) 18, and a transmitter circuit 20, which can include an antenna(s) (not shown) as an example.

[0028] The transceiver circuit 16 is configured to generate an RF signal 22 having a time-variant input power PIN(t) that corresponds to a time-variant voltage envelope 24 and provides the RF signal 22 to the power amplifier circuit 12. The transceiver circuit 16 is also configured to generate a time-variant target voltage V.sub.TGT, which is associated with a time-variant target voltage envelope 26 that tracks the time-variant voltage envelope 24 of the RF signal 22. The PMIC 18 is configured to generate a modulated voltage V.sub.CC having a time-variant modulated voltage envelope 28 (e.g., an average power tracking voltage) that tracks the time-variant target voltage envelope 26 of the time-variant target voltage V.sub.TGT and provides the modulated voltage V.sub.CC to the power amplifier circuit 12. The power amplifier circuit 12 is configured to amplify the RF signal 22 based on the modulated voltage V.sub.CC to a time-variant output voltage V.sub.OUT associated with a time-variant output voltage envelope 30. The power amplifier circuit 12 then provides the amplified RF signal 22 to the RF frontend circuit 14. The RF frontend circuit 14 may be a filter circuit that performs further frequency filtering on the amplified RF signal 22 before providing the amplified RF signal 22 to the transmitter circuit 20 for transmission.

[0029] When the power amplifier circuit 12 is coupled to the RF frontend circuit 14, the unwanted voltage distortion filter H.sub.IV(s) can cause a frequency-dependent AM-AM error across all modulation frequencies across the modulation bandwidth. For a detailed analysis as to how the unwanted voltage distortion filter H.sub.IV(s) can be created by the coupling of the power amplifier circuit 12 and the RF frontend circuit 14, please refer to U.S. patent application Ser. No. 17/939,350, entitled PHASE AND AMPLITUDE ERROR CORRECTION IN A TRANSMISSION CIRCUIT.

[0030] FIG. 2 is a graphic diagram illustrating a distribution of the AM-AM error across an entire modulation bandwidth 32 of the wireless communication circuit 10 of FIG. 1. The modulation bandwidth 32 includes multiple modulation frequencies f.sub.1-f.sub.N. Each of the modulation frequencies f.sub.1-f.sub.N corresponds to a respective time-variant gain error that is dependent on the time-variant input power P.sub.IN(t). In other words, the gain error has a dependency on both the modulation frequencies f.sub.1-F.sub.N and the time-variant input power P.sub.IN(t).

[0031] A conventional approach for correcting such gain error is to employ a memory digital predistortion (mDPD) circuit in the transceiver circuit 16 to inject a gain error correction term into the RF signal 22. However, given the frequency and power dependency of the gain error, the mDPD circuit must define and calibrate a respective set of complex coefficients for each of the modulation frequencies f.sub.1-f.sub.N. Notably, to operate in a fifth generation (5G) or a 5G new-radio (5G-NR) system, the wireless communication circuit 10 often needs to support a wide modulation bandwidth (e.g., >200 MHZ). As such, a number of the modulation frequencies f.sub.1-f.sub.N can increase significantly, thus leading to a significantly increased complexity with respect to implementation and calibration of the mDPD coefficients. Hence, it is desirable to enhance the wireless communication circuit 10 based on a low-complexity AM-AM error correction scheme to effectively correct the gain error across the entire modulation bandwidth 32.

[0032] FIG. 3 is a graphic diagram illustrating a low-complexity AM-AM error correction scheme that can effectively correct the AM-AM error in the wireless communication circuit 10 of FIG. 1. Herein, the low-complexity AM-AM correction scheme is able to reduce complexity associated with AM-AM error correction by eliminating modulation frequency dependency of the gain error.

[0033] First of all, the gain error associated with each of the modulation frequencies f.sub.1-f.sub.N is first linearized with respect to the time-variant input power P.sub.IN(t). As shown in FIG. 3, the linearized gain error associated with each of the modulation frequencies f.sub.1-f.sub.N is independent from the time-variant input power P.sub.IN(t).

[0034] Next, a reference modulation frequency f.sub.REF among the modulation frequencies f.sub.1-f.sub.N is chosen and a set of linearized gain error correction terms is defined for the reference modulation frequency f.sub.REF. In a non-limiting example, the reference modulation frequency f.sub.REF can be a center modulation frequency among the modulation frequencies f.sub.1-f.sub.N.

[0035] Subsequently, the linearized gain error of any selected one of the modulation frequencies f.sub.1-f.sub.N can be superimposed onto the linearized gain error of the reference modulation frequency f.sub.REF. Herein, the phrase superimposing refers to a process for determining an appropriate x-axis shift (e.g., a vector) to align a respective linearized gain error of any selected one of the modulation frequencies f.sub.1-f.sub.N with the respective linearized gain error of the reference modulation frequency f.sub.REF.

[0036] As shown in FIG. 3, superimposing the linearized gain error of the modulation frequency f.sub.1 onto the linearized gain error of the reference modulation frequency f.sub.REF is equivalent to shifting the linearized gain error of the modulation frequency f.sub.1 rightward along the x-axis. Likewise, superimposing the linearized gain error of the modulation frequency f.sub.N onto the linearized gain error of the reference modulation frequency f.sub.REF is equivalent to shifting the linearized gain error of the modulation frequency f.sub.N leftward along the x-axis. By superimposing the linearized gain error of each of the modulation frequencies f.sub.1-f.sub.N onto the linearized gain error of the reference modulation frequency f.sub.REF, it is possible to determine a respective linearized gain error correction term for each of the modulation frequencies f.sub.1-f.sub.N based on the set of linearized gain error correction terms defined for the reference modulation frequency f.sub.REF. In this regard, the complexity associated with AM-AM error correction only revolves around the reference modulation frequency f.sub.REF, as opposed to having to involve all the modulation frequencies f.sub.1-f.sub.N. As a result, the low-complexity AM-AM error correction scheme, as further described in FIG. 4 below, is clearly advantageous over the conventional methods where complicated mDPD coefficients must be defined and calibrated for each of the modulation frequencies f.sub.1-f.sub.N.

[0037] FIG. 4 is a schematic diagram of an exemplary transceiver circuit 34 configured to correct the AM-AM error in the wireless communication circuit 10 based on the low-complexity AM-AM error correction scheme described in FIG. 3. The transceiver circuit 34 can be provided in the wireless communication circuit 10 to replace the transceiver circuit 16. By replacing the transceiver circuit 16 with the transceiver circuit 34, the wireless communication circuit 10 can be adapted to support the low-complexity AM-AM error correction scheme of the present disclosure.

[0038] The transceiver circuit 34 includes a digital baseband circuit 36, a frequency equalization circuit 38, a gain error correction circuit 40, and a modulation circuit 42. In an embodiment, the gain error correction circuit 40 includes a lookup table (LUT) circuit 44, which may be preprogrammed to store a set of decibel gain error correction terms ?Gain-dB associated with the reference modulation frequency f.sub.REF. As previously described in FIG. 3, each of the modulation frequencies f.sub.1-f.sub.N can be superimposed on the reference modulation frequency f.sub.REF by shifting a respective one of the modulation frequencies f.sub.1-f.sub.N leftward or rightward. In this regard, in a non-limiting example, the LUT circuit 44 can be programmed to correlate different amounts of a leftward or rightward shift with different decibel gain error correction terms ?Gain-dB. As such, once the amount of the leftward or rightward shift associated with a respective one of the modulation frequencies f.sub.1-f.sub.N is determined, the LUT circuit 44 will be able to provide a corresponding decibel gain error correction term ?Gain-dB for the respective one of the modulation frequencies f.sub.1-f.sub.N.

[0039] The digital baseband circuit 36 is configured to generate an input vector {right arrow over (b.sub.MOD)} in a selected modulation frequency among the modulation frequencies f.sub.1-f.sub.N across the modulation bandwidth 32. The frequency equalization circuit 38 is configured to apply a frequency equalization filter H.sub.FEQ(s) to the input vector {right arrow over (b.sub.MOD)} to generate a frequency-equalized input vector {right arrow over (b.sub.MOD-FE)}, in which the respective gain error in each of the modulation frequencies f.sub.1-f.sub.N is linearized. As previously illustrated in FIG. 3, the linearized gain error associated with each of the modulation frequencies f.sub.1-f.sub.N becomes independent from the time-variant input power P.sub.IN(t).

[0040] In an embodiment, the gain error correction circuit 40 includes an equalizer circuit 46, a vector-to-real (V2R) converter 48, a scaler 50, a converter circuit 52, and a multiplier circuit 54. The equalizer circuit 46 is configured to apply a complex filter HG(s) to the frequency-equalized input vector {right arrow over (b.sub.MOD-FE)} to superimpose the respective linearized gain error in a selected one of the modulation frequencies f.sub.1-f.sub.N onto the respective linearized gain error in the reference modulation frequency f.sub.REF.

[0041] The V2R converter 48 is configured to extract a real parameter X.sub.R from the superimposed frequency-equalized input vector {right arrow over (b.sub.MOD-FE)}. The scaler 50 may be configured to scale the real parameter X.sub.R based on a scaling factor Fs to generate a scaled real parameter X.sub.RS. According to an embodiment of the present disclosure, the scaled real parameter X.sub.RS represents an amount of the leftward (e.g., a negative number) or rightward (e.g., a positive number) shift that is required to superimpose the linearized gain error of the selected one of the modulation frequencies f.sub.1-f.sub.N onto the linearized gain error of the reference modulation frequency f.sub.REF. Understandably, if the selected one of the modulation frequencies f.sub.1-f.sub.N is the same as the reference modulation frequency f.sub.REF, then the leftward or rightward shift will not be needed.

[0042] Based on the scaled real parameter X.sub.RS, the LUT circuit 44 is able to determine a corresponding decibel gain error correction term ?Gain-dB in the reference modulation frequency f.sub.REF. The converter circuit 52 then converts the decibel gain error correction term ?Gain-dB into a linearized gain error correction term ?Gain for the selected one of the modulation frequencies f.sub.1-f.sub.N. Accordingly, the multiplier circuit 54 can multiply the linearized gain error correction term ?Gain with the frequency-equalized input vector {right arrow over (b.sub.MOD-FE)} to thereby generate an equalized input vector {right arrow over (b.sub.MOD-EQ)} that can correct the AM-AM error in the power amplifier circuit 12 in FIG. 1. Subsequently, the modulation circuit 42 can convert the equalized input vector {right arrow over (b.sub.MOD-EQ)} into the RF signal 22 and modulate the RF signal 22 onto an intermediate frequency (IF) or a carrier frequency.

[0043] The transceiver circuit 34 may include an mDPD circuit 56. In an embodiment, the mDPD circuit 56 can be configured to correct any residual gain error in the equalized input vector {right arrow over (b.sub.MOD-EQ)}. The transceiver circuit 34 may also include a delay circuit 58, which can be configured to delay the frequency-equalized input vector {right arrow over (b.sub.MOD-FE)} to compensate for a group delay associated with the gain error correction circuit 40.

[0044] The transceiver circuit 34 further includes an envelope detection circuit 60 and a target voltage circuit 62. The envelope detection circuit 60 is configured to detect a time-variant amplitude envelope ?{square root over (I.sup.2+Q.sup.2)} of the input vector {right arrow over (b.sub.MOD)}, wherein I and Q represent an in-phase component and a quadrature component of the input vector {right arrow over (b.sub.MOD)}, respectively. The target voltage circuit 62 is configured to generate the time-variant target voltage V.sub.TGT that keeps track of the time-variant amplitude envelope ?{square root over (I.sup.2+Q.sup.2)} of the input vector {right arrow over (b.sub.MOD)}.

[0045] The transceiver circuit 34 of FIG. 4 can be provided in a user element (e.g., wireless device) to provide the low-complexity AM-AM error correction according to the embodiments described above. In this regard, FIG. 5 is a schematic diagram of an exemplary user element 100 wherein the transceiver circuit 34 of FIG. 4 can be provided.

[0046] Herein, the user element 100 can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0047] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0048] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 110. The multiple antennas 112 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0049] The user element 100 of FIG. 5 can be configured to correct amplitude error based on a process. In this regard, FIG. 6 is a flowchart of an exemplary process 200 for correcting amplitude error in the user element 100 of FIG. 5.

[0050] Specifically, the process 200 includes applying the frequency equalization filter H.sub.FEQ(s) to the input vector {right arrow over (b.sub.MOD)} to linearize the gain error of the input vector {right arrow over (b.sub.MOD)} in each of the modulation frequencies f.sub.1-f.sub.N to thereby generate the frequency-equalized input vector {right arrow over (b.sub.MOD-FE)} (step 202). The process 200 also includes applying the complex filter HG(s) to the frequency-equalized input vector {right arrow over (b.sub.MOD-FE)} to superimpose the respective linearized gain error in the selected modulation frequency among the modulation frequencies (f.sub.1-f.sub.N) onto the respective linearized gain error in the reference modulation frequency f.sub.REF among the modulation frequencies f.sub.1-f.sub.N (step 204). The process 200 also includes determining the linearized gain error correction term ?Gain in the selected modulation frequency based on the respective linearized gain error in the reference modulation frequency f.sub.REF (step 206). The process 200 also includes applying the determined linearized gain error correction term ?Gain to the frequency-equalized input vector {right arrow over (b.sub.MOD-FE)} to thereby generate the equalized input vector {right arrow over (b.sub.MOD-EQ)} in the selected modulation frequency (step 208).

[0051] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.