RADAR CIRCUIT

Abstract

A radar circuit for a measuring device is provided, including: a radar chip, configured to generate a radar measurement signal; an application-specific integrated circuit (ASIC); and a processor, configured to determine a measured value, the ASIC and the radar chip being separate components.

Claims

1. A radar circuit for a measuring device, comprising: a radar chip, configured to generate a radar measurement signal; an application-specific integrated circuit (ASIC); and a processor, configured to determine a measured value, wherein the ASIC and the radar chip are separate components.

2. The radar circuit according to claim 1, wherein the ASIC comprises a phase locked loop (PLL).

3. The radar circuit according to claim 1, wherein the ASIC comprises an analog-to-digital converter (ADC) circuit.

4. The radar circuit according to claim 1, wherein the ASIC has a digital interface to the processor.

5. The radar circuit according to claim 1, wherein the ASIC has a finite state machine (FSM), which is configured to control the radar chip.

6. The radar circuit according to claim 1, wherein the radar chip is a radar monolythic microwave integrated circuit (MMIC).

7. The radar circuit according to claim 1, wherein the ASIC is a radar companion ASIC, which is configured to perform control tasks and/or measured value acquisition tasks in the radar circuit.

8. The radar circuit according to claim 1, wherein the radar circuit is a level radar circuit for a level radar measuring device.

9. The radar circuit according to claim 1, wherein the ASIC is configured to wake the processor from a sleep mode and thereupon transmit measurement data to the processor.

10. The radar circuit according to claim 1, wherein the ASIC is configured to supply a voltage-controlled oscillator (VCO) of the radar chip and/or a multiplier of the radar chip.

11. An application-specific integrated circuit (ASIC) configured for a level radar measuring device, which comprises a radar chip, the ASIC and the radar chip being separate components.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0028] In the following, embodiments of the present disclosure are described with reference to the figures. If the same reference signs are used in the following description of the figures, these designate the same or similar elements. The illustrations in the figures are schematic and not to scale.

[0029] FIG. 1 shows a circuit diagram of a radar MMIC with a peripheral circuit using discrete components;

[0030] FIG. 2 shows a radar companion ASIC that can take over control and detection tasks when operating a purely analog MMIC;

[0031] FIG. 3 shows the structure of a radar circuit for a radar measuring device with the ASIC of FIG. 2;

[0032] FIG. 4 illustrates the universal usability of the Radar Companion ASIC for widely used radar MMICs for level measurement;

[0033] FIG. 5 shows the time sequence for energy-optimized recording of measured values;

[0034] FIG. 6 shows an example of the states of a processor during the energy-optimized acquisition of measured values;

[0035] FIG. 7 shows an example of the states of a Radar Companion ASIC during the energy-optimized acquisition of measured values; and

[0036] FIG. 8 shows a measuring device with a radar circuit.

DETAILED DESCRIPTION OF EMBODIMENTS

[0037] FIG. 1 shows a radar MMIC 101 with a peripheral circuit using discrete components. The radar MMIC 101 generates a radar measurement signal of 80 GHz, which is emitted via the antenna 118 in the direction of the product. The MMIC 101 has a VCO 107, which is controlled by an external PLL 104. A temperature-compensated crystal oscillator (TCXO) 115 is provided, which controls the PLL with a frequency of 40 MHz. The TCXO also controls the ADC circuit 105.

[0038] In addition to the VCO 107, the MMIC 101 has a multiplier 108, which is controlled by the VCO 107 at 40 GHz. The multiplier doubles the frequency to 80 GHz and controls a TX amplifier 109, which is connected to the antenna 118 via a transmit/receive switch, for example a circulator. In addition, a down converter or mixer 110 is provided, which receives signals from the multiplier 108 and the transmit/receive switch.

[0039] All other components are located outside the MMIC 101. The down converter 110 passes its signal to an analog amplifier and filter circuit 113, which then passes it on to the ADC circuit 105. The ADC circuit 105 is connected to the processor 103 via a serial peripheral interface (SPI), for example. The processor 103 can exchange data with an external memory 116. In addition, the processor 103 is connected to a fieldbus modem 117 for measured value transmission.

[0040] FIG. 2 shows a radar companion ASIC 102, which can perform control and detection tasks when operating a purely analog MMIC. The ASIC 102 has a linearization circuit, for example a integer or fractionally rational PLL 104, a power supply 111, a self-test circuit 201, an analogue amplification and filter circuit 113, an ADC circuit 105 (which is set up, for example, to convert analogue signals into digital values with an accuracy of 16 bits and a sampling frequency of 40 MHz), a first-in-first-out (FiFo) memory 202, and a finite state machine 203. The ASIC 102 is a separate component, but can be arranged on the same circuit board as the MMIC 101 (see FIG. 3).

[0041] FIG. 3 shows the structure of a radar circuit 100 for a radar measuring device, which has the ASIC 102 or radar companion ASIC 102 described above. The ASIC 102 is connected between the radar chip 101 and the processor 103. Communication between ASIC 102 and processor 103 takes place, for example, via the FiFo 202 by means of a quad serial peripheral interface (QSPI) and, starting from processor 103, via an SPI interface to FSM 203.

[0042] The ASIC 102 can supply the VCO 107 and the multiplier 108 of the MMIC 101 with energy and perform or trigger a self-test of the MMIC 101 (see FIG. 3). In particular, the RC-ASIC 102 can be used to check the function of the MMIC 101. This is particularly advantageous for SIL applications. It is possible that the processor 103 is integrated on the ASIC 102. However, it can also be a separate component, as shown in FIG. 3.

[0043] In particular, the MMIC 101 and the RC-ASIC 102 can be manufactured using different semiconductor technologies and chip materials. For example, the MMIC can be optimized for use at high frequencies, for example 80 GHz or above, whereas the RC-ASIC 102 is optimized for applications at significantly lower frequencies, for example 40 MHz. This can save energy or production costs compared to integrating the ASIC module on an MMIC.

[0044] FIG. 4 shows the universal usability of the RC-ASIC 102 for radar MMICs for level measurement, which are designed for very different frequency ranges, for example for 6 GHz, 24 GHz, 80 GHz, 180 GHz, or 240 GHz.

[0045] FIG. 5 shows a time sequence for the energy-optimized acquisition of measured values. Certain steps take place at the times t.sub.1 to t.sub.6, which are described below with reference to FIGS. 6 and 7.

[0046] The first diagram shows the energy consumed by the processor 103 over time. Initially, the processor is in sleep mode and is then woken up externally to start a new measurement run. After a period of increased energy demand (for example during an initialization phase of the processor), the energy demand decreases again and then increases again. The second diagram shows the energy requirement of the RC-ASIC 102 over time, which is woken up by the processor 103 at a specific time t.sub.1 and has the highest energy requirement precisely in the period in which the energy requirement of the processor has fallen again.

[0047] The third diagram shows the energy requirement of the MMIC 101 over time, which has an increased energy requirement precisely when the processor has a low energy requirement.

[0048] And the last diagram shows the energy consumption of a fieldbus modem over time, which is used to transmit the measured values. The measured value transmission takes place at the end of a cycle when the MMIC is in sleep mode.

[0049] FIG. 6 shows an example of the states of the processor 103 during the energy-optimized acquisition of measured values. The process starts in step 601. The processor is started in step 602. This takes place at time t.sub.0 (see also FIG. 5). At time t.sub.1, the RC-ASIC is activated in step 603, which is then configured in step 604. In step 605, at time t.sub.2, a start command is sent to the RC-ASIC and in step 606 the energy-saving mode of the processor is activated. In step 607, it is assessed whether the processor has received an interrupt request (IRQ) from the RC-ASIC.

[0050] If this is not the case, the system waits and then checks again whether an IRQ has been received from the RC-ASIC. If an IRQ has been received, step 608 takes place at time t.sub.4, namely the reactivation of the processor, whereupon the processor reads data from the first-in-first-out memory of the RC-ASIC in step 609.

[0051] At time t.sub.5, the RC-ASIC is deactivated in step 610, whereupon the processor determines the measured value from the data read out by the FiFo in step 611. At time t.sub.6, the measured value is provided in step 612 and the process ends with step 613.

[0052] FIG. 7 shows an example of the states of a RC-ASIC during the energy-optimized acquisition of measured values. The procedure starts with step 701, whereupon the RC-ASIC is activated by the processor at time t.sub.1 in step 702. In step 703, the configuration of the RC-ASIC is set under the control of the processor. For this purpose, specific operating parameters adapted to the respective connected MMIC are set, which may differ depending on the operating frequency of the connected MMIC. In step 704, it is determined whether the ASIC has received a start command. If this is not the case, the system waits and checks again whether a start command has been received. If this is the case, the PLL is activated in step 705 at time t.sub.2. In step 706, the VCO and multiplier are supplied with power under the control of the RC-ASIC and in step 707 IF Gain, ADC and FiFo are activated and/or supplied with power by the RC-ASIC. At time t.sub.3, the TX amplifier and the down converter are supplied and then the measurement is performed in step 709. It should be noted here that the times t.sub.2, t.sub.3, t.sub.4, t.sub.5 in particular should be determined depending on the MMIC connected in each case, whereby the RC-ASIC is set up to be able to implement the different times here. At time t.sub.4, the MMIC is disconnected from the power supply under the control of the RC-ASIC and in step 711 the PLL, IF Gain and ADC are again deactivated or disconnected from the power supply by the RC-ASIC. In step 712, the processor is woken up again (by the RC-ASIC) and in step 713 the RC-ASIC supplies data to the processor. At time t.sub.5, the RC-ASIC is deactivated in step 714. The procedure then continues with step 715.

[0053] FIG. 8 shows a measuring device 200, for example a radar level measuring device, with the radar circuit 100 described above, which has a level radar antenna 118 for emitting the radar measuring signal and for receiving the radar measuring signal reflected at the product surface.

[0054] The terms used in the claims should be construed so as to give them the broadest reasonable interpretation consistent with the foregoing description. For example, the use of the article a or the when introducing an element should not be construed to exclude a plurality of elements. Similarly, the mention of or should be construed to include a plurality of elements, so that the mention of A or B does not exclude A and B unless it is clear from the context or the preceding description that only one of A and B is meant. Furthermore, the phrase at least one of A, B, and C should be understood as one or more of a group of elements consisting of A, B and C, and should not be interpreted as requiring at least one of each of the listed elements A, B, and C, regardless of whether A, B, and C are combined as categories or otherwise. In addition, the mention of A, B, and/or C or at least one of A, B, or C should be construed to include any single unit of the listed elements, e.g., A, any subset of the listed elements, e.g., A and B, or the entire list of elements A, B, and C.