CALIBRATION METHOD AND TUNING METHOD FOR ON-CHIP DIFFERENTIAL ACTIVE RC FILTER

Abstract

A calibration method and a tuning method for an on-chip differential active RC filter are provided. The calibration method comprises: obtaining zero-crossing time of a differential signal outputted by a single-pole point real number filter by analyzing the single-pole point real number filter; setting a reference clock period according to the relationship between the zero-crossing time and the bandwidth of the single-pole point real number filter, and setting a calibration working time sequence according to the reference clock period; and scanning an RC configuration of an RC array according to the calibration working time sequence to realize calibration of the RC array.

Claims

1. A calibration method for an on-chip differential active RC filter, comprising: obtaining a zero-crossing time of a differential signal outputted by a single-pole point real number filter by analyzing the single-pole point real number filter; setting a reference clock period according to a relationship between the zero-crossing time and a bandwidth of the single-pole point real number filter, and setting a calibration working time sequence according to the reference clock period; and scanning an RC configuration of an RC array according to the calibration working time sequence to realize calibration of the RC array, wherein scanning the RC configuration of the RC array according to the calibration working time sequence comprises: step one: arranging a pulse generation unit connected to an input terminal of the single-pole point real number filter, outputting a pulse signal by the pulse generation unit according to the calibration working time sequence, and presetting an RC configuration for the RC array; step two: sampling, through a comparator, the differential signal outputted by the single-pole point real number filter according to the pulse signal, and obtaining a comparison result; step three: determining a size relationship between a current bandwidth of the single-pole point real number filter and a target bandwidth of the single-pole point real number filter according to the comparison result; and step four: setting a next set of RC configuration in the RC array by using a successive approximation algorithm, repeating step two and step three; until an operation of the successive approximation algorithm is finished, so that an RC configuration with a bandwidth closest to the target bandwidth is obtained, and completing the calibration of the RC array, wherein a compensation unit is arranged according to an operational amplifier delay of an operational amplifier in the single-pole point real number filter, so that the comparator is delayed based on the operational amplifier delay and then the comparator samples an output voltage of the single-pole point real number filter, wherein the compensation unit is an inverter chain configured to perform a fixed delay on a comparator sampling control signal to cancel the operational amplifier delay, wherein the pulse generation unit is composed of a resistive voltage divider structure and two switch groups with opposite phases, wherein the resistive voltage divider structure is composed of two resistors R.sub.a and one resistor R.sub.b, one terminal of one of the two resistors R.sub.a acts as a power terminal of the resistive voltage divider structure, and one terminal of the resistor R.sub.b acts as a ground terminal of the resistive voltage divider structure, the two resistors R.sub.a and the one resistor R.sub.b are sequentially connected in series between the power terminal and the ground terminal, the power terminal also acts as a first direct current (DC) signal terminal, one terminal that the two resistors R.sub.a are connected with each other is a common-mode reference voltage terminal, and one terminal that one of the two resistors R.sub.a connected to the resistor R.sub.b acts as a second DC signal terminal, wherein the two switch groups are composed of a third switch group and a fourth switch group whose switching state is opposite to that of the third switch group; the third switch group is composed of a first switch and a second switch, and two terminals of the first switch are respectively connected to the first DC signal terminal and a first input terminal of the single-pole point real number filter in one-to-one manner; two terminals of the second switch are respectively connected to the second DC signal terminal and a second input terminal of the single-pole point real number filter in one-to-one manner; the fourth switch group is composed of a third switch and a fourth switch, and two terminals of the third switch are respectively connected to the first DC signal terminal and the first input terminal of the single-pole point real number filter in one-to-one manner, two terminals of the fourth switch are respectively connected to the second DC signal terminal and the second input terminal of the single-pole point real number filter in one-to-one manner.

2. The calibration method for the on-chip differential active RC filter according to claim 1, further comprising: changing a transfer function of the single-pole point real number filter through an inverse Laplace transform, obtaining a differential time domain response of the single-pole point real number filter with respect to a falling edge of a pulse input; and obtaining the zero-crossing time according to that the differential time domain response at an output of the single-pole point real number filter is zero, wherein the zero-crossing time is: $\mathrm{tr}=\ln \left(2\right)?,$ wherein ? is a time constant, $?=\frac{1}{2?f_n},$ and f.sub.n is the bandwidth of the single-pole point real number filter.

3. The calibration method for the on-chip differential active RC filter according to claim 2, wherein the reference clock period is: $T=\ln \left(2\right)\frac{1}{2?f_{n1}},$ wherein f.sub.n1 is the target bandwidth of the single-pole point real number filter.

4. The calibration method for the on-chip differential active RC filter according to claim 1, wherein in step three: if the comparator outputs a high level, a current zero-crossing time of the differential signal is ahead of the reference clock period, indicating that a bandwidth obtained through a current RC configuration is excessively large; and if the comparator outputs a low level, the current zero-crossing time of the differential signal lags behind the reference clock period, indicating that the bandwidth obtained through the current RC configuration is excessively small.

5. The calibration method for the on-chip differential active RC filter according to claim 1, wherein an input terminal of the comparator is connected to a first switch group, a second switch group, and a sampling capacitor; wherein the first switch group is connected to an output terminal of the single-pole point real number filter, and the second switch group is connected to the pulse generation unit.

6. A tuning method for an on-chip differential active RC filter, wherein: according to a target bandwidth of a single-pole point real number filter, using the calibration method according to claim 1 to tune an RC array.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] FIG. 1 is a schematic diagram of an overall structure of an active RC filter calibration circuit according to the invention.

[0039] FIG. 2 is a waveform graph of a calibration working time sequence according to the invention.

[0040] FIG. 3 is a waveform graph of an output performed by a single-pole point real number filter during calibration according to the invention.

[0041] FIG. 4 is a schematic graph of calibration waveforms affected by a bandwidth of an operational amplifier according to the invention.

[0042] FIG. 5 is a schematic graph of errors caused by the operational amplifier at different K values according to the invention.

[0043] FIG. 6 is a schematic graph of operational amplifier delays of the operational amplifier under a general time scale according to the invention.

[0044] FIG. 7 is a schematic diagram of capacitor array successive approximation.

[0045] FIG. 8 is a waveform diagram simulating the capacitor array successive approximation.

DESCRIPTION OF THE EMBODIMENTS

[0046] The invention will be further described below in combination with the embodiments, and the embodiments do not constitute any limitation on the invention. A limited number of modifications made by anyone within the scope of the claims of the invention are still within the scope of the claims of the invention.

[0047] In a calibration method for an on-chip differential active RC filter provided by the invention, zero-crossing time of a differential signal V.sub.out outputted by a single-pole point real number filter is obtained by analyzing the single-pole point real number filter. A reference clock period is set according to a relationship between the zero-crossing time and a bandwidth of the single-pole point real number filter, and a calibration working time sequence is set according to the reference clock period. An RC configuration of an RC array is scanned according to the calibration working time sequence to realize calibration of the RC array.

[0048] A reference voltage is not required in the entire calibration process, so that the complexity of a calibration circuit is reduced. By setting the calibration working time sequence, the RC array on the filter may be multiplexed when a time constant is tested, and an RC array is not required to be additionally added, so an area occupied by the calibration circuit is reduced.

[0049] AS shown in FIG. 1, this figure is a schematic diagram of a structure of an active RC filter calibration circuit according to the embodiment.

[0050] In FIG. 1, a pulse generation unit generates a pulse input required to test a time constant 1.

[0051] A single-pole point real number filter is the basic module that constitutes a higher-order active RC filter. A single-pole point real number filter is mainly formed by an operational amplifier and an RC array. During the calibration of the RC array, the RC array may be isolated by simply disconnecting the single-pole point real number filter from other parts in the active RC filter. Therefore, during calibration, there is no need to separately set up a set of RC configuration of the RC array for testing. The RC array on the active RC filter may be multiplexed, and an RC array does not need to be additionally added, so the purpose of reducing the area of the active RC filter is achieved.

[0052] A comparator is used to sample a response of the single-pole point real number filter to a pulse input and detect a relationship between current zero-crossing time and a reference clock period. A comparison result of the comparator is fed back to a control logic module, and the control logic module determines a next set of RC array control words R.sub.T<T:0>, R.sub.P<X:0>, C.sub.P<Y:0> based on a sampling result.

[0053] The theoretical derivation of the zero-crossing time in this embodiment is as follows.

[0054] Assuming that the operational amplifier in the single-pole point real number filter is an ideal operational amplifier, and a transfer function of the single-pole point real number filter is as follows:

[00003]$H\left(s\right)=-\frac{R_P}{R_T}\frac{1}{1+{\mathrm{sR}}_P{C}_P}.$

[0055] Assuming that a pulse amplitude inputted to an input terminal of the operational amplifier is V.sub.a=V.sub.H?V.sub.L. Regardless of a delay caused by the operational amplifier, the transfer function of the single-pole point real number filter is changed through the inverse Laplace transform, and a differential time domain response of the single-pole point real number filter with respect to a falling edge of the pulse input is obtained. The differential time domain response is expressed as:

[00004]$V_{\mathrm{out}}\left(t\right)=V_a?\frac{R_P}{R_T}\left(1+\left(-1-1\right)e^{-\frac{t}{?}}\right)=V_a?\frac{R_P}{R_T}\left(1-2e^{-\frac{t}{?}}\right).$

[0056] Let the differential signal V.sub.out outputted by the single-pole point real number filter be equal to 0, and the time required for a differential signal V.sub.out waveform to rise to a zero-crossing point may be obtained, that is, the zero-crossing time is:

[00005]$\mathrm{tr}=\ln \left(2\right)?,$$?=\frac{1}{2?f_n},$

where ? is the time constant, ?=R.sub.PC.sub.P, and f.sub.n is the bandwidth of the single-pole point real number filter. Different ? corresponds to different bandwidths of the single-pole point real number filter.

[0057] The reference clock period of this embodiment is:

[00006]$T=\ln \left(2\right)\frac{1}{2?f_{n1}},$

wherein f.sub.n1 is a target bandwidth of the single-pole point real number filter. That is, f.sub.n1 is the desired bandwidth of the single-pole point real number filter.

[0058] In order to compare a difference between the time when the differential signal V.sub.out outputted by the operational amplifier rises to the zero-crossing point and the reference clock period during actual operation, the calibration working time sequence as shown in FIG. 2 is set in the invention according to the reference clock period.

[0059] The scanning of the RC configuration of the RC array according to the calibration working time sequence specifically includes the following.

[0060] In step one, a pulse generation unit connected to an input terminal of the single-pole point real number filter is arranged, the pulse generation unit outputs a pulse signal according to the calibration working time sequence, and an RC configuration is preset for the RC array.

[0061] In step two, when a reference clock period is inputted into the pulse signal, the comparator samples the differential signal outputted by the single-pole point real number filter, and a comparison result is obtained.

[0062] In step three, a relationship between a current bandwidth and a target bandwidth of the single-pole point real number filter is determined according to the comparison result.

[0063] In this step:

[0064] If the comparator outputs a high level, then the current zero-crossing time of the differential signal V.sub.out is ahead of the reference clock period, that is tr<T, indicating that a bandwidth obtained through a current RC configuration is excessively large.

[0065] If the comparator outputs a low level, then the current zero-crossing time of the differential signal V.sub.out lags behind the reference clock period, that is, tr>T, indicating that the bandwidth obtained through the current RC configuration is excessively small.

[0066] In step four, a next set of RC configuration is set in the RC array by using a successive approximation algorithm, step two and step three are repeated; until the operation of the successive approximation algorithm is finished, so that an RC configuration with a bandwidth closest to the target bandwidth is thus obtained, and the calibration of the RC array is completed.

[0067] The single-pole point real number filter of this embodiment provides the pulse signal through the pulse generation unit. The pulse generation unit outputs the pulse signal according to the calibration working time sequence, and the pulse signal is the pulse input required by the single-pole point real number filter.

[0068] The pulse generation unit of this embodiment is mainly formed by a resistive voltage divider structure and two switch groups with opposite phases. To be specific, the resistive voltage divider structure mainly is formed by two resistors R.sub.a and one resistor R.sub.b. These three resistors are connected in series between a power terminal and a ground terminal. Herein, one of the resistors R.sub.a is connected to the power terminal, and a connection terminal thereof is a first direct current (DC) signal terminal, which outputs a DC signal V.sub.H. One terminal that the two resistors R.sub.a are connected with each other is a common-mode reference voltage terminal, configured to output a common-mode reference voltage V.sub.cm. The other terminal of the other resistor R.sub.a is connected to one terminal of the resistor R.sub.b, and its connection terminal acts as a second DC signal terminal to output a DC signal V.sub.L. The other terminal of the resistor R.sub.b is connected to ground.

[0069] That is, the resistive voltage divider structure uses resistive voltage division to generate three output voltages. The common-mode voltages outputted and inputted by the single-pole point real number filter are the same, both are the common-mode reference voltages V.sub.cm. Therefore, considering the virtual short characteristics of the operational amplifier, the voltage at point X in FIG. 1 is also the outputted common-mode reference voltage V.sub.cm. Therefore, the current I.sub.p in FIG. 1 is:

[00007]$I_P=\frac{V_H-V_{\mathrm{cm}}}{R_T}.$

[0070] The current I.sub.n is:

[00008]$I_n=\frac{V_{\mathrm{cm}}-V_L}{R_T}.$

[0071] Moreover, since V.sub.cm=(V.sub.H+V.sub.L)/2, I.sub.p=I.sub.n, that is, the current flowing through the resistor R.sub.b is still the input current I.sub.b of the power terminal, that is:

[00009]$V_a=V_H-V_L=2*\left(I_b-I_p\right)*R_a,$$V_{\mathrm{cm}}=I_b*R_b+\left(I_b-I_p\right)*R_a.$

[0072] From the above expression, a decrease in a resistor R.sub.1 may cause the pulse amplitude V.sub.a and the common-mode reference voltage V.sub.cm to reduce. However, the pulse amplitude V.sub.a does not affect the rising of the output of the single-pole point real number filter to the zero-crossing time. However, if the common-mode reference voltage V.sub.cm drops too much, the single-pole point real number filter may not work. Therefore, in order to ensure that an electrical signal provided by the pulse generation unit can make the single-pole point real number filter work effectively and reliably, a resistance value of the resistor R.sub.1 may be set to be much larger than that of the resistors R.sub.a, so that the pulse amplitude V.sub.a and the common-mode reference voltage V.sub.cm may not be significantly affected.

[0073] Preferably, a relationship between the resistor R.sub.a and the resistor R.sub.1 in the invention is set to: R.sub.a<R.sub.T/10.

[0074] The two groups of switch groups with opposite phases include a third switch group and a fourth switch group whose switching state is opposite to that of the third switch group. That is, the high level of a differential pulse outputted by these two switch groups is V.sub.H?V.sub.L, and the low level is V.sub.L?V.sub.H. The amplitudes of high and low levels are symmetrical. The third switch group is controlled by a control signal PG, and the fourth switch group is controlled by a control signal PG. The pulse signal is generated through these two switch groups, and its structure is simple and easy to be implemented.

[0075] An input terminal of the comparator is connected to a first switch group, a second switch group, and a sampling capacitor C.sub.S. The first switch group is connected to an output terminal of the single-pole point real number filter, and the second switch group is connected to the pulse generation unit. The first switch group inputs the differential signal V.sub.out outputted by the single-pole point real number filter into the comparator for comparison according to the calibration working time sequence, obtains a comparison result of the positive and negative terminals of the comparator, and thus obtains a zero-crossing relationship based on the comparison result. I.sub.n this embodiment, the first switch group is controlled by a control signal PHI1 outputted by the control logic module in FIG. 1, and the second switch group is controlled by a control signal PHI2 outputted by the control logic module in FIG. 1. When the differential signal V.sub.out outputted by the single-pole point real number filter is sampled, the first switch group is turned on, and the voltage on the sampling capacitor C.sub.S is the differential signal V.sub.out outputted by the single-pole point real number filter. When the first switch group is turned off, sampling is completed, and the sampling capacitor C.sub.S maintains the input of the comparator to the voltage before the switch is turned off. During reset, the second switch group is turned on, the voltage on the sampling capacitor C.sub.S is set to the DC signal V.sub.L and the DC signal V.sub.H outputted by the pulse generation unit, and the comparator completes the reset.

[0076] It can be seen from FIG. 2 that the calibration working time sequence of this embodiment mainly includes the control signal PG and the control signals PHI1 and PHI2. Herein, the control signal PHI1 leads the control signal PG by one reference clock period, the control signal PHI2 lags behind the control signal PG by three reference clock periods, and the high levels of the control signals PG, PHI1, and PHI2 are equal to two reference clock periods.

[0077] During the calibration process, when the control signal PHI1 is high level, the signal inputted by the comparator is the differential signal V.sub.out outputted by the operational amplifier. Further, the differential signal V.sub.out charges the sampling capacitor C.sub.S. When V.sub.out>0, the comparator outputs high level, otherwise it outputs low level. When the control signal PHI1 is low level, the connection between the comparator and the operational amplifier is disconnected. At this time, the input of the comparator is the voltage V.sub.S=V.sub.out held on the sampling capacitor C.sub.S before the disconnection. If V.sub.S>0, the output of the comparator is still high level. Therefore, the purpose of the arrangement of the sampling capacitor C.sub.S is to more accurately sample the differential signal V.sub.out after one reference clock period without being limited by the speed of the comparator in this embodiment.

[0078] As shown in FIG. 2, when the control signal PHI1 is high level, the comparator samples the differential signal V.sub.out. One clock period after the rising edge of the control signal PHI1 arrives, the rising edge of the control signal PG arrives, and the differential signal V.sub.out begins to rise. One clock period after the rising edge of the control signal PG arrives, the control signal PHI1 becomes low level, and the sampling of the output of the single-pole point real number filter is completed. The voltage on the sampling capacitor C.sub.S remains the output voltage of the single-pole point real number filter at this moment. As shown in FIG. 3, if the voltage V.sub.S of the sampling capacitor C.sub.S>0, it means that the zero-crossing time of the differential signal V.sub.out is ahead of the reference clock period. The zero-crossing time is advanced, indicating that the RC configuration value of the RC array is excessively small, and the RC value shall be increased. If V.sub.S<0, it means that the zero-crossing time of the differential signal V.sub.out lags behind the reference clock period. The zero-crossing lag indicates that the RC configuration value of the RC array is excessively large, and the RC value shall be reduced. Two clock periods after the rising edge of the control signal PG, the control signal PG becomes low level, and the differential signal V.sub.out outputted by the single-pole point real number filter begins to decrease and eventually returns to the lowest voltage. One clock period after the falling edge of the control signal PG arrives, the high level of the control signal PHI2 remains high for two clock periods and then changes to the low level after the rising edge arrives. The voltages on the two sampling capacitors C.sub.S of the comparator are set to V.sub.L and V.sub.H, and the comparator is reset.

[0079] I.sub.n order to ensure that the output of the single-pole point real number filter returns to the lowest voltage before the next comparison, the calibration working time sequence is repeated with 16 reference clock periods in this embodiment.

[0080] After obtaining the relationship between the zero-crossing point and the reference clock period, the calibration circuit calibrates the RC array based on this relationship. To be specific, the control logic module uses the successive approximation algorithm to scan the RC array based on each comparison result to complete the calibration.

[0081] Preferably, a compensation unit is arranged according to an operational amplifier delay td of the operational amplifier in the single-pole point real number filter, so that the comparator is delayed by the operational amplifier delay td and then samples the output voltage of the single-pole point real number filter, so that the calibration accuracy is effectively improved.

[0082] To be specific, the compensation unit is an inverter chain. The inverter chain is formed by a plurality of inverters connected in series.

[0083] Due to the limited bandwidth of the operational amplifier, a delay occurs as the signal passes through the operational amplifier. The following analyzes the impact of the operational amplifier delay td on calibration to illustrate the feasibility of using an inverter chain to compensate for the delay.

[0084] I.sub.n the calibration circuit of the active RC filter, let R.sub.p=R.sub.T=R and C.sub.p=C, and the analytical formula A.sub.0/(1+s/?.sub.0) is used to model the operational amplifier, where A.sub.0 is the low-frequency gain, and co is the main pole. A transfer function of the single-pole point real number filter after considering the bandwidth of the operational amplifier is:

[00010]$H\left(s\right)=\frac{-A_0{?}_0}{{\mathrm{RCs}}^2+\left(\mathrm{RC}{?}_0+A_0{?}_0\mathrm{RC}+2\right)s+\left(A_0+2\right){?}_0}.$

[0085] Assuming that the two poles of the transfer function H(s) are far apart, ?.sub.p1<<?.sub.p2, then:

[00011]${?}_{p1}?\frac{1}{\mathrm{RC}},$${?}_{p2}?\left(A_0+2\right){?}_0?A_0{?}_0.$

[0086] The pole ?.sub.p2 introduced by the operational amplifier may delay the output waveform of the single-pole point real number filter. This will make the calibrated single-pole point real number filter have a larger bandwidth. As ?.sub.p2 increases, the impact becomes smaller.

[0087] Normalizing the time unit to the ideal filter time constant ?, the step response of the filter using an ideal operational amplifier is:

[00012]$V_{\mathrm{ideal}}=1-2e^t.$

[0088] Assuming ?.sub.p2=K?.sub.p1, the step response of the filter using a non-ideal operational amplifier is:

[00013]$V_{\mathrm{non}-\mathrm{ideal}}=\frac{2}{K-1}{e}^{-\mathrm{Kt}}-\frac{2K}{K-1}{e}^{-t}+1,$

where K is the operation factor.

[0089] FIG. 4 shows the transient waveform graph when K=14 drawn through MATLAB.

[0090] FIG. 5 shows the error of K at some values calculated through MATLAB.

[0091] Herein, the error value is:

[00014]$\mathrm{Error}=\frac{t@\left(V_{\mathrm{non}-\mathrm{ideal}}=0\right)-t@\left(V_{\mathrm{ideal}}=0\right)}{t@\left(V_{\mathrm{ideal}}=0\right)}?100\%.$

[0092] Then the delay of the non-ideal zero-crossing point relative to the ideal zero-crossing point is:

[00015]$?t=t@\left(V_{\mathrm{non}-\mathrm{ideal}}=0\right)-t@\left(V_{\mathrm{ideal}}=0\right).$

[0093] The above times are normalized to the time constant r of an ideal single-pole point real number filter, but operational amplifier delays at various bandwidths cannot be directly compared. Therefore, we try to convert it to a general time scale, as shown in the following formula:

[00016]$?t=\mathrm{??}t=\frac{1}{{?}_{p1}}?t=\frac{K}{{?}_{p2}}?t=K?t\left(\frac{1}{{?}_{p2}}\right).$

[0094] If ?.sub.p2 is set to 2??600 MHz, the operational amplifier delays at different K are shown in FIG. 6.

[0095] The above analysis shows that when K is small, the error caused by the operational amplifier delay td is considerably large. However, FIG. 6 shows that the actual delays at different K are not much different, so it can be cancelled by a fixed delay. As shown in FIG. 1, the control signal PHI1 is delayed using the inverter chain to compensate for the error caused by the operational amplifier delay td in the invention. The delayed signal of the control signal PHI1 is PHI1_D. After actual testing, this method shows favorable accuracy.

[0096] Regarding the successive approximation algorithm, it is explained through the schematic diagram shown in FIG. 7 in this embodiment. In FIG. 7, a capacitor array with 32 unit capacitors connected in parallel is taken as an example to show how to achieve successive approximation calibration of capacitance. The same principle applies to the successive approximation algorithm for more complex RC arrays.

[0097] FIG. 8 is a waveform diagram simulating the calibration circuit of FIG. 1. In FIG. 8, C at the bottom of the figure is the number of unit capacitors connected in parallel.

[0098] In a tuning method for an on-chip differential active RC filter, the calibration method is applied to tune the RC array according to the target bandwidth of the single-pole point real number filter, and this method is simple and effective.

[0099] The above are only preferred embodiments of the invention. It should be pointed out that for a person having ordinary skill in the art, some modifications and improvements may be made without departing from the structure of the invention, which will not affect the effect of the invention and the practicability of the patent.