PEAK AND VALLEY CURRENT MODE CONTROL USING DOUBLE COMPENSATION RAMP

Abstract

A method for controlling peak and valley of a controlled current in a switched mode power supply comprising a current mode control loop and being connected to an electrical power source. The method comprises providing an upper compensation ramp signal for controlling a peak of the controlled current, the upper compensation ramp signal being a sawtooth signal with a negative, falling, substantially linear slope (−S.sub.e,Upper), starting periodically in time. The method further comprising providing a lower compensation ramp signal for controlling a valley of the controlled current, the lower compensation ramp signal being a sawtooth signal with a positive, raising, substantially linear slope (S.sub.e,Lower), starting periodically in time. The method additionally comprising providing a reference voltage signal (V.sub.ref), to the control loop, and obtaining a signal indicative of the controlled current (I). Finally, the method comprises comparing alternatingly the signal indicative of the controlled current referenced to the reference voltage signal to the lower compensation ramp and the upper compensation ramp, respectively, to switch on or off the electrical power from the electrical power source into the control loop, and switching the electrical power with modulation at a fixed frequency (f.sub.s).

Claims

1. A method for controlling peak and valley of a controlled current in a switched mode power supply comprising a current mode control loop, a switch, and being connected to an electrical power source, the method comprising: providing an upper compensation ramp signal for controlling a peak of the controlled current, the upper compensation ramp signal being a sawtooth signal with a negative, falling, substantially linear slope, −S.sub.e,Upper, starting periodically in time, providing a lower compensation ramp signal for controlling a valley of the controlled current, the lower compensation ramp signal being a sawtooth signal with a positive, raising, substantially linear slope, S.sub.e,Lower starting periodically in time, providing a reference voltage signal, V.sub.ref, to the control loop, obtaining a signal indicative of the controlled current, I, comparing alternatingly the signal indicative of the controlled current referenced to the reference voltage signal to the lower compensation ramp and the upper compensation ramp, respectively, to switch on or off the switch into the control loop, and switching the electrical power with modulation at a fixed frequency, f.sub.s.

2-13. (canceled)

14. The method according to claim 1, wherein the upper compensation ramp signal and the lower compensation ramp signal are separated in voltage by a predetermined offset.

15. The method according to claim 1, wherein the lower compensation ramp is reset to a low state when the current signal has crossed the lower compensation ramp, and the upper compensation ramp is reset to a high state when the current signal has crossed the upper compensation ramp.

16. The method according to claim 1, wherein the upper compensation ramp signal and the lower compensation ramp signal are separated in time by a predetermined offset.

17. A method for controlling peak and valley of a controlled current in a switched mode power supply comprising a current mode control loop, a switch, a digital circuit, and being connected to an electrical power source, the method comprising: switching the electrical power with modulation at a fixed frequency, f.sub.s, providing a reference voltage signal, V.sub.ref, to the control loop, obtaining a signal indicative of the controlled current, I, sampling and converting digitally repeatedly the signal indicative of the controlled current after a switching operation, computing from the sampling of the signal indicative of the controlled current, referenced to the reference voltage signal, a predicted switching time for a next switching operation, wherein the predicted switching time is an intersection point with either: a virtual upper compensation ramp signal for controlling a peak of the controlled current, the virtual upper compensation ramp signal being a sawtooth signal with a negative, falling, substantially linear slope, −S.sub.e,Upper, starting periodically in time, or a virtual lower compensation ramp signal for controlling a valley of the controlled current, the virtual lower compensation ramp signal being a sawtooth signal with a positive, raising, substantially linear slope, S.sub.e,Lower, starting periodically in time, and at the predicted switching time, switching off or on, respectively, the switch.

18. The method according to claim 1, wherein the step of obtaining a signal indicative of the controlled current is performed by measuring the controlled current.

19. The method according to claim 1, wherein the step of obtaining a signal indicative of the controlled current is performed by obtaining a time-derivative of a voltage developed over a capacitor by the controlled current.

20. The method according to claim 1, wherein the switched mode power supply connected to the electrical power source is switched on/off with pulse width modulation, PWM.

21. The method according to claim 1, wherein the fixed switching frequency, f.sub.s, of the switched mode power supply is about 1 kHz to about 100 MHz.

22. The method according to claim 1, wherein the slope of the upper compensating ramp signal is substantially numerically equal to the slope of the lower compensating ramp signal, S.sub.e,Upper=S.sub.e,Lower.

23. The method according to claim 1, wherein the numerical value of the slope of the upper compensating ramp signal is different from the slope of the lower compensating ramp signal, S.sub.e,Upper+S.sub.e,Lower.

24. A method for voltage mode control in a voltage mode control loop, wherein the voltage mode control loop comprises a current mode control loop according to claim 1.

25. A method for voltage mode control in a voltage mode control loop, wherein the voltage mode control loop comprises a signal indicative of the controlled current obtained by time-derivative of the voltage developed over a capacitor by the controlled current according to claim 1.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0059] The control scheme according to the invention will now be described in more detail with regard to the accompanying figures. The figures show one way of implementing the present invention and is not to be construed as being limiting to other possible embodiments falling within the scope of the attached claim set.

[0060] FIG. 1a details a circuit diagram for asymmetrical current control,

[0061] FIG. 1b details the waveforms relevant to asymmetrical current control,

[0062] FIG. 1c details the voltage reference response in an asymmetrical current control,

[0063] FIG. 1d details the current response in an asymmetrical current control,

[0064] FIG. 2 details the waveforms relevant to symmetrical average current control,

[0065] FIG. 3 details an embodiment of the peak and valley current control scheme according to the invention,

[0066] FIG. 4 details an embodiment for the removal of parasitic crossings,

[0067] FIG. 5a details a second embodiment for the removal of parasitic crossing,

[0068] FIG. 5b details an embodiment for increased robustness in the system,

[0069] FIG. 6 details an embodiment of an analogue implementation of the control scheme,

[0070] FIG. 7 details an embodiment of a digital control circuit for the implementation of the control scheme,

[0071] FIG. 8 details a comparison of the control schemes in one embodiment completed by the inventors,

[0072] FIG. 9 details an electrically board according to one embodiment of the invention,

[0073] FIGS. 10 and 11 details experimental data for an embodiment of the invention and

[0074] FIG. 12 shows an embodiment of the inventions circuit associated to peak and valley current control,

[0075] FIGS. 13a and b shows an embodiment of the invention in relation to predictive control with and without reference numerals.

DETAILED DESCRIPTION OF AN EMBODIMENT

[0076] FIG. 3 details an embodiment of a peak and valley current control scheme as described by the invention employing two asymmetrical compensation ramps in a voltage vs time graph, where T defines the switching period. In FIG. 12 a circuit diagram in an embodiment of the invention is shown. FIG. 12 shows that two asymmetrical compensation ramps are used in the control scheme. Note that in FIG. 12 the inverse of the compensation is shown as compared to FIG. 3, however, these two solutions are numerically equivalent.

[0077] The control procedure for conventional symmetrical current control mode (average current control) is to compute the difference between the reference voltage, V.sub.ref, and the output current measurement, I, hereafter V.sub.error. The control scheme works by switching between the on and off position when the modulation signal and V.sub.error intersect. This allows for the control of the average value of the output current. Such a procedure is conventional within the field of electronic and has been utilized in numerous applications. This procedure restricts the achievable bandwidth frequency, since the bandwidth frequency is limited by the inductance charge slope S.sub.n, the inductance discharge slope S.sub.f, which shall be lower (in absolute vales) than the slope of the symmetrical sawtooth S.sub.e in absolute value.

[0078] As illustrated in FIG. 3, the stripped line 1 indicates a symmetrical sawtooth. Further, an upper asymmetrical compensation ramp 2 and a lower asymmetrical compensation ramp 3 are shown. The dotted line 4 shows the behaviour of the current under conductance control according to a symmetrical sawtooth, which can also be achieve by use of the upper 2 and lower 3 compensation ramps. The inventor has shown that average current control with symmetrical sawtooth control is a particular case of peak and valley current control, where both peak and valley current can be controlled, meaning that the dynamical response of the systems are the same, resulting in that two asymmetrical compensation ramps can be used as a single symmetrical sawtooth.

[0079] Replacing a symmetrical sawtooth by two asymmetrical compensation ramps will facilitate the possibility of increasing the loop gain by going from the dotted line 4 to the dotted line 5, thereby enabling a higher frequency bandwidth in the same control system. In conventional systems, one would either use parallel converters to increase the bandwidth, adding to the circuit complexity, or increase the switching frequency, resulting in additional power losses and lower conversion efficiency.

[0080] In the current embodiment the current will rebound on the compensation ramps as shown in FIG. 1. The upper (res. lower) compensation ramp, controls the peak (resp. valley) of the current.

[0081] The configuration in such an embodiment enables higher bandwidth and higher loop gain compared to the peak and average asymmetrical current control. As seen in FIG. 3 there might be parasitic crossing in the control scheme wherein it crosses a compensation ramp without requiring a switching. Such parasitic crossing can be removed by increasing the distances between the asymmetrical sawtooth control ramps, as seen in FIG. 4 where the upper and lower compensation ramps have been shifted in voltage. The dashed line 5 has in this embodiment no parasitic crossing and the same bandwidth characteristics.

[0082] Other methods for removing the parasitic crossing may be to reset the compensation ramps, when a crossing has been made, as seen in FIG. 5 a, where the compensation ramps are reset when a crossing has been made. In this embodiment we see that the dotted lines 2 and 3 are the lower and upper compensation ramps, which has been reset to, respectively, a higher value for the upper compensation 2, such that it becomes 6, and a lower value for the lower compensation ramp 3 such that it become 7. The resetting means that the compensation ramp, after a crossing, becomes a value, which is out of the reachable interval of the current behaviour 5, until a new cycle begin. E.g. for the lower compensation a crossing occurs in 8, after which a reset of the compensation occurs until a new period 9. In this period the compensation ramps are moved to a value in which a crossing between the current 5 cannot occur.

[0083] Parasitic crossings may in an embodiment mainly be addressed by a reset, as shown in FIG. 5a, but increasing the horizontal distances between the compensation ramps may be beneficial to avoid working at the very beginning or end of a compensation ramp, as seen in FIG. 5b. Such a design will improve the robustness of the system as parametric robustness is less of a concern when the crossings occur away from the very beginning or end of a compensation ramp.

[0084] FIG. 5b shows that shifting the compensation ramps in time, with respect to each other, allows for tailoring the compensation ramps so as to not operate the system very near the beginning or end of a ramp, thereby improving the robustness of the system.

[0085] In an embodiment of the invention, the control scheme is implemented using analogue component as detailed in FIG. 6, wherein the separate components of the analogue scheme are detailed.

[0086] In FIG. 6 the COMPARATOR1 21 and COMPARATOR2 22, requested to respectively compare the error signal to the lower and upper compensation ramps, will change the status of FLIP-FLOP 23 depending on whether the feedback signal has reached the lower 3 or upper 2 compensation ramps. FLIP-FLOP 23 controls in turns the chopper 24 to increase or decrease the current level. The SWITCH 1 25 and SWITCH 2 26 materialize the provision for injecting a stepwise perturbation allowing the open-loop gain to be measured. Such provision is not necessary for nominal control scheme operation.

[0087] In another embodiment, the peak and valley current control mode can be implemented in a digital current mode control architecture, see FIG. 7. In such an embodiment the control scheme is carried out using a digital current control circuit, the digital current mode control 10 consisting of a field programmable gate array 11, FPGA, a sample and hold circuit 12, S/H, and an Analogue to Digital converter 13, ADC. Note that the FPGA may be replaced by any other numeric circuit able to implement the requested digital operation (e.g. by an ASIC).

[0088] The FPGA 11 will trigger the S/H circuit 12 and the ADC 13 will convert the sample into a numerical value to be provided to the FPFA 11, on its request. By repeating such operation at a frequency sufficiently large with respect to the switching frequency of the SMPS, the FPGA can implement numerically the analogue peak and valley current control scheme presented above and control the power switch 15 accordingly.

[0089] A more powerful embodiment can however be achieved with this digital architecture. Due to the time-discrete behaviour of the closed-loop dynamics indeed, the deviation of the current from it steady-state waveform is constant in between two switching operations. On the other hand, the targeted steady-state waveform is foreseeable, that is computable by the FPGA, on the basis of the system model. Therefore, a single measurement of the current, performed after each switching operation, is enough to compute and acquire that constant deviation of the current with respect to its steady-state waveform. The current deviation then allows to compute and determine the next switching time in an early way, and to enforce that switching when the time comes. Note that in such system, the upper and lower compensation ramps are virtual. They materialize as slope parameters within the formula foreseeing the next switching time on the basis of the current measurements performed after each switching operation.

[0090] Corresponding waveforms are shown on FIGS. 13a and 13b. FIG. 13b corresponds to FIG. 13a including reference numerals. The switching operations controlling the current peak and valley are indicated respectively by the orange dot 42 and the violet dot 43. The measurements of the current occur after each switching operation and are indicated by a green dot 44. A slight delay 41 between switching and measurement allows for switching noise settling, preventing inaccurate measurement. In the present illustration, a ΔV.sub.ref step occurring before time t.sub.k is completely resorbed at the next switching operation due to the implemented control scheme.

[0091] The definite advantage of such scheme is that no continuous operation of a fast ADC is needed. At the contrary, a slower ADC is acceptable, consuming e.g. 10% of the switching period to convert the analogue current measurement into a digital information, leaving the remaining switching period time for the FPGA to compute the next switching time and to implement that switching operation. Such control scheme, referred to as predictive control, proves therefore to be very effective in terms of results achieved with limited additional electronic cost (low speed ADC to be added to the existing digital control FPGA).

[0092] In FIG. 8, the performance of the control system in an ideal embodiment is compared with the asymmetrical conductance mode and with the symmetrical average current mode control. It is seen that the bandwidth performance, F.sub.b/F.sub.s, of the symmetrical conductance control is a factor 2 better than the asymmetrical one. Further, the symmetrical conductance features a linear relation between average current and duty-cycle. In addition, bandwidth frequency and stability margin change much less with duty-cycle, that is with the output voltage, than for the asymmetrical conductance controls. All this is beneficial for large signal operation.

[0093] It must be noted that since the constraint of S.sub.f<S.sub.e for the asymmetrical average control case with falling sawtooth and S.sub.n<S.sub.e and S.sub.f<S.sub.e for the average symmetrical case does not apply to peak current control or peak and valley current control, such that peak (and valley) current control bandwidth surpasses that of the average current control.

[0094] Now referring to FIG. 9, a circuit validating the different control schemes is shown, the results of which will be discussed in connection with FIG. 10.

[0095] The validation is shown in FIGS. 10 and 11 detailing the open-loop gain and the associated phase and gain margin of the PVCC control scheme. Upper diagram in FIG. 10 indicates the Bode plot amplitude for different gain values. Lower plot of FIG. 10 stands for Bode plot phase and is unaffected by the loop gain. The diagram of FIG. 11 includes the relation between bandwidth on one side, and gain and phase margin on the other side, wherein the upper curve is the phase margin curve 31 and the lower curve is the gain margin curve 32. The continuous lines are relevant to theoretical figures, while measurements are indicated by dots, which are in good accordance with the theoretical forecast.

[0096] In FIG. 12 an embodiment shows a circuit of the compensation ramp. In this embodiment the inverse of the ramp is added to the current, depending on the input of the comparator that is chosen, such that signal is flipped in sign. The basic mechanisms of the invention remains the same, as the upper compensation ramp will then have a positive slope, while the lower compensation ramp has a negative slope. This will be the same control scheme was discussed in connection with FIG. 3.

[0097] The invention can be implemented by means of hardware, software, firmware or any combination of these. The invention or some of the features thereof can also be implemented as software running on one or more data processors and/or digital signal processors.

[0098] The individual elements of an embodiment of the invention may be physically, functionally and logically implemented in any suitable way such as in a single unit, in a plurality of units or as part of separate functional units. The invention may be implemented in a single unit or be both physically and functionally distributed between different units and processors.

[0099] Although the present invention has been described in connection with the specified embodiments, it should not be construed as being in any way limited to the presented examples. The scope of the present invention is to be interpreted in the light of the accompanying claim set. In the context of the claims, the terms “comprising” or “comprises” do not exclude other possible elements or steps. Also, the mentioning of references such as “a” or “an” etc. should not be construed as excluding a plurality. The use of reference signs in the claims with respect to elements indicated in the figures shall also not be construed as limiting the scope of the invention. Furthermore, individual features mentioned in different claims, may possibly be advantageously combined, and the mentioning of these features in different claims does not exclude that a combination of features is not possible and advantageous.

REFERENCE NUMERALS

[0100] 1 Symmetrical sawtooth [0101] 2 Upper asymmetrical sawtooth [0102] 3 Lower asymmetrical sawtooth [0103] 4 Current behaviour [0104] 5 Current behaviour [0105] 6 Reset upper compensation [0106] 7 Reset lower compensation ramp [0107] 8 Start of reset period [0108] 9 End of reset period [0109] 10 Digital current mode control [0110] 11 Field programmable gate array [0111] 12 Sample and hold circuit [0112] 13 Analogue to digital converter [0113] 15 Power switch [0114] 21 COMPARATOR1 [0115] 22 COMPARATOR2 [0116] 23 FLIP-FLOP [0117] 24 CHOPPER [0118] 25 SWITCH 1 [0119] 26 SWITCH 2 [0120] 31 Phase margin curve [0121] 32 Gain margin curve [0122] 41 Delay [0123] 42 Current peaks [0124] 43 Current valleys [0125] 44 Switching operations

REFERENCE TO LITERATURE

[0126] (Ridley, 1990) R. B. Ridley, “A New Small-Signal Model for Current-Mode Control”, Dissertation submitted for the degree of PhD, 27 Nov. 1990