TWO BIT MEMORY DEVICE AND METHOD FOR OPERATING THE TWO-BIT MEMORY DEVICE AND ELECTRONIC COMPONENT

Abstract

A two-bit memory device having a layer structure containing in order a bottom layer, a molecular layer containing a chiral compound having at least one polar functional group, and a top layer, which is electrically conductive and ferromagnetic. The chiral compound acts as a spin filter for electrons passing through the molecular layer. The chiral compound is of flexible conformation and has a conformation-flexible molecular dipole moment. An electrical resistance of the layer structure for an electrical current running from the bottom layer to the top layer has at least four distinct states which depend on the magnetization of the top layer and on the orientation of the conformation-flexible dipole moment of the chiral compound. Furthermore, a method for operating the two-bit memory device and an electronic component containing at least one two-bit memory device.

Claims

1. A two-bit memory device (1) having a layer structure (10), the layer structure (10) comprising in this order a bottom layer (A), a molecular layer (C) comprising a chiral compound having at least one polar functional group, and a top layer (E), wherein the top layer (E) is electrically conductive and ferro-magnetic, wherein the chiral compound acts as a spin filter for electrons passing through the molecular layer (C), the chiral compound being of flexible conformation and having a conformation-flexible molecular dipole moment, and wherein an electrical resistance of the layer structure (10) for an electrical current running from the bottom layer (A) to the top layer (E) has at least four distinct states which depend on the magnetization of the top layer (E) and on the orientation of the conformation-flexible dipole moment of the chiral compound of the molecular layer (C).

2. The two-bit memory device (1) of claim 1, characterized in that the chiral compound of the molecular layer (C) is bound to the bottom layer (A) or in that an anchoring layer (B) for bonding of the chiral compound of the molecular layer (C) is arranged between the bottom layer (A) and the molecular layer (C) and the chiral compound of the molecular layer (C) is bound to the anchoring layer (B).

3. The two-bit memory device (1) of claim 1, characterized in that an interlayer (D) is arranged between the molecular layer (C) and the top layer (E).

4. The two-bit memory device (1) of claim 2, characterized in that the material of the anchoring layer (B) and/or of the interlayer (D) is chosen from the group comprising Al.sub.2O.sub.3, ZrO.sub.2, HfO.sub.2, TiO.sub.2, SiO.sub.2, ITO, AZO, IGZO, ZnO, MgO and combinations thereof.

5. The two-bit memory device (1) of claim 1, characterized in that the material of the bottom layer (A) is chosen from the group comprising doped Si, and Al, W, Mo, Ru, Ag, Au, TiN, TaN and combinations thereof.

6. The two-bit memory device (1) of claim 1 characterized in that the material of the top layer (E) is chosen from the group comprising Ni, Co, Fe, NiFe, CoFeB, CoFe, GdFe, TbFeCo, GdFeCo and combinations thereof.

7. The two-bit memory device (1) of claim 1, characterized in that the molecular layer (C) is a self-assembled monolayer comprising the molecules of the chiral compound.

8. The two-bit memory device (1) of claim 1, characterized in that the quotient of a difference between the electrical resistances of the two states of the molecular layer (C) and a difference between the two states of the top layer (E) is in the range of from 10 to 10000.

9. The two-bit memory device (1) of claim 1, characterized in that the chiral compound is selected from the group of compounds of the formulae
R.sup.1-(A.sup.1-Z.sup.1).sub.r—B.sup.1—(Z.sup.2-A.sup.2).sub.s-Sp.sup.A-G  (IA)
D.sup.1-Z.sup.D-(A.sup.1-Z.sup.1).sub.r—B.sup.1—(Z.sup.2-A.sup.2).sub.s-Sp-G  (IB)
R.sup.1C-(A.sup.1-Z.sup.1).sub.r—B.sup.1—Z.sup.L-A.sup.2C-(Z.sup.3-A.sup.3).sub.s-G  (IC) in which R.sup.1 denotes straight chain or branched racemic or branched non-racemic alkyl or alkoxy, each having up to 20 C atoms, where one or more CH.sub.2 groups in these radicals may each be replaced, independently of one another, by —C≡C—, —CH═CH—, ##STR00057## —O—, —S—, —CF.sub.2O—, —OCF.sub.2—, —CO—O—, —O—CO—,—SiR.sup.0R.sup.00—, —NH—, —NR.sup.0— or —SO.sub.2— in such a way that O atoms are not linked directly to one another, and in which one or more H atoms may be replaced by halogen, CN, SCN or SF.sub.5, R.sup.1C denotes straight chain or branched racemic or branched non-racemic alkyl or alkoxy each having up to 20 C atoms, where one or more CH.sub.2 groups in these radicals may each be replaced, independently of one another, by —C≡C—, —CH═CH—, ##STR00058## —O—, —S—, —CF.sub.2O—, —OCF.sub.2—, —CO—O—, —O—CO—,—SiR.sup.0R.sup.00—, —NH—, —NR.sup.0— or —SO.sub.2— in such a way that O atoms are not linked directly to one another, and in which one or more H atoms may be replaced by halogen, CN, SCN or SF.sub.5, and alternatively denotes a group D.sup.1-Z.sup.D, Z.sup.D has one of the meanings of Z.sup.1, Z.sup.2 and Z.sup.3 or denotes a spacer group, Z.sup.1, Z.sup.2, Z.sup.3 on each occurrence, identically or differently, denote a single bond, —CF.sub.2O—, —OCF.sub.2—, —CF.sub.2S—, —SCF.sub.2—, —CH.sub.2O—, —OCH.sub.2—, —C(O)O—, —OC(O)—, —C(O)S—, —SC(O)—, —(CH.sub.2).sub.n1—, —(CF.sub.2).sub.n2—, —CF.sub.2—CH.sub.2—, —CH.sub.2—CF.sub.2—, —CH═CH—, —CF═CF—, —CF═CH—, —CH═CF—, —(CH.sub.2).sub.n3O—, —O(CH.sub.2).sub.n4—, —C≡C—, —O—, —S—, —CH═N—, —N═CH—, —N═N—, —N═N(O)—, —N(O)═N— or —N═C—C═N—, n1, n2, n3, n4 identically or differently, are 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10, Z.sup.L denotes —O—, —S—, —CH.sub.2—, —C(O)—, —CF—, —CHF—, —C(R.sup.x).sub.2—, —S(O)— or —SO.sub.2—, where a group —CHF— or an asymmetrically substituted group —C(R.sup.x).sub.2— can be racemic or non-racemic, R.sup.0, R.sup.00, identically or differently, denote an alkyl or alkoxy radical having 1 to 15 C atoms, in which, in addition, one or more H atoms may be replaced by halogen, R.sup.x on each occurrence, identically or differently, denotes H or straight-chain or branched alkyl having 1 to 6 C atoms, D.sup.1 denotes a diamondoid radical, preferably derived from a lower diamondoid, very preferably selected from the group consisting of adamantyl, diamantyl, and triamantyl, in which one or more H atoms can be replaced by F, in each case optionally fluorinated alkyl, alkenyl or alkoxy having up to 12 C atoms, in particular ##STR00059## A.sup.1, A.sup.2, A.sup.3 on each occurrence, identically or differently, denote an aromatic, heteroaromatic, alicyclic or heteroaliphatic ring having 4 to 25 ring atoms, which may also contain condensed rings and which may be mono- or polysubstituted by Y, A.sup.2C denotes an aromatic or heteroaromatic ring having 5 to 25 ring atoms, which may also contain condensed rings and which may be mono- or polysubstituted by Y.sup.C, Y on each occurrence, identically or differently, denotes F, Cl, CN, SCN, SF.sub.5 or straight-chain or branched, in each case optionally fluorinated alkyl, alkoxy, alkylcarbonyl, alkoxycarbonyl, alkylcarbonyloxy or alkoxycarbonyloxy having 1 to 12 C atoms, preferably F or Cl, Y.sup.C on each occurrence, identically or differently, denotes F, Cl, CN, SCN, SF.sub.5 or straight-chain or branched, in each case optionally fluorinated alkyl, alkoxy, alkylcarbonyl, alkoxycarbonyl, alkylcarbonyloxy or alkoxycarbonyloxy having 1 to 12 C atoms, or cycloalkyl or alkylcycloalkyl each having 3 to 12 C atoms, preferably methyl, ethyl, isopropyl, cylopropyl, cyclobutyl, cyclopentyl, cyclohexyl, trifluoromethyl, methoxy or trifluoromethoxy, B.sup.1 denotes ##STR00060## ##STR00061## where the groups may be oriented in both directions, L.sup.1 to L.sup.3, independently of one another, denote F, Cl, Br, I, CN, SF.sub.5, CF.sub.3 or OCF.sub.3, preferably CF.sub.3, Cl or F, where L.sup.3 may alternatively also denote H, Sp.sup.A denotes a spacer group or a single bond, Sp denotes a chiral spacer group, G denotes —OH, —CH(CH.sub.2OH).sub.2, —C(CH.sub.2OH).sub.3, —SH, —SO.sub.2OH, —OP(O)(OH).sub.2, —PO(OH).sub.2, —C(OH)(PO(OH).sub.2).sub.2, —COOH, —Si(OR.sup.x).sub.3 or —SiCl.sub.3, —SO.sub.2OR.sup.V, —OP(O)(OR.sup.V).sub.2, —PO(OR.sup.V).sub.2, —C(OH)(PO(OR.sup.V).sub.2).sub.2, —COOR.sup.V or —Si(OR.sup.V).sub.3, R.sup.V denotes secondary or tertiary alkyl having 1 to 20 C atoms, and r, s on each occurrence, identically or differently, are 0, 1 or 2, where at least one of R.sup.1 and Sp.sup.A of formula IA is chiral, and at least one of R.sup.1C and Z.sup.L of formula IC is chiral, and wherein B.sup.1 is polar.

10. The two-bit memory device (1) of claim 1, characterized in that the bottom layer (A) is configured as a bottom electrode (14) or is connected to a bottom electrode (14) and the top layer (E) is connected to a top electrode (12) and for switching of the molecular layer (C) into a first state of electrical resistance or a second state of electrical resistance, a first or second switching voltage is applied between the bottom layer (A) and the top layer (E), and for switching of the top layer (E) into a first state of electrical resistance or a second state of electrical resistance, a third or fourth switching voltage is applied between the bottom layer (A) and the top layer (E), wherein the absolute values of the third and fourth switching voltages are at least two times larger than the absolute values of the first switching voltage and the second switching voltage.

11. The two-bit memory device (1) of claim 1, characterized in that the bottom layer (A) is configured as a bottom electrode (14) or is contacted by a bottom electrode (14) and the bottom electrode (14) is contacted by a first electrical contact (16) and additionally by a second electrical contact (18) and forms an electrical conductor (20) being arranged parallel to the top layer (E) and the first electrical contact (16) and the second electrical contact (18) are arranged such that an electrical current flows through the electrical conductor (20) when a voltage is applied between the first electrical contact (16) and the second electrical contact (18).

12. A method for operating the two-bit memory device (1) of claim 1, characterized in that for switching of the molecular layer (C) into a first state of electrical resistance the bottom layer (A) is set to a first electrical potential and the top layer (E) is set to a second electrical potential, where the absolute value of the voltage between the bottom layer (A) and the top layer (E) is greater than a first switching voltage and the first potential is greater than the second potential, and for switching of the molecular layer (C) into a second state of electrical resistance the bottom layer (A) is set to a third electrical potential and the top layer (E) is set to a fourth electrical potential, where the absolute value of the voltage between the bottom layer (A) and the top layer (E) is greater than a second switching voltage and the fourth potential is greater than the third potential.

13. The method for operating the two-bit memory device (1) according to claim 12, characterized in that the state of the two-bit memory device (1) is determined by applying a reading voltage whose absolute value is smaller than the first and second switching voltages between the bottom layer (A) and the top layer (E) and measuring the resulting electrical current.

14. The method for operating the two-bit memory device (1) according to claim 12, characterized in that for a two-bit memory device (1) for switching of the top layer (E) into a first state of electrical resistance the bottom layer (A) is set to a fifth electrical potential and the top layer (E) is set to a sixth electrical potential, where the absolute value of the voltage between the bottom layer (A) and the top layer (E) is greater than a third switching voltage and the fifth potential is greater than the sixth potential, and for switching of the top layer (E) into a second state of electrical resistance the bottom layer (A) is set to a seventh electrical potential and the top layer (E) is set to an eighth electrical potential, where the absolute value of the voltage between the bottom layer (A) and the top layer (E) is greater than a fourth switching voltage and the eighth potential is greater than the seventh potential, and wherein the absolute values of the third switching voltage and the fourth switching voltage are larger than the absolute values of the first switching voltage and the second switching voltage so that the state of the top layer (E) and the molecular layer (C) are switched simultaneously to the respective first or second state of resistance and, if the molecular layer (C) is to be switched to a different state, an additional step of switching of the molecular layer (C) is performed after switching of the top layer (E).

15. The method for operating the two-bit memory device (1) according to claim 12, characterized in that for a device (1) for switching of the top layer (E) into a first state of electrical resistance a first switching current is supplied to the electrical conductor being arranged parallel to the top layer (E) by applying a ninth potential to the first electrical contact and a tenth electrical potential to the second electrical contact, the first electrical potential being greater than the second electrical potential, and for switching of the top layer (E) into a second state of electrical resistance a second switching current is supplied to the electrical conductor being arranged parallel to the top layer (E) by applying an eleventh potential to the first electrical contact and a twelfth electrical potential to the second electrical contact, the twelfth electrical potential being greater than the eleventh electrical potential.

16. An electronic component comprising at least one two-bit memory device (1) according to claim 1.

17. The electronic component of claim 16, characterized in that the electronic component comprises a crossbar array having word lines (32) and bit lines (34) and a plurality of two-bit memory devices (1), wherein the word lines (32) are electrically connected to the bottom electrodes (14) of the two-bit memory devices (1) and the bit lines (34) are connected to the top electrodes (12) of the two-bit memory devices (1).

18. The electronic component of claim 17, wherein a selector device (30) is assigned to each one of the plurality of two-bit memory devices (1).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0224] The drawings show:

[0225] FIGS. 1a to 1d show different embodiments of the layer structure,

[0226] FIG. 2 shows a first embodiment of the two-bit memory device, and

[0227] FIG. 3 shows a second embodiment of the two-bit memory device.

[0228] FIGS. 1a to 1d show four different embodiments of a layer structure 10 of the two-bit memory device 1, see FIGS. 2 and 3.

[0229] The first embodiment of FIG. 1a shows a layer structure 10 consisting of in this order a bottom layer (A), a molecular layer (C) and a top layer (E). The respective layers are in direct contact with each other.

[0230] The molecular layer (C) comprises a chiral compound having at least a conformation-flexible molecular dipole moment. Due to the chiral structure, the chiral compound may act as a spin filter for electrons passing through the molecular layer (C). Due to the chiral compound being of flexible conformation, the polar functional group of the molecules of the chiral compound may change its orientation when an electric field is applied. The electrical resistance for a current flowing from the bottom layer (A) through the molecular layer (C) into the top layer (E) is dependent on the orientation of the polar group. Thus, the state of the molecular layer (C) may be changed by applying an electric field.

[0231] The molecular layer (C) also serves as spin injector and provides a spin polarized current. Depending on the magnetization of the top layer (E), a spin polarized current flowing from the molecular layer (C) into the top layer (E) exhibits a low or high resistance.

[0232] The top layer (E) is electrically conductive and ferromagnetic. The top layer (E) may be magnetized. Depending on the orientation of the magnetization, the state of the top layer (E) may be changed.

[0233] The bottom layer (A) of the first embodiment is preferably an electrically conductive material and also serves as a substrate for the chiral compound of the molecular layer (C). For example, a bottom layer made of electrically conductive TiN may be used.

[0234] In the second embodiment of FIG. 1b, the layer structure 10 consists of in this order a bottom layer (A), a molecular layer (C), an interlayer (D) and a top layer (E). The respective layers are in direct contact with each other.

[0235] The additional interlayer (D) may be used in order to adjust the electrical properties of the layer structure and/or for protection of the molecular layer (C). For example, depending on the electrical properties of the molecular layer (C) an interlayer (D) in the form of an additional electrically insulating layer may be required in order to reduce leakage currents through the layer structure 10. The electrically insulating layer is, for example, an Al.sub.2O.sub.3 layer.

[0236] In the third embodiment of FIG. 1c, the layer structure 10 consists of in this order a bottom layer (A), an anchoring layer (B), a molecular layer (C) and a top layer (E). The respective layers are in direct contact with each other.

[0237] The anchoring layer (B) serves as substrate for the molecular layer (C) and is not required to be electrically conductive. The anchoring layer (B) may be required for bonding of the molecular layer (C). For example, a thin layer of Al.sub.2O.sub.3 may be used as anchoring layer (B). The thin anchoring layer allows electrons from the bottom layer (A) to tunnel into the molecular layer (C) so that a tunnel current may flow. In preferred embodiments, the molecular layer (C) is bonded directly to the bottom layer (A) without the means of an additional anchoring layer (B).

[0238] In the fourth embodiment of FIG. 1d, the layer structure 10 consists of in this order a bottom layer (A), an anchoring layer (B), a molecular layer (C), an interlayer (D) and a top layer (E). The respective layers are in direct contact with each other.

[0239] FIG. 2 schematically shows a first embodiment of a two-bit memory device 1 comprising a layer structure 10 embedded between a bottom electrode 14 and a top electrode 12.

[0240] The layer structure 10 is configured as described with respect to FIG. 1a and comprises in this order a bottom layer (A), a molecular layer (C) and a top layer (E). Alternatively, layer structures 10 according to the further embodiments of FIGS. 1b to 1d may be used.

[0241] The bottom electrode 14 is in direct contact with the bottom layer (A) and has an electrical contact 15 which is connected to a selector device 20 which is, for example, configured as a transistor.

[0242] The two-bit memory device 1 as shown in FIG. 2 may be embedded in an electronic component comprising a crossbar array. The top electrode 12 serves as bit line 34 of the crossbar array. Further, the selector device 30 is connected to a word line 32 of the crossbar array. By means of the selector device 30, the electrical contact 15 may be connected to a source line 36 depending on a signal on the word line 32.

[0243] For reading of the state of the two-bit memory device 1, an electrical current flows according to a read path 40 from the source line 36 through the selector device 30, the electrical contact 15 and the bottom electrode 14 to the layer structure 10. The electrical current flows through the bottom layer (A), the molecular layer (C) and through the top layer (E) and finally into the top electrode 12 or bit line 34.

[0244] The electrical resistance of the layer structure 10 for the electrical current running from the bottom layer (A) to the top layer (E) has at least four distinct states which depend on the magnetization of the top layer (E) and on the orientation of the conformation-flexible dipole moment of the chiral compound of the molecular layer (C). Thus, four distinct current levels may be detected which correspond to the four states of the two-bit memory device 1.

[0245] For setting of the state of the molecular layer (C), a voltage is applied along a dielectric write path 42 which is identical to the read path 40. Accordingly, a respective switching voltage is applied by means of the top electrode 12 or bit line 34 and the source line 36.

[0246] For setting of the state of the top layer (E), a spin polarized current is applied by supplying an electrical current along a magnetic write path 44 which is in the first embodiment identical to the read path 40. Accordingly, current flows from the source line 36 through the selector device 30, the electrical contact 15 and the bottom electrode 14 to the layer structure 10.

[0247] The electrical current flows through the bottom layer (A), the molecular layer (C) and through the top layer (E) and finally into the top electrode 12 or bit line 34. The current is spin polarized by means of the molecular layer (C).

[0248] FIG. 3 schematically shows a second embodiment of a two-bit memory device 1 comprising a layer structure 10 embedded between a bottom electrode 14 and a top electrode 12.

[0249] The layer structure 10 is configured as described with respect to FIG. 1a and comprises in this order a bottom layer (A), a molecular layer (C) and a top layer (E). Alternatively, layer structures 10 according to the further embodiments of FIGS. 1b to 1d may be used.

[0250] The bottom electrode 14 is in direct contact with the bottom layer (A) and has a first electrical contact 16 which is connected to a selector device 20 which is, for example, configured as a transistor.

[0251] As described with respect to the two-bit memory device 1 of FIG. 2, the two-bit memory device 1 may be embedded in an electronic component comprising a crossbar array. The top electrode 12 serves as bit line 34 of the crossbar array. Further, the selector device 30 is connected to a word line 32 of the crossbar array. By means of the selector device 30, the electrical contact 15 may be connected to a source line 36 depending on a signal on the word line 32.

[0252] For reading of the state of the two-bit memory device 1, an electrical current flows according to a read path 40 as described with respect to the first embodiment of FIG. 2.

[0253] Also, the setting of the state of the molecular layer (C), is performed as described with respect to the first embodiment of FIG. 2 by applying a voltage along a dielectric write path 42 which is identical to the read path 40.

[0254] For setting of the state of the top layer (E), an external magnetic field is generated. For this, a part of the bottom electrode 14 is used as an electrical conductor 20 and an electric current is applied to this electrical conductor 20. For application of the current, the bottom electrode 14 comprises a second electrical contact 18 in addition to the first electrical contact 16.

[0255] By applying a voltage difference between the first electrical contact 16 and the second electrical contact 18, a current is generated along a magnetic write path 44 which in turn generates the magnetic field used for switching of the top layer (E).

LIST OF REFERENCE NUMERALS

[0256] A bottom layer [0257] B anchoring layer [0258] C molecular layer [0259] D interlayer [0260] E top layer [0261] 1 two bit memory device [0262] 10 layer structure [0263] 12 top electrode [0264] 14 bottom electrode [0265] 16 first electrical contact [0266] 18 second electrical contact [0267] 20 electrical conductor [0268] 30 selector device [0269] 32 word line [0270] 34 bit line [0271] 36 source line [0272] 40 read path [0273] 42 write path dielectric state [0274] 44 write path magnetic state