METHOD AND CIRCUIT FOR SIMPLE MEASUREMENT OF THE PHASE SHIFT BETWEEN TWO DIGITAL CLOCK SIGNALS HAVING THE SAME FREQUENCY

Abstract

A method for simple measurement of phase shift between a first clock signal and a second clock signal is described, each clock signal having a period T.sub.0. The method includes: feeding the first clock signal into a first input of a mixer; feeding the second clock signal into a second input of the mixer; feeding the output signal of the mixer into a low pass filter; and measuring the output signal of the low pass filter, with the aid of an output voltage that is normalized to operating voltage of the mixer. A circuit for implementing the method includes a mixer and a low pass filter. The mixer includes a first input for feeding in the first clock signal, and a second input for feeding in the second clock signal. The output of the mixer is connected to the input of the low pass filter.

Claims

1-14. (canceled)

15. A method for measuring a phase shift between a first clock signal and a second clock signal, the first clock signal and the second clock signal having the same frequency, the method comprising the following steps: a-1) feeding the first clock signal into a first input of a mixer; a-2) feeding the second clock signal into a second input of the mixer ; d) feeding an output signal of the mixer into a low pass filter; and e) measuring the output signal of the low pass filter.

16. The method as recited in claim 15, wherein the mixer includes an XOR gate, and step d) includes feeding an output signal of the XOR gate into an input of the low pass filter.

17. The method as recited in claim 16, wherein step a-1) includes feeding the first clock signal into a first input of the XOR gate, step a-2) includes feeding the second clock signal into a second input of the XOR gate, and the method further includes the following step: f) normalizing the output signal of the low pass filter to a period duration of the first and second clock signals and an operating voltage of the mixer, the output signal of the low pass filter being multiplied by one-half the period duration and divided by the operating voltage of the mixer.

18. The method as recited in claim 16, wherein the mixer includes a first edge-controlled flip-flop, a second edge-controlled flip-flop, and an AND gate, step a-1) includes feeding the first clock signal into a dynamic input of the first flip-flop; step a-2) includes feeding the second clock signal into a dynamic input of the second flip-flop; and the method further comprises the following steps: b-1) feeding an output signal of the first flip-flop into a first input of the XOR gate and into a first input of the AND gate; b-2) feeding an output signal of the second flip-flop into a second input of the XOR gate and into a second input of the AND gate; c-1) relaying an output signal of the AND gate to a reset input of the first flip-flop; and c-2) relaying the output signal of the AND gate to a reset input of the second flip-flop.

19. The method as recited in claim 18, wherein the mixer also includes an OR gate and an inverter, step c-1) includes feeding the output signal of the AND gate into a first input of the OR gate and feeding an output signal of the OR gate into the reset input of the first flip-flop; step c-2) includes feeding the output signal of the AND gate into the first input of the OR gate and feeding the output signal of the OR gate into the reset input of the second flip-flop; and wherein the method further includes the following steps: feeding a constant activation signal into a data input of the first flip-flop, a data input of the second flip-flop, and an input of the inverter; feeding an output signal of the inverter into a second input of the OR gate.

20. The method as recited claim 19, further comprising the following step: f′) normalizing the output signal of the low pass filter to the period duration of the first and second clock signals and the operating voltage of the mixer.

21. The method as recited in claim 20, wherein in step f) either: (i) the output voltage of the low pass filter being multiplied by the period duration and divided by the operating voltage of the mixer when the output voltage of the low pass filter is less than one-half the operating voltage of the mixer, or (ii) a difference between the operating voltage of the mixer and the output voltage of the low pass filter being multiplied by the period duration and divided by the operating voltage of the mixer when the output voltage of the low pass filter is greater than one-half the operating voltage of the mixer or is equal to one-half the operating voltage of the mixer.

22. A circuit for measuring the phase shift between a first clock signal and a second clock signal, comprising: a mixer; and a low pass filter; wherein the mixer includes a first input configured to feed in the first clock signal and a second input configured to feed in the second clock signal, and an output of the mixer is connected to the input of the low pass filter.

23. The circuit as recited in claim 22, wherein the mixer includes an XOR gate, and an output of the XOR gate is connected to the input of the low pass filter.

24. The circuit as recited in claim 23, wherein the first input of the mixer is a first input of the XOR gate, and the second input of the mixer is a second input of the XOR gate.

25. The circuit as recited in claim 23, wherein the mixer further includes a first edge-controlled flip-flop, a second edge-controlled flip-flop, and an AND gate, the first input of the mixer is a dynamic input of the first flip-flop, the second input of the mixer is a dynamic input of the second flip-flop, an output of the first flip-flop is connected to a first input of the XOR gate and to a first input of the AND gate, the output of the second flip-flop is connected to a second input of the XOR gate and to a second input of the AND gate, the mixer includes a connection between an output of the AND gate and a reset input of the first flip-flop, and the mixer includes a connection between the output of the AND gate and a reset input of the second flip-flop.

26. The circuit as recited in claim 25, wherein the mixer further includes an OR gate and an inverter, the connection between the output of the AND gate and the reset input of the first flip-flop and to the reset input of the second flip-flop extends via the OR gate, the output of the AND gate is connected to a first input of the OR gate, and an output of the OR gate is connected to the reset input of the first flip-flop and to the reset input of the second flip-flop, the mixer includes a third input, the third input of the mixer being connected to a data input of the first flip-flop, to a data input of the second flip-flop, and to an input of the inverter, and an output of the inverter is connected to a second input of the OR gate.

27. The circuit as recited in claim 22, wherein the circuit is an integrated circuit.

28. The circuit as recited in claim 22, wherein the low pass filter is a passive low pass filter and includes a resistor and a capacitor.

29. The circuit as recited in claim 23, wherein the XOR gate is a highly symmetrical XOR gate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Exemplary embodiments of the present invention are explained in greater detail based on the figures and the following description.

[0051] FIG. 1 shows an illustration of two digital clock signals having different duty cycles (related art).

[0052] FIG. 2 shows an example of two clock signals CLK.sub.1 and CLK.sub.2 having same period duration T.sub.0, and which are phase-shifted by time offset ΔT (related art).

[0053] FIG. 3 shows an illustration of the principle of measuring the phase shift between two clock signals having the same frequency.

[0054] FIG. 4 shows a normalized transfer function of the measuring system according to FIGS. 3 and 5.

[0055] FIG. 5 shows a specific example embodiment of the circuit according to the present invention for measuring the phase shift between two digital clock signals having the same frequency.

[0056] FIG. 6 shows for two clock signals, at least one of which has a duty cycle different from ½, the mixed product and the filtered result when the measuring system according to FIG. 3 is used.

[0057] FIG. 7 shows, for the same incoming clock signals as in FIG. 6(a), the mixed product and the filtered result when the measuring system according to FIG. 9 is used.

[0058] FIG. 8 shows a normalized transfer function of the measuring system illustrated in FIG. 9.

[0059] FIG. 9 shows a circuitry embodiment (measuring system) for implementing the measuring method from FIG. 7.

[0060] FIG. 10 shows a temporal pattern of the signals within the circuit from FIG. 9, and of the signals at the dynamic inputs and the reset inputs of the flip-flops in the circuit from FIG. 9.

[0061] FIG. 11 shows a circuitry-based implementation of the symmetrical XOR gate/mixer.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0062] FIG. 1 is used to explain several terms used below. The term “signal” is understood here to mean a measured variable (amplitude), in particular a voltage V, that is a function of time t. A signal is “digital” when the amplitude can assume only two values. These values are typically referred to as “logical 0” and “logical 1.” FIG. 1 shows signals that are expressed as a function V(t), i.e., as voltage V as a function of time t. The illustrated signals are “digital” due to the fact that voltage V in each case assumes only two values, namely, V.sub.0 and V.sub.1. V.sub.0 (typically V.sub.0=0; i.e., no voltage is present) corresponds to “logical 0,” and V.sub.1 (typically a voltage greater than V.sub.0) corresponds to “logical 1.”

[0063] FIG. 1, (a) and (b) each show a “periodic” signal, since the shape of the signal temporally repeats with period duration T.sub.0; i.e., V(t)=V(t+T.sub.0) applies for all t. However, the “duty cycles” of the illustrated signals, i.e., the ratios of the pulse duration (duration of logical 1)—denoted in the figure by reference symbol τ—to period duration T.sub.0, are different. In FIG. 1 (a) the duty cycle is ½, since pulse duration τ is precisely one-half of period duration T.sub.0, or in other words, because duration τ of logical 1 corresponds exactly to duration τ′ of logical 0. In contrast, in FIG. 1 (b) the duty cycle is greater than ½, since pulse duration τ is greater than one-half of period duration T.sub.0, or in other words, because duration τ of logical 1 exceeds duration τ′ of logical 0.

[0064] Only digital signals are considered in the following discussion. To maintain clarity in the figures, in the subsequent illustrations of the digital signals the coordinate axes and their descriptions are omitted; it is clear that in each case they may be supplemented, as illustrated in FIG. 1.

[0065] FIG. 2 schematically shows an example of two digital periodic clock signals CLK.sub.1 and CKL.sub.2 (situated one on top of the other) that have same period duration T.sub.0, and that are shifted relative to one another by a time offset ΔT, or in other words, have a phase shift ΔT.

[0066] It is noted that it is generally sufficient to ascertain absolute time offset |ΔT|, since typically only the phase shift between the signals is important, not for which of signals CLK.sub.1 and CLK.sub.2 the start of a period occurs “earlier.” Since the signals are periodic, establishing specific start t.sub.0 and end t.sub.0+ΔT of a period is arbitrary anyway, and only the time difference between the start and the end must correspond to period duration T.sub.0. For the same reason, it ultimately makes no difference whether a time offset is expressed as |ΔT| or |T.sub.0−ΔT|; it is usually expressed here as min{|ΔT|, |T.sub.0−ΔT|}.

[0067] The method provided here in accordance with the present invention is also used for mixing two clock signals having the same frequency. The method is schematically illustrated in FIG. 3. Signals CLK.sub.1 and CLK.sub.2 shown in FIG. 3 (a) correspond to those described above with reference to FIG. 2. Clock signals CLK.sub.1 and CLK.sub.2 in particular have the same frequency (period duration T.sub.0), and in addition each have the duty cycle ½ (cf. FIG. 1 (a)). Their phase shift ΔT, highlighted by the crosshatched areas, is unknown and is to be determined with the aid of the measuring system schematically illustrated in FIG. 3 (b). For this purpose, initially signals CLK.sub.1 and CLK.sub.2 are mixed together; i.e., first signal CLK.sub.1 is fed into a first input 201a of a mixer 200a, and signal CLK.sub.2 is fed into the second input of mixer 200a.

[0068] Since the duty cycles of both signals is ½, a signal s having twice the frequency of signals CLK.sub.1 and CLK.sub.2 is obtained at the mixer output, i.e., at node y. This is schematically illustrated in FIG. 3 (c), with the pulses, i.e., the times at which the signal supplies a logical 1, once again being highlighted with crosshatched areas. The resulting duty cycle of signal s at the output of mixer 200a is a function of the phase shift between signals CLK.sub.1 and CLK.sub.2. With the aid of low pass filtering, the high-frequency signal components may be suppressed, and direct component 2.Math.|ΔT|/T.sub.0, normalized to the full signal swing (i.e., signal voltage V.sub.1 corresponding to logical 1 (cf. FIG. 1)), remains. The direct component of periodic signal s is the constant term in the progression of signal s into a Fourier series. The constant term corresponds precisely to the surface area of function s(t) over a full period T.sub.0, and is normalized to this period T.sub.0; it may therefore be taken directly from FIG. 3 (c).

[0069] Consequently, output signal y of mixer 200a is initially fed into a low pass filter 300 (cf. FIG. 3 (b)), whose essentially constant (see above) output voltage V.sub.out at the output (out) of low pass filter 300 then represents the measured variable for determining ΔT (cf. FIG. 3 (d)). In particular, only a voltmeter is needed for measuring the signal swing at the output of the low pass filter, i.e., output voltage V.sub.out.

[0070] The relationship between the signal swing at the output of low pass filter 300 and the (one-half) duty cycle of signal s at the output of mixer 200a are shown in FIG. 4, the output voltage at low pass filter 300 being illustrated here normalized to the full signal swing, i.e., operating voltage V.sub.DD of mixer 200a. In particular, FIG. 4 shows that the transfer function of the measuring system according to FIG. 3 (b) is piecewise-linear. When signals CLK.sub.1 and CLK.sub.2 to be compared have a time offset ΔT that corresponds exactly to one-half of period duration T.sub.0, the signal swing at the low pass output is at a maximum.

[0071] Thus, for measuring (absolute) time offset |ΔT|, it is necessary only to measure direct voltage V.sub.out at the low pass output, using a standard voltmeter or multimeter. The time offset between the two signals may then be ascertained by computation from measured and known variables. In particular, it is apparent from FIG. 3 (d) and the (piecewise) linearity of the transfer function from FIG. 4 that duty cycle 2.Math.|ΔT|/T.sub.0 of signal s at the output of mixer 200a corresponds precisely to output voltage V.sub.out at low pass filter 300 normalized to operating voltage V.sub.DD of mixer 200a.

[0072] The absolute value of time offset |ΔT| may thus be expressed by

[00001]$\begin{array}{cc}.Math.\mathrm{\Delta T}.Math.=T_0.Math.\frac{V_{\mathrm{out}}}{2V_{DD}},& \left(1\right)\end{array}$

where T.sub.0 is the period duration, V.sub.DD is the operating voltage of the mixer, and V.sub.out is the direct voltage at the output of the low pass filter.

[0073] An XOR gate is the simplest way to implement such a mixer 200a. This gate supplies a logical 1 at the output when the signals at the inputs are different, exactly as illustrated in FIGS. 3 (a) and (c). The measuring system shown in FIG. 3 (b) may be implemented, for example, using a design as illustrated in FIG. 5. Each of clock signals CLK.sub.1 and CLK.sub.2 to be compared is respectively fed into one of the two inputs 201a and 202a of an XOR gate 210, whose output (node y) is then used as the output of the mixer and is connected to the input of a passive low pass filter 300.

[0074] Low pass filter 300 may be easily implemented, for example, by the combination of resistor R and capacitor C shown in FIG. 5. One terminal 301 of resistor R is used as the input of low pass filter 300, and the other terminal of resistor R is used as the output (out) of the low pass filter, which, however, at the same time is connected to ground via capacitor C.

[0075] However, in this simple implementation of a mixer with the aid of an XOR gate, it should be noted that the duty cycles of signals CLK.sub.1 and CLK.sub.2 to be compared influence the result. In other words, the arrangements and results described in conjunction with FIGS. 3 through 5 may generally be used only when signals CLK.sub.1 and CLK.sub.2 reliably have the duty cycle ½. In the general case, in which not only time offset ΔT but also the duty cycles of signals CLK.sub.1 and CLK.sub.2 are unknown, the measuring system must be appropriately modified.

[0076] The phenomenon of the influence of the duty cycles of signals CLK.sub.1 and CLK.sub.2 to be compared on the transfer function when the measuring system according to FIG. 3 (b) or FIG. 5 is used is illustrated in FIGS. 6 (a) through (c). As is apparent from FIG. 6 (a), time offset ΔT is unchanged compared to the situation from FIG. 3. However, although second clock signal CLK.sub.2 in FIG. 6 (a) likewise remains unchanged in comparison to the second clock signal from FIG. 3 (a) and thus still has a duty cycle of ½, the duty cycle of signal CLK.sub.1 in FIG. 6 (a) is reduced in comparison to that in FIG. 3 (a), since the ratio of the duration of the signal pulse (logical 1) in a period T.sub.0 of signal CLK.sub.1 to period T.sub.0 is now smaller. Times t in which either only signal CLK.sub.1 supplies a pulse or only signal CLK.sub.2 supplies a pulse are highlighted in crosshatch in FIG. 6 (a) for clarification. Thus, mixing signals CLK.sub.1 and CLK.sub.2 with the aid of an XOR gate, as described in the context of FIGS. 3 through 5, supplies a logical 1 at the output of the mixer specifically at the points in time denoted by the crosshatched highlighting in FIG. 6 (a), which is likewise illustrated by crosshatched highlighting in FIG. 6 (b).

[0077] With the aid of low pass filters, as described above the duty cycle of the signal illustrated in FIG. 6 (b) may now be measured at the output of the mixer (XOR gate). However, the width of the crosshatched highlighting for each period in FIG. 6 (a) and (b) now directly indicates that the duration of logical 1 for each period at the output of the XOR gate, denoted as |ΔT′| in the figure, is greater than twice time offset |ΔT|. Thus, for constant signal swing V.sub.out/V.sub.DD, normalized to operating voltage V.sub.DD of the mixer, at the output of low pass filter, V.sub.out/V.sub.DD=|ΔT′|/T.sub.0>2.Math.|ΔT|/T.sub.0 applies, as illustrated in FIG. 6 (c). Formula (1), developed for measuring and ascertaining absolute time offset |ΔT| (see above) for the simple case of a duty cycle of ½ for both signals, based on FIGS. 3 through 5, is thus no longer usable in this way in the case of arbitrary duty cycles, since, without knowledge of the greatly differing different duty cycles, an absolute time offset of |ΔT′| that does not match actual value |ΔT| would be ascertained as the result.

[0078] For an accurate measurement of the time offset between CLK.sub.1 and CLK.sub.2 that is independent of the duty cycle, the method must be modified as illustrated in FIGS. 7 (a) through (c). The crosshatched areas in FIG. 7 (a) denote for each period the time period between the points in time of occurrence of the respective rising edge of signals at CLK.sub.1 and CLK.sub.2. The rising edges of the signals remain disregarded. By use of a suitable mixer circuit, the times denoted in crosshatch in FIG. 7 (a) are subsequently filtered out; in other words, the mixer at its output supplies a logical 1 for the duration between the points in time of the rising edges of signals CLK.sub.1 and CLK.sub.2, and otherwise supplies a logical 0. This is illustrated in FIG. 7 (b). It is apparent from the figure that for each period, a logical 1 is then supplied at the output of the mixer for the exact duration of absolute time offset |ΔT|. The constant component of the signal from FIG. 7 (b) may then be ascertained once again, as described above, using a low pass filter downstream from the mixer; (constant) output voltage V.sub.out/V.sub.DD of the constant component of the signal, normalized to operating voltage V.sub.DD of the mixer, then corresponds precisely to absolute time offset |ΔT| of signals CLK.sub.1 and CLK.sub.2 normalized to period duration T.sub.0; i.e., V.sub.out/V.sub.DD=|ΔT|/T.sub.0 (cf. FIG. 7 (c)).

[0079] The transfer function of such a circuit is illustrated in FIG. 8 (a) for time offsets in range |ΔT|/T.sub.0≤½. As described above, the constant component at the filter output, normalized to the signal swing, is now |ΔT|/T.sub.0. The steepness of the transfer function is therefore only half as great as in the method according to FIG. 3, since a doubling of the frequency at the mixer output no longer takes place.

[0080] FIG. 8 (b) expands the region of FIG. 8 (a); in range |ΔT|/T.sub.0≤½ and V.sub.out/V.sub.DD≤½, the relationship from FIG. 8 (b) matches the transfer function from FIG. 8 (a) (section C.sub.0 of the shown relationship, illustrated as a solid line). However, depending on the particular point in time at which the measurement of signals CLK.sub.1 and CLK.sub.2 in FIG. 7 (a) is started, time offsets T.sub.0 with T.sub.0≥|ΔT|>T.sub.0/2 may also occur. Such time offsets result in normalized signal swings V.sub.out/V.sub.DD at the filter output with V.sub.out/V.sub.DD>½, or equivalently, V.sub.out>V.sub.DD/2. This corresponds to section C.sub.1, denoted by a dashed line, of the relationship illustrated in FIG. 8 (b). However, as noted above, for measured time offsets |ΔT| with T.sub.0≥|ΔT|>T.sub.0/2, generally not |ΔT|, but instead preferably |T.sub.0−ΔT|, would be stated, since |T.sub.0−ΔT|≤T.sub.0/2 then once again applies. This is equivalent to folding over (mirroring) section C.sub.1 in FIG. 8 (b) at the vertical through point |ΔT|/T.sub.0=½ (section C.sub.2 of the relationship).

[0081] The modification of the method described in FIGS. 7 (a) through (c) and 8 (a) and (b), previously described with reference to FIGS. 3 through 5, thus results in a different computation of the absolute time offset, which, as may be determined from FIG. 8, may be ascertained as follows:

[00002]$\begin{array}{cc}.Math.\Delta T.Math.=\frac{T_0}{V_{DD}}.Math.\{\begin{array}{cc}{V}_{\mathrm{out}}& \mathrm{for}{V}_{\mathrm{out}}\le V_{DD}/2\\ V_{DD}-V_{\mathrm{out}}& \mathrm{for}{V}_{\mathrm{out}}>V_{DD}/2\end{array},& \left(2\right)\end{array}$

where once again T.sub.0 is the period duration, V.sub.DD is the operating voltage of the mixer, and V.sub.out is the direct voltage at the output of the low pass filter.

[0082] Of course, the modified method described above for determining the absolute time offset of two digital clock signals having the same frequency also requires a different mixer than the XOR gate used in the simple method according to FIGS. 3 through 5.

[0083] For implementing the circuitry-based method illustrated in FIGS. 7 (a) through (c), this means that the rising clock edge of the leading signal opens the signal path, and thus a logical 1 is present at an input of the mixer until a rising edge of the second signal blocks the signal path, and in each case a logical 0 is once again present at both inputs of the mixer.

[0084] The circuit illustrated in FIG. 9 implements the method illustrated in FIGS. 7 (a) through (c). The circuit includes a mixer 200 and a low pass filter 300. The two signals CLK.sub.1 and CLK.sub.2 serve dynamic inputs (clock inputs) 201 and 202, respectively, of flip-flops FF1 or FF2, as denoted in each case by circuitry symbol “”. Outputs Q of the flip-flops are connected to an input of an XOR gate 210 via node x.sub.1 or x.sub.2, respectively, and also to an input of an AND gate 220.

[0085] When the circuit is active, i.e., en=1 (where “en” stands for “enable”), the outputs of flip-flops FF1 and FF1 at the respective rising edges of CLK.sub.1 or CLK.sub.2 accept the piece of data from respective data inputs D of the flip-flops at outputs Q. The outputs are set, i.e., are logical 1's.

[0086] Flip-flops FF1 and FF2 are reset in each case with the aid of a combinational circuit made up of AND gate 220, an OR gate 230, and an inverter 240. This takes place either as soon as both flip-flops are set, or if en=0. As a result of this design, various logical signal values are present at the inputs of XOR gate 210 only for the exact duration of time offset |ΔT| between CLK.sub.1 and CLK.sub.2. This is totally independent of the duty cycles of signals CLK.sub.1 and CLK.sub.2.

[0087] The mixing of the signals on nodes x.sub.1 and x.sub.2 is carried out using XOR gate 210. The mixed product at output 204 of XOR gate 210 (i.e., the signal at node y) is filtered using a passive low pass filter 300 made up of a resistor R and a capacitor C (also see the description for FIG. 5). As a result, the high-frequency signal components are suppressed, and essentially only the constant component of the mixed product is provided at the output (out) of the circuit.

[0088] FIG. 10 illustrates by way of example the temporal pattern of the signals at the nodes of the circuit in FIG. 9, and at the dynamic inputs and the reset inputs of the flip-flops in this circuit. At the very top, illustrated once again are the two input clock signals CLK.sub.1 and CLK.sub.2 having the same frequency, with period T.sub.0 and phase shift ΔT, based on the example described in FIGS. 2 and 3 (a). The signals underneath, denoted by reference symbols x.sub.1 and x.sub.2, correspond to the voltage patterns at nodes x.sub.1 and x.sub.2 in FIG. 9, and arise when en=1 is set at this circuit (i.e., a logical 1 is set at inverter 240 and at the data inputs of flip-flops FF1 and FF2), and signals CLK.sub.1 and CLK.sub.2 are fed into the dynamic inputs (clock inputs) of flip-flops FF1 or FF2. Due to en=1, OR gate 230 simply relays the signal present at node z.sub.1 to its output, and thus to the reset inputs of flip-flops FF1, FF2 via node z.

[0089] At the start of the measurement, signal CLK.sub.2 initially supplies a rising edge, so that output Q of second flip-flop FF2 switches, i.e., a logical 1 is set there, which is then present at the first input of XOR gate 210 and likewise at the first input of AND gate 220 (node x.sub.2). However, signal CLK.sub.1 is still at a logical 0, so that the Q output of first flip-flop FF1 still supplies a 0. The XOR gate thus switches; i.e., at its output 204 and thus at node y a 1 is supplied (lowest signal in the figure), which is then passed on to low pass filter 300. However, the AND gate at its output remains at a 0, as the result of which, via node z, a 0 is also present at reset inputs RST of both flip-flops (signal denoted by reference symbol RST in the figure). The duration of the above-described state is denoted in the figure by the left crosshatched highlight.

[0090] As soon as first clock signal CLK.sub.1 also supplies a 1, i.e., beginning with the first rising edge of CLK.sub.1, a 1 is also set at the Q output of first flip-flop FF1, and the 1 is then present, via node x.sub.1, at the second input of XOR gate 210 and at the same time at the second input of AND gate 220. Thus, at that moment a logical 1 is set on both nodes x.sub.1 and x.sub.2 (the circuit is in this state for only a very short time, characterized here by the duration of the first pulse of signal x.sub.1 (see below)). At its output 204, XOR gate 210 thus switches a 0, which is then transferred to the low pass filter via node y, and at its output AND gate 220 switches a 1, which is then relayed to the reset inputs of the two flip-flops via OR gate 230 and nodes z.sub.1 and z. As a result, at their respective Q outputs both flip-flops now switch a 0, which (via nodes x.sub.1 and x.sub.2) is then present at both inputs of XOR gate 210 and of AND gate 220, so that XOR gate 210 as well as AND gate 220 switch to 0 at their respective output. Thus, the signal at node y is set to 0 and passed on to low pass filter 300. The reset inputs of the flip-flops are likewise set to 0 via nodes z.sub.1, z and OR gate 230. Thus, in summary, nodes x.sub.1, x.sub.2, y and the reset inputs of the flip-flops are set to 0 (state prior to the second crosshatched strip in the figure, viewed starting from the left).

[0091] This state does not change, even if signals CLK.sub.1 and CLK.sub.2 drop back to 0, since this does not affect the state of the Q outputs of the flip-flops. Nodes x.sub.1, x.sub.2, y and the reset inputs of the flip-flops thus continue to remain at 0 (states of the circuit over the duration of the second crosshatched strip, viewed starting from the left, to the start of the third crosshatched strip in the figure). This corresponds to the original state. The above-described procedure now repeats upon reaching the second rising edge of second signal CLK.sub.2.

[0092] As is apparent in the figure from the signal at node y, for each period T.sub.0 this node is set to 1 for the exact duration of phase shift ΔT. The signal of node y is then fed into the low pass filter, which, as described above, then filters out the constant component of the signal, which may then be measured with a voltmeter, and after appropriate normalization (see above) corresponds precisely to value |ΔT|/T.sub.0, which via equation (2) described above may be immediately converted into absolute time offset |ΔT| of incoming clock signals CLK.sub.1 and CLK.sub.2.

[0093] When the above-described circuit is used, for each period small pulse widths result for the signals at node z (i.e., at reset inputs RST of the flip-flops) and x.sub.1, as well as a temporal overhang of the signal pulse at node x.sub.2 beyond the end of the signal pulse at node y. These small pulse widths as well as the stated temporal overhang of the signal pulse at node x.sub.2 are determined by the signal propagation time through the chain made up of the AND gate and the OR gate. In particular, the pulse width is approximately equal to the sum of all delays in the signal path, from inputs RST of the flip-flops to the output of the OR gate. However, the overlappings of x.sub.1 and x.sub.2 determined by the propagation time have no effect due to the behavior of the XOR gate, in which a logical 1 appears at its output only when its two inputs are different (i.e., when a logical 0 is present at one input of the XOR gate, and at the same time a logical 1 is present at the other input of the XOR gate). The accuracy is affected mainly by manufacturing- or design-related differences in the propagation times due to the flip-flops (clock to output delay) and propagation time differences between the two XOR inputs. This is the reason for the symmetrical design in the arrangement of the flip-flops. Also for this reason, a symmetrical design of the internal structure of the XOR gate is advantageous (see the discussion for FIG. 11 below).

[0094] As described above, with regard to the temporal sequences of the signal processing, a highly symmetrical XOR gate is advantageous for implementation of the circuit shown above using circuitry techniques. FIG. 11 illustrates one example of a circuit design of such a highly symmetrical XOR gate. Reference symbols VDD and VSS denote the positive and negative power supply connections, respectively. In addition, nine PMOS transistors are denoted by reference symbols M.sub.P0, M.sub.P1, . . . , M.sub.P8, and likewise nine NMOS transistors are denoted by reference symbols M.sub.N0, M.sub.N1, . . . , M.sub.N8. BF1 and BF2 are signal drivers, each with an inverting output (indicated by a circle) and a non-inverting output. Apart from the inverter at the output (implemented by transistors M.sub.P8 and M.sub.N8), each branch exists in duplicate in the structure of the circuit. The only difference between the branches is that the order of the transistors controlled by a certain signal has been reversed in the respective branch. The logical function thus remains unchanged. However, identical (i.e., symmetrical) signal propagation times for both XOR inputs are thus achieved. The prerequisite here is that the propagation times from the signal driver inputs to the inverting output and to the non-inverting output of the driver are the same; i.e., the inverted and the non-inverted variant of the signal are provided at the same time. A further prerequisite is that there are no differences in propagation times between the two signal drivers.

[0095] If the circuit shown in FIG. 11 is used as an XOR gate 220 in the circuit of mixer 200 in FIG. 9, the signal of nodes x.sub.1 and x.sub.2 of mixer 200 is supplied to the inputs of signal drivers BF1 and BF2, respectively. The output signal of the highly symmetrical XOR gate (i.e., the output of the inverter implemented by transistors M.sub.P8 and M.sub.N8 (see above)) is then fed into node y.