Diamond-Capped Gallium Oxide Transistor

Abstract

A method for growing nanocrystalline diamond (NCD) on Ga.sub.2O.sub.3 to provide thermal management in Ga.sub.2O.sub.3-based devices. A protective SiN.sub.x interlayer is deposited on the Ga.sub.2O.sub.3 before growth of the NCD layer to protect the Ga.sub.2O.sub.3 from damage caused during growth of the NCD layer. The presence of the NCD provides thermal management and enables improved performance of the Ga.sub.2O.sub.3-based device.

Claims

1. A method for forming a Ga.sub.2O.sub.3-based electronic device having enhanced thermal management properties, comprising: forming a Ga.sub.2O.sub.3-based buffer layer on a substrate; forming a Ga.sub.2O.sub.3-based barrier layer on the Ga.sub.2O.sub.3-based buffer layer; depositing a SiN.sub.x interlayer on the Ga.sub.2O.sub.3-based barrier layer; and forming a nanocrystalline diamond (NCD) layer on the Ga.sub.2O.sub.3 barrier layer; wherein the SiN.sub.x interlayer protects the Ga.sub.2O.sub.3 barrier layer from damage during formation of the NCD layer; and wherein the NCD layer provides thermal management to the device.

2. The method according to claim 1, wherein the NCD layer is grown on the barrier layer capped Ga.sub.2O.sub.3 semiconductor.

3. The method according to claim 2, wherein the NCD layer is grown by microwave plasma enhanced chemical vapor deposition (MW-CVD) or hot filament CVD (HF-CVD).

4. The method according to claim 1, wherein the Ga.sub.2O.sub.3 is ?-Ga.sub.2O.sub.3.

5. The method according to claim 1, wherein the buffer layer comprises unintentionally doped ?-Ga.sub.2O.sub.3 and the barrier layer comprises ?-(Al.sub.xGa.sub.1-x).sub.2O.sub.3.

6. The method according to claim 1, further comprising doping the Ga.sub.2O.sub.3 buffer layer with a hydrogenic donor species.

7. The method according to claim 6, wherein the hydrogenic donor species comprises silicon (Si), germanium (Ge), or tin (Sn).

8. The method according to claim 1, further comprising forming source, gate, and drain electrodes to form a heterostructure field-effect transistor (HFET).

9. An Ga.sub.2O.sub.3-based electronic device having enhanced thermal management properties, comprising: a Ga.sub.2O.sub.3-based buffer layer formed on a substrate; a Ga.sub.2O.sub.3-based barrier layer formed on the Ga.sub.2O.sub.3-based buffer layer; a SiN.sub.x interlayer deposited on the Ga.sub.2O.sub.3-based barrier layer; and a nanocrystalline diamond (NCD) layer formed on the Ga.sub.2O.sub.3 barrier layer wherein the SiN.sub.x interlayer protects the Ga.sub.2O.sub.3 barrier layer from damage during growth of the NCD layer; and wherein the NCD layer provides thermal management to the device.

10. The device according to claim 9, wherein the Ga.sub.2O.sub.3 is ?-Ga.sub.2O.sub.3.

11. The device according to claim 9, wherein the buffer layer comprises unintentionally doped ?-Ga.sub.2O.sub.3 and the barrier layer comprises ?-(Al.sub.xGa.sub.1-x).sub.2O.sub.3.

12. The device according to claim 9, further comprising doping the Ga.sub.2O.sub.3 buffer layer with a hydrogenic donor species.

13. The device according to claim 9, wherein the hydrogenic donor species comprises silicon (Si), germanium (Ge), or tin (Sn).

14. The device according to claim 9, wherein the device is a heterostructure field-effect transistor (HFET), a field effect transistor (FET), a metal-oxide-semiconductor field effect transistor (MOSFET), a modulation-doped field effect transistor (MODFET), a current aperture vertical electron transistor (CAVET), a FinFET, or a hot electron transistor (HET).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 is a block schematic illustrating an exemplary Ga.sub.2O.sub.3-based electronic device incorporating an NCD heat-spreading layer in accordance with the present invention.

[0020] FIGS. 2A-2F are a ?-series of atomic force microscope (AFM) images showing NCD films grown on Ga.sub.2O.sub.3 at 400? C. and 500? C. with three different SiN.sub.x barrier dielectric layers.

[0021] FIGS. 3A and 3B are SEM images illustrating how a barrier dielectric layer in accordance with the present invention protects an NCD-coated Ga.sub.2O.sub.3 crystal during an H.sub.2 plasma etch.

[0022] FIG. 4 is a plot showing Raman spectra confirming growth of NCD on Ga.sub.2O.sub.3 having the various SiN.sub.x barrier dielectrics shown in FIGS. 2D-2F.

[0023] FIG. 5 is a plot showing Raman spectra confirming growth of NCD on Ga.sub.2O.sub.3 with a protective interlayer up to a temperature of 650? C.

[0024] FIGS. 6A and 6B are plots showing DC transfer curves for ?-Ga.sub.2O.sub.3 devices without (FIG. 6A) and with (FIG. 6B) NCD/SiN.sub.x layers in accordance with the present invention.

[0025] FIGS. 7A and 7B are plots showing DC output curves for ?-Ga.sub.2O.sub.3 devices without (FIG. 7A) and with (FIG. 7B) NCD/SiN.sub.x layers in accordance with the present invention.

[0026] FIG. 8 is a plot illustrating the average temperature rise as a function of power density for HFET devices with and without NCD/SiN.sub.x layers in accordance with the present invention.

DETAILED DESCRIPTION

[0027] The aspects and features of the present invention summarized above can be embodied in various forms. The following description shows, by way of illustration, combinations and configurations in which the aspects and features can be put into practice. It is understood that the described aspects, features, and/or embodiments are merely examples, and that one skilled in the art may utilize other aspects, features, and/or embodiments or make structural and functional modifications without departing from the scope of the present disclosure.

[0028] For example, although the present invention will be described below in the context of an exemplary Ga.sub.2O.sub.3-based heterostructure grown via ozone-assisted molecular beam epitaxy (O.sub.3-MBE), one skilled in the art will readily recognize that heterostructures having other configurations or grown by other means can also benefit from thermal management provided by incorporation of an NCD layer with protective interlayer disposed between the NCD and the Ga.sub.2O.sub.3, and all such alternative heterostructures are deemed to be within the scope of the present disclosure.

[0029] As described above, the low thermal conductivity of ?-Ga.sub.2O.sub.3 is a significant concern for maximizing the potential of this ultra-wide bandgap semiconductor technology, but previous attempts to incorporate NCD into Ga.sub.2O.sub.3-based devices have not been successful.

[0030] The present invention overcomes the problems of incorporating NCD into such Ga.sub.2O.sub.3-based devices. In accordance with the present invention, a protective interlayer is deposited onto the Ga.sub.2O.sub.3 layer before growth of the NCD layer to protect the Ga.sub.2O.sub.3 from damage caused during growth of the NCD layer. In this way, the present invention enables the formation of devices that incorporate NCD as a top-side, device-level thermal management solution on a lateral ?-Ga.sub.2O.sub.3 transistor.

[0031] In many embodiments, the protective interlayer will be in the form of a dielectric layer such as a SiN.sub.x layer deposited on an upper surface of the Ga.sub.2O.sub.3 barrier layer in the device. The presence of the protective dielectric interlayer prevents etch damage to the Ga.sub.2O.sub.3 surface caused by hydrogen plasma during diamond CVD growth and enables the formation of a high-quality continuous NCD layer which can provide effective thermal management and thereby reduce self-heating in the device.

[0032] Thus, as described in more detail below, in accordance with the present invention, an NCD heat-spreading layer is grown via microwave plasma enhanced chemical vapor deposition on a Ga.sub.2O.sub.3 layer in a Ga.sub.2O.sub.3-based heterostructure, where a protective dielectric interlayer such as a SiN.sub.x layer is deposited on the Ga.sub.2O.sub.3 layer prior to growth of the NCD layer to protect the surface of the Ga.sub.2O.sub.3 from damage caused by the diamond deposition conditions.

[0033] In many embodiments, the Ga.sub.2O.sub.3-based structure is a ?-(Al.sub.xGa.sub.1-x).sub.2O.sub.3/?-Ga.sub.2O.sub.3 heterostructure, with the NCD being deposited prior to the gate formation, though other embodiments in which the NCD layer is deposited after the Ni/Au gate contact or, conversely, the Ni/Au gate is deposited onto an existing NCD layer, are also possible.

[0034] The incorporation of the NCD heat-spreading layer enables the formation of a ?-(Al.sub.xGa.sub.1-x).sub.2O.sub.3/?-Ga.sub.2O.sub.3 heterostructure field-effect transistor (HFET) showing a decrease in total thermal resistance at the gate by >40%.

[0035] FIG. 1 illustrates an exemplary embodiment of a ?-(Al.sub.xGa.sub.1-x).sub.2O.sub.3/Ga.sub.2O.sub.3 heterostructure field-effect transistor (HFET) incorporating a nanocrystalline diamond (NCD) heat-spreading layer and SiN.sub.x protective interlayer in accordance with the present invention. As noted above, in the embodiment illustrated in FIG. 1, the NCD layer was etched prior to deposition of the Ni/Au gate contact, but other embodiments in which the NCD layer is deposited after the Ni/Au gate contact or, conversely, the Ni/Au gate is deposited onto an existing NCD layer, are also possible.

[0036] As illustrated in FIG. 1, such an exemplary device can comprise a 125 nm-thick unintentionally doped (UID) Ga.sub.2O.sub.3 buffer layer 102 grown on an Fe-doped (010) Ga.sub.2O.sub.3 substrate 101, with a 28 nm-thick (Al.sub.xGa0.sub.1-x).sub.2O.sub.3 barrier layer 103 disposed on the Ga.sub.2O.sub.3 layer, where the AlGaO layer 103 is delta-doped with Si approximately 3 nm above its interface with Ga.sub.2O.sub.3 layer 102 (i.e., approximately 25 nm from the top of the layer in the case shown in the FIGURE). Si ions are implanted and annealed in an N.sub.2 atmosphere for 30 min at 925? C. to form n+ areas 104a/104b for the source and drain, respectively, with Ti/Au being deposited by e-beam evaporation on each of the n+ areas and annealed in an N.sub.2 atmosphere for approximately one minute at 470? C. to form Ohmic source/drain contacts 105a/105b. The specific contact resistivity, mobility, sheet carrier concentration, and sheet resistance of this structure at room temperature were measured as follows:

TABLE-US-00001 contact resistivity 4.3 ? 10.sup.?4 ? ? cm.sup.2 mobility 54 cm.sup.2/V .Math. s sheet carrier concentration 1.26 ? 10.sup.13 cm.sup.?2 sheet resistance 9.1 k?/square

[0037] In accordance with the present invention, a SiN.sub.x layer 106 having an exemplary thickness of about 50 nm was then deposited by plasma-enhanced chemical vapor deposition (PECVD) at 400? C. The presence of the SiN.sub.x layer protects the Ga.sub.2O.sub.3 layer from damage caused by the H.sub.2 plasma required for growth of NCD layer 107.

[0038] NCD layer 107 was then grown on the Ga.sub.2O.sub.3 layer as protected by the SiN.sub.x layer. The NCD layer can be grown by any suitable process, but typically will be grown via microwave plasma enhanced chemical vapor deposition (MW-CVD). To start the NCD growth process, nucleation sites for the growth of NCD layer 107 were facilitated via a seeding method using detonation nanodiamond powder. In an exemplary case, the growth chamber was pre-treated with 200 sccm of H.sub.2 at a temperature of 100? C. and a pressure of 15 torr for 1 hour. NCD growth was then performed using a 1.5% CH.sub.4/H.sub.2 concentration at a temperature of 400? C., pressure of 15 Torr, and power of 800 W for about 6 hours to produce an NCD film having a thickness of about 100 nm. Growth temperature for the NCD can range up to 650? C., with the other parameters also being adjustable as appropriate, i.e., power can range from 500-1000 W, pressure can range from 5-20 Torr, and the CH.sub.4/H.sub.2 concentration can range from 0.5 to 3%, with the specific values of each of these parameters depending on the process conditions and the intended end use of the device.

[0039] The NCD layer and SiN.sub.x interlayer were then etched to expose the source/drain metal contacts on which electrical connections are made and to define the gate region. In an exemplary embodiment, this etching can be performed using an O.sub.2 inductively coupled plasma (ICP) etch of the NCD layer at 1000 W ICP power and 100 W reactive-ion etch (RIE) power, followed by an ICP-RIE SF.sub.6 etch of the SiN.sub.x interlayer at ICP 200 W, RIE 50 W, but other suitable etching conditions can be used, e.g., pressures of about 5 mT, O.sub.2 flow rate of 10-50 sccm, and temperatures of about 20-30? C. In other embodiments, the etch can be performed using a SF.sub.6 plasma rather than an O.sub.2 plasma.

[0040] Following the etching of the NCD and SiN.sub.x, a 22 nm HfO.sub.2 gate dielectric layer 108 was then deposited by atomic layer deposition (ALD) on the upper surface of the NCD layer and the sides and bottom of the etched trench, and finally the gate contacts 109 were formed by depositing a 20/200 nm thick Ni/Au metal stack into the thus-defined trench.

[0041] Other etching regimes can also be used to define the gate area. For example, in some embodiments, a SiN.sub.x mask can be deposited on an upper surface of the NCD layer to protect the NCD surface during the SF.sub.6 etch, while in other embodiments, a wet etching (e.g., using buffered HF) can be used on the SiN.sub.x interlayer to minimize plasma damage to the Ga.sub.2O.sub.3 active region. In still other embodiments, the gate area can be defined by etching the SiN.sub.x layer before the growth of the NCD layer.

[0042] FIGS. 2A-2F are a ?-series of atomic force microscope (AFM) images showing NCD films grown on Ga.sub.2O.sub.3 at 400? C. (FIGS. 2A-2C) and 500? C. (FIGS. 2D-2F) with different SiN.sub.x barrier dielectric layers, i.e., with a rapid-thermal annealed (RTA) SiN.sub.x barrier layer deposited at 300? C. (FIGS. 2A and 2D), a SiN.sub.x barrier layer deposited at 400? C. (FIGS. 2B and 2E), and a SiN.sub.x barrier layer deposited at 500? C. (FIGS. 2C and 2F). The different deposition and annealing conditions of the SiN.sub.x layers were aimed at densifying these dielectric layers in order to reduce their etch rate during NCD deposition as much as possible.

[0043] The SEM images in FIGS. 3A and 3B show how a barrier dielectric layer in accordance with the present invention protects an NCD-coated Ga.sub.2O.sub.3 crystal during an H.sub.2 plasma etch. As can be seen from the image in FIG. 3A, an NCD-coated Ga.sub.2O.sub.3 crystal that is not protected with a dielectric coating is damaged during the etch, with multiple gallium droplets being readily visible on the surface of the crystal. In contrast, the NCD-coated Ga.sub.2O.sub.3 crystal shown in FIG. 3B includes a properly deposited barrier dielectric, and exhibits a smooth, continuous NCD layer on the surface of the Ga.sub.2O.sub.3.

[0044] The plot in FIG. 4 shows Raman spectra measured on the NCD samples grown on Ga.sub.2O.sub.3 at 500? C. with different SiN.sub.x dielectric interlayers shown in FIGS. 2D-2F. These spectra show both the signature Raman mode of sp3-bonded diamond and the signature Raman modes of monoclinic ?-Ga.sub.2O.sub.3, confirming growth of the high quality NCD film on ?-Ga.sub.2O.sub.3 without compromising the Ga.sub.2O.sub.3 quality. This would not be possible to do on a wafer scale without the use of a barrier dielectric such as SiN.sub.x, precluding the use of NCD as top-side heat spreading layer for thermal management of Ga.sub.2O.sub.3 electronic devices.

[0045] The plot in FIG. 5 shows Raman spectra of NCD films grown on Ga.sub.2O.sub.3 with a protective SiN.sub.x interlayer in accordance with the present invention up to a temperature of 650? C. The presence of a Raman peak near 1340 cm.sup.?1, specifically at 1332.5 cm.sup.?1, confirms the covalent sp3 bonding of the deposited NCD layer. The higher NCD deposition temperature leads to increased NCD grain size and thermal conductivity without compromising the underlying Ga.sub.2O.sub.3 layers, enabling more efficient heat spreading compared to NCD grown at a lower temperature, e.g., at 400? C.

[0046] Thus, as confirmed by the Raman spectra in FIGS. 4 and 5, high-quality NCD thermal management layers can successfully be grown on Ga.sub.2O.sub.3 having a SiN.sub.x interlayer deposited thereon before growth of the NCD, in accordance with the present invention.

[0047] To test the performance of a device having a structure such as that illustrated in FIG. 1, on-state drain current was measured via DC current-voltage testing for a reference HFET lacking an NCD/SiN.sub.x stack in accordance with the present invention (FIG. 6A) and an HFET having an NCD/SiN.sub.x stack in accordance with the present invention (FIG. 6B).

[0048] As can be seen from the plots in FIGS. 6A and 6B, the reference device without the incorporation of an NCD/SiN.sub.x stack (FIG. 6A) is in a depletion mode or normally-on, and has a much larger on/off current ratio than is exhibited by a device having an NCD/SiN.sub.x stack in accordance with the present invention (FIG. 6B), i.e., V.sub.DS=10V vs. V.sub.DS=5V. By etching through the NCD/SiN.sub.x layers above the gate in a device in accordance with the present invention, as illustrated in FIG. 1, enhancement mode, or normally-off device behavior, can be achieved. It is well known that enhancement mode transistors are highly desirable for operational safety of power electronic systems, and so the present invention enables the formation of these highly desirable devices.

[0049] The plots in FIGS. 7A and 7B show the DC output curves for the devices with and without an NCD/SiN.sub.x stack discussed above with respect to FIGS. 6A and 6B. As can be seen by the plots in FIGS. 7A and 7B, the reference device without the NCD/SiN.sub.x stack in accordance with the present invention (FIG. 7A) shows a 20? higher drain current compared to the device having such a stack (FIG. 7B). That is, as illustrated by the plot in FIG. 7B, a lower drain current is seen in the device having the NCD/SiN.sub.x stack, likely due to the plasma damage to the ?-(Al.sub.xGa.sub.1-x).sub.2O.sub.3 active region during diamond formation in the structure without the protective dielectric layer. Although lower drain current is observed, we still achieve current modulation with this device structure. Improvement to the NCD/SiN.sub.x removal process during gate formation will result in higher drain current.

[0050] Thermal measurements of devices with and without an NCD/SiN.sub.x stack were performed using a TMX Scientific T? Imager (532 nm, 100? objective) at a base temperature maintained at 20? C. Power dissipated in the device was monitored using an oscilloscope. A maximum power density of ?0.6.58 W/mm, with a gate voltage of 0 V, was measured before catastrophic failure occurred on the Gate on NCD device.

[0051] The plot in FIG. 8 shows the average temperature rise at the gate as a function of power density where the slope corresponds to the device thermal resistance. A 40% reduction in the thermal resistance at the gate electrode was observed with the incorporation of the NCD heat spreading layer when compared to a reference uncapped HFET. Optimization of the NCD/SiN.sub.x etch within the gate region will be required to maintain good device performance with the incorporation of this thermal management technique.

Advantages and New Features

[0052] The main new feature introduced by the present invention is the reduced device temperature as measured by thermoreflectance imaging of the source/drain/gate metal contacts of the fabricated device. The thermal resistance reduction in the device from 44.5 mmK/W to 25.5 mmK/W, combined with the high maximum power density in the on state, are the best reported for a Gallium Oxide transistor to-date.

[0053] The improved thermal management of such Ga.sub.2O.sub.3-based devices provided by NCD films that can be deposited on the Ga.sub.2O.sub.3 due to the presence of a dielectric interlayer in accordance with the present invention leads to lower device operating temperature, increased carrier mobility, higher measured output current density, improved thermal budget, as well as improved overall device reliability.

[0054] Alternative approaches to thermal management in gallium oxide devices has been proposed via wafer bonding to higher thermal conductivity substrate such as silicon, silicon carbide, or diamond. See Y. Xu et al., Direct wafer bonding of Ga.sub.2O.sub.3SiC at room temperature, Ceramics International 45 (5) 6552 (2019); M. Liao et al., Interfacial Thermal Transport of Thinned and Chemical Mechanical Polished (?201) ?-Ga2O3 Direct Wafer Bonded to (001) Si, Electronic Materials Conference, 2022, pp. 110-111; and T. Matsumae et al., supra.

[0055] However, this approach has not resulted in levels of thermal resistance reduction observed via the top-side diamond capping approach of the present invention. Other alternative methods include capping via materials other than diamond, such as aluminum nitride, but again, such methods have been less effective due to lower thermal conductivity of the capping layer. See J. S. Lundh et al., AlN-capped ?-(Al.sub.xGa.sub.1-x).sub.2O.sub.3/Ga.sub.2O.sub.3 heterostructure field-effect transistors for near-junction thermal management of next generation power devices, Proc. Dev. Res. Conf. (2022).

ALTERNATIVES

[0056] Although particular embodiments, aspects, and features have been described and illustrated, one skilled in the art would readily appreciate that the invention described herein is not limited to only those embodiments, aspects, and features but also contemplates any and all modifications and alternative embodiments that are within the spirit and scope of the underlying invention described and claimed herein.

[0057] For example, although the present invention is described in the context of ?-Ga.sub.2O.sub.3, an NCD/SiN.sub.x stack can also be used for thermal management of devices based on other forms of Ga.sub.2O.sub.3 such as ?-Ga.sub.2O.sub.3, ?-Ga.sub.2O.sub.3, ?-Ga.sub.2O.sub.3, ?-Ga.sub.2O.sub.3, or ?-Ga.sub.2O.sub.3.

[0058] An NCD/SiN.sub.x or an NCD/SiO.sub.2 stack in accordance with the present invention can also be incorporated into devices based on alloys of Ga.sub.2O.sub.3, such as devices based on (Al.sub.xGa.sub.1-x).sub.2O.sub.3, where 0?x?1.

[0059] The present application contemplates any and all modifications within the spirit and scope of the underlying invention described and claimed herein, and all such modifications and alternative embodiments are deemed to be within the scope and spirit of the present disclosure.