Differential Amplifier and Method for Enhancing Gain of a Differential Amplifier

Abstract

A differential amplifier is provided. The differential amplifier includes a first single-ended amplifying means including at least a first terminal and a second terminal, a second single-ended amplifying means including at least a first terminal and a second terminal, a first transmission line, and a second transmission line. In this context, the first terminal of the first single-ended amplifying means is connected to the second terminal of the second single-ended amplifying means via the first transmission line. In addition to this, the first terminal of the second single-ended amplifying means is connected to the second terminal of the first single-ended amplifying means via the second transmission line.

Claims

1. A differential amplifier comprising: a first single-ended amplifier comprising a first terminal and a second terminal; a second single-ended amplifier comprising a first terminal and a second terminal; a first transmission line; and a second transmission line, wherein the first terminal of the first single-ended amplifier is connected to the second terminal of the second single-ended amplifier via the first transmission line, and wherein the first terminal of the second single-ended amplifier is connected to the second terminal of the first single-ended amplifier via the second transmission line.

2. The differential amplifier according to claim 1, further comprising: a first capacitance between the first terminal of the first single-ended amplifier and the first transmission line or between the first transmission line and the second terminal of the second single-ended amplifier; and a second capacitance between the first terminal of the second single-ended amplifier and the second transmission line or between the second transmission line and the second terminal of the first single-ended amplifier.

3. The differential amplifier according to claim 2, wherein a value of the first capacitance is between 50 femtofarad and 200 femtofarad or between 100 femtofarad and 150 femtofarad, per millimeter of a length of the first transmission line, and wherein a value of the second capacitance is between 50 femtofarad and 200 femtofarad or between 100 femtofarad and 150 femtofarad, per millimeter of a length of the second transmission line.

4. The differential amplifier according to claim 2, wherein a value of the first capacitance is between one and three times or between 1.5 and 2.5 times a value of a first-terminal-to-second-terminal capacitance of the first single-ended amplifier, and wherein a value of the second capacitance is between one and three times or between 1.5 and 2.5 times a value of a first-terminal-to-second-terminal capacitance of the second single-ended amplifier.

5. The differential amplifier according to claim 2, further comprising: a first passive element network between the first terminal of the first single-ended amplifier and the first transmission line or between the first terminal of the first single-ended amplifier and the first capacitance; and a second passive element network between the first terminal of the second single-ended amplifier and the second transmission line or between the first terminal of the second single-ended amplifier and the second capacitance.

6. The differential amplifier according to claim 5, wherein the first passive element network comprises a first inductance, and wherein the second passive element network comprises a second inductance.

7. The differential amplifier according to claim 2, further comprising: a third passive element network between the second terminal of the first single-ended amplifier and the second transmission line or between the second terminal of the first single-ended amplifier and the second capacitance; and a fourth passive element network between the second terminal of the second single-ended amplifier and the first transmission line or between the second terminal of the second single-ended amplifier and the first capacitance.

8. The differential amplifier according to claim 7, wherein the third passive element network comprises a third, and wherein the fourth passive element network comprises a fourth inductance.

9. The differential amplifier according to claim 1, wherein a length of the first transmission line is at least 50 micrometers or at least 100 micrometers, and wherein a length of the second transmission line is at least 50 micrometers or at least 100 micrometers.

10. The differential amplifier according to claim 1, wherein the first single-ended amplifier comprises a first transistor, wherein the first terminal of the first single-ended amplifier is connected to a gate terminal of the first transistor and the second terminal of the first single-ended amplifier is connected to a drain terminal of the first transistor, and wherein the second single-ended amplifier comprises a second transistor, wherein the first terminal of the second single-ended amplifier is connected to a gate terminal of the second transistor and the second terminal of the second single-ended amplifier is connected to a drain terminal of the second transistor.

11. A method for gain adjustment of a differential amplifier, the method comprising: providing a first single-ended amplifier comprising a first terminal and a second terminal, a second single-ended amplifier comprising a first terminal and a second terminal, a first transmission line, and a second transmission line, connecting the first terminal of the first single-ended amplifier to the second terminal of the second single-ended amplifier via the first transmission line, and connecting the first terminal of the second single-ended amplifier to the second terminal of the first single-ended amplifier via the second transmission line.

12. The method according to claim 11, further comprising: inserting a first capacitance between the first terminal of the first single-ended amplifier and the first transmission line or between the first transmission line and the second terminal of the second single-ended amplifier; and inserting a second capacitance between the first terminal of the second single-ended amplifier and the second transmission line or between the second transmission line and the second terminal of the first single-ended amplifier.

13. The method according to claim 11, further comprising tracking a stability factor of the differential amplifier.

14. The method according to claim 11, further comprising: configuring a coupling between the first terminal of the first single-ended amplifier and the second terminal of the second single-ended amplifier such that a stability factor of the differential amplifier is nearly equal to one; and configuring a coupling between the first terminal of the second single-ended amplifier and the second terminal of the first single-ended amplifier such that a corresponding stability factor of the differential amplifier is nearly equal to one.

15. The method according to claim 11, further comprising: using the differential amplifier to amplify a signal having a wavelength, wherein a length of the first transmission line is between a twentieth and a quarter, or between a fifteenth and a sixth, of the wavelength, and wherein a length of the second transmission line is between a twentieth and a quarter, or between a fifteenth and a sixth, of the wavelength.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0037] The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.

[0038] Exemplary embodiments of the disclosure are now further explained with respect to the drawings by way of example only, and not for limitation. In the drawings:

[0039] FIG. 1 shows a differential amplifier comprising capacitors in series with corresponding transmission lines, according to an example.

[0040] FIG. 2A illustrates a differential G.sub.max-core, according to an example.

[0041] FIG. 2B shows a single-ended representation of FIG. 2A for 2-port analysis, according to an example.

[0042] FIG. 3A shows a plot of G.sub.ma versus θ, according to an example.

[0043] FIG. 3B shows a plot of G.sub.ma versus K.sub.f, according to an example.

[0044] FIG. 4A shows a broadband G.sub.max-core, according to an example.

[0045] FIG. 4B illustrates trace fitting in the context of FIG. 4A, according to an example.

[0046] FIG. 5A shows a plot of gain (versus frequency) of the implemented core of FIG. 4A, according to an example.

[0047] FIG. 5B shows a plot of stability (over frequency) of the implanted core of FIG. 4A, according to an example.

[0048] FIG. 5C shows a plot of 0 (versus frequency) of the implemented core according to FIG. 4A, according to an example.

[0049] FIG. 6 shows a flow chart of a method, according to an example.

[0050] All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

[0051] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.

[0052] FIG. 1 is a block diagram of a differential amplifier or the core thereof, for example the G.sub.max-core thereof. According to FIG. 1, the differential amplifier comprises a first transistor 11, a second transistor 12, a first transmission line 13, and a second transmission line 14.

[0053] In this context, a gate terminal of the first transistor 11 is connected to a drain terminal of the second transistor 12 via the first transmission line 13. Additionally, a gate terminal of the second transistor 12 is connected to a drain terminal of the first transistor 11 via the second transmission line 14.

[0054] The circuit diagram according to FIG. 1, for example the depicted connections thereof, can be summarized as follows: The gate terminal of the first transistor 11 is connected to a first terminal of the first transmission line 13, whereas a second terminal of the first transmission line 13 is connected to the drain terminal of the second transistor 12. By analogy therewith, the gate terminal of the second transistor 12 is connected to a first terminal of the second transmission line 14, whereas a second terminal of the second transmission line 14 is connected to the drain terminal of the first transistor 11.

[0055] Furthermore, the second terminal of the second transmission line 14 may be connected to a first tap terminal 41. Additionally or alternatively, the second terminal of the first transmission line 13 may be connected to a second tap terminal 42. It is further noted that the first terminal of the first transmission line 13 may be connected to a third tap terminal 43. The first terminal of the second transmission line 14 may be connected to a fourth tap terminal 44. Moreover, a source terminal of the first transistor 11 may be connected to ground. In addition to this or as an alternative, a source terminal of the second transistor 12 may be connected to ground.

[0056] As it will be explained regarding FIG. 4A, the differential amplifier further comprises a first capacitance 21, a first capacitor, wherein the first capacitance 21, the first capacitor, is inserted between the gate terminal of the first transistor 11 and the first transmission line 13 in a serial manner.

[0057] Additionally or alternatively, the differential amplifier further comprises a second capacitance 22, a second capacitor, wherein the second capacitance 22, the second capacitor, is inserted between the gate terminal of the second transistor 12 and the second transmission line 14 in a serial manner.

[0058] Furthermore, it is noted that the length of the first transmission line 13 or TL, may be between a twentieth and a tenth, for example, between a sixteenth and a fourteenth, of the respective signal wavelength. In addition to this or as an alternative, the length of the second transmission line 14 or TL, may be between a twentieth and a tenth, for example between a sixteenth and a fourteenth, of the respective signal wavelength.

[0059] For example, the length of the first transmission line 13 or TL, is at least 50 μm, for example at least 100 μm. Additionally or alternatively, the length of the second transmission line 14 or TL, may be at least 50 μm, for example at least 100 μm.

[0060] For example, the value of the first capacitance Co is between one and three times, for example between 1.5 and 2.5 times, the value of the respective parasitic gate capacitance of the first transistor 11 or M.sub.1. For example, the value of the second capacitance C.sub.gd is between one and three times, for example between 1.5 and 2.5 times, the value of the respective parasitic gate capacitance of the second transistor 12 or M.sub.2.

[0061] Furthermore, the value of the first capacitance C.sub.gd may be between 50 fF and 200 fF, for example between 100 fF and 150 fF, per millimeter of the length of the first transmission line 13 or TL. In addition to this or as an alternative, the value of the second capacitance C.sub.gd may be between 50 fF and 200 fF, for example between 100 fF and 150 fF, per millimeter of the length of the second transmission line 14 or TL.

[0062] In an example, the first transistor and the second transistor have the same properties. Additionally or alternatively, the first transmission line and the second transmission line may have the same properties. In further addition to this or as further alternative, the first capacitance and the second capacitance may have the same properties.

[0063] For example, at least one of the first transmission line and the second transmission line is replaced by appropriate high-order passives. Additionally or alternative, in the case that at least one of the first capacitance and the second capacitance is present, at least one of the corresponding series connections may for example be replaced by appropriate high-order passives.

[0064] FIG. 2A shows a differential amplifier or G.sub.max-core. Before the working principle of the differential G.sub.max-core is investigated with the aid of FIG. 2A and FIG. 2B, it is remembered that G.sub.max denotes the enhanced gain.

[0065] In general, the present disclosure comprises a broadband gain boosting technique which can achieve the G.sub.max for the ultra-broad band without gain drop, thus, expanding its usage in the broad band system. Furthermore, the broad band technique is applied on the respective differential pair, whereas the conventional structures mostly rely on the single-ended configuration.

[0066] In addition to the enhanced gain G.sub.max, it is noted that two further types of gain are of interest in the following: the maximum available gain denoted as G.sub.ma, and the unilateral gain denoted as U.

[0067] With respect to G.sub.ma, it is noted that the input and the output may be conjugate matched. In this context, the corresponding stability factor, denoted as K.sub.f, may be greater than one. In an example, U is invariant with linear, lossless, and reciprocal passive embedding.

[0068] Again, with respect to FIG. 2A, the core is embedded by gate, drain, and cross-coupled passives. The feedback path is achieved through the cross-coupled components while the gate and drain embedding provide additional design freedom as utilized in the single-ended configuration.

[0069] The differential structure can be interpreted as a 2-port network and, hereby, simplified to an equivalent single-ended configuration in FIG. 2B, wherein each Y-parameter can be translated to:

[00001]$$\begin{gathered} \begin{array}{cc}{Y}_{\mathrm{tr}}=\frac{Y_{\mathrm{tr},s}}{2},Y_g=\frac{Y_{g,s}}{2},Y_d=\frac{Y_{d,s}}{2}, \\ {Y}_{\mathrm{gd}}=\frac{1}{2}\left[\begin{array}{cc}{Y}_{\mathrm{gd},s,11}& -Y_{\mathrm{gd},s,12}\\ -Y_{\mathrm{gd},s,21}& Y_{\mathrm{gd},s,22}\end{array}\right]& \left(1\right)\end{array} \end{gathered}$$

[0070] Compared to the single-ended configuration, its Y-parameters are scaled by half and Y.sub.gd,12 and Y.sub.gd,21 of the cross-coupled passive change their signs due to the cross-coupling. Given the two-port parameters of the core, required conditions to achieve the G.sub.max are:

K.sub.f=1

θ=180°,

[0071] wherein K.sub.f denotes the above-mentioned stability factor and θ is a phase of a transfer parameter ratio

[00002]$\frac{Y_{\mathrm{core},21}}{Y_{core,12}}.$

The equivalent expression in 2-port parameters is:

[00003]$\begin{array}{cc}-G_{\max }=\frac{Y_{core,21}}{Y_{c\mathrm{ore},12}}.& \left(2\right)\end{array}$

[0072] Along with the required G.sub.max conditions for each embedding component, the derivation of the maximal available gain G.sub.ma with respect to K.sub.f and θ indicates a direction for the broadband core design:

[00004]$\begin{array}{cc}{G}_{ma}=\frac{1}{2}\left\{{\mathrm{Ua}}^2-2a\cos \theta \left(U-1\right)+U+\sqrt{{\left({\mathrm{Ua}}^2-2a\cos \theta \left(U-1\right)+U\right)}^2-4a^2}\right\},& \left(3\right)\end{array}$

[0073] wherein a=K.sub.f−√{square root over (K.sub.f.sup.2−1)} and U is the above-mentioned unilateral gain of the core.

[0074] The G.sub.ma as a function of K.sub.f and θ in equation (3) and FIGS. 3A and 3B highlight an interesting finding that the G.sub.ma varies drastically with K.sub.f deviation around 1 rather than 0.

[0075] This explains extremely narrow gain peaks around the target frequency, where K.sub.f varies across 1, limiting the usage of conventional G.sub.max-cores to the narrow band system.

[0076] The G.sub.max-core thereby devises an embedding network that tracks K.sub.f=1 condition for the frequency range of interest to avoid a G.sub.ma drop and to achieve a broadband operation.

[0077] A broadband G.sub.max-core with embedding passives is shown in FIG. 4A. The core consists of gate inductors denoted as L.sub.g, and drain inductors denoted as L.sub.d, and cross-coupled components. In this case, the embedding passives are implemented in two steps.

[0078] The circuit diagram according to FIG. 4A, for example the depicted connections thereof, can be summarized as follows: As already stated regarding FIG. 1 above, the circuit of FIG. 4A comprises a first transistor 11, a second transistor 12, a first capacitance 21, for example a first capacitor with value C.sub.gd, and a second capacitance 22, for example a second capacitor with value C.sub.gd. For example, the first capacitance 21 and the second capacitance 22 have the same value.

[0079] Furthermore, in accordance with FIG. 4A, the circuit may comprise a first inductance 31, for example a first inductor with value L.sub.g, a second inductance 32, for example a second inductor with value L.sub.g, a third inductance 33, for example a third inductor with value L.sub.d, and fourth inductance 34, for example a fourth inductor with value L.sub.d.

[0080] In this exemplary case of FIG. 4A, a gate terminal of the first transistor 11 is connected to a first terminal of the first inductance 31, whereas a second terminal of the first inductance 31 is connected to a first terminal of the first capacitance 21. A second terminal of the first capacitance 21 is connected to a first terminal of the first transmission line 13, whereas a second terminal of the first transmission line 13 is connected to a first terminal of the fourth inductance 34. Furthermore, a second terminal of the fourth inductance 34 is connected to a drain terminal of the second transistor 12.

[0081] Moreover, a gate terminal of the second transistor 12 is connected to a first terminal of the second inductance 32, whereas a second terminal of the second inductance 32 is connected to a first terminal of the second capacitance 22. A second terminal of the second capacitance 22 is connected to a first terminal of the second transmission line 14, whereas a second terminal of the second transmission line 14 is connected to a first terminal of the third inductance 33. Furthermore, a second terminal of the third inductance 33 is connected to a drain terminal of the first transistor 11.

[0082] It is noted that the second terminal of the second transmission line 14 may be connected to a first tap terminal 41. The second terminal of the first transmission line 13 may be connected to a second tap terminal 42. Furthermore, the first terminal of the first capacitance 21 may be connected to a third tap terminal 43. The first terminal of the second capacitance 22 may be connected to a fourth tap terminal 44. Moreover, a source terminal of the first transistor 11 may be connected to ground. In addition to this or as an alternative, a source terminal of the second transistor 12 may be connected to ground.

[0083] For example, alternative embodiments of the circuit according to FIG. 4A are deduced from the embodiment depicted in FIG. 4A by shorting at least one, for example at least two, of the inductances 31, 32, 33, 34. In this context, shorting may be performed in a symmetric manner, i.e. each of the first and the second inductance 31, 32, which can also be called “gate inductances,” is shorted. Additionally or alternatively, each of the third and the fourth inductances 33, 34, which can also be called “drain inductances,” is shorted.

[0084] First, the L.sub.g, L.sub.d, and Y.sub.gd are designed to satisfy the G.sub.max conditions at the center frequency. Second, the cross-coupled passive Y.sub.gd is manipulated such that the required Y-parameter values for K.sub.f=1 can be tracked for broad frequency range.

[0085] Furthermore, the required Y.sub.gd (b.sub.tar) satisfying the K.sub.f=1 condition can be calculated from:

[00005]$\begin{array}{cc}{K}_f=\frac{2g_{\mathrm{eq},11}{g}_{\mathrm{eq},22}-Re\left\{Y_{\mathrm{eq},21}{Y}_{\mathrm{eq},12}\right\}}{.Math.Y_{\mathrm{eq},21}{Y}_{\mathrm{eq},12}.Math.}=1,& \left(4\right)\end{array}$

[0086] wherein Y.sub.x=g.sub.x+jb.sub.x.

[0087] By solving the above-mentioned equation (4):

[00006]$\begin{array}{cc}{b}_{\mathrm{tar}}=\mathrm{Im}\left(Y_{\mathrm{gd},12}\right)=b_{\mathrm{gd},12}=b_{\mathrm{gd},21}=\frac{-E\pm \sqrt{E^2-4DF}}{2D},& \left(5\right)\end{array}$
D=g.sub.cas,12.sup.2+g.sub.cas,21.sup.2−4g.sub.cas,11g.sub.cas,22+2g.sub.cas,21g.sub.cas,12,E=2g.sub.cas,12.sup.2b.sub.cas,21+2g.sub.cas,21.sup.2b.sub.cas,12+(2g.sub.cas,21g.sub.cas,12−4g.sub.cas,11g.sub.cas,22)(b.sub.cas,21+g.sub.cas,12),F=g.sub.cas,12.sup.2b.sub.cas,21.sup.2+g.sub.cas,21.sup.2b.sub.cas,12.sup.2−4g.sub.cas,11.sup.2g.sub.cas,22.sup.2+4g.sub.cas,11g.sub.cas,22g.sub.cas,21g.sub.cas,12−2b.sub.cas,21b.sub.cas,12(2g.sub.cas,11g.sub.cas,22−g.sub.cas,21g.sub.cas,12).

[0088] In this context according to equation (5) above, it is noted that terms comprising g.sub.cas and/or bias are defined by the above-mentioned formula Y.sub.x=g.sub.x+jb.sub.x. Additionally or alternatively, the definition may be based on the block denoted as Y.sub.cas in FIG. 2B.

[0089] As the b.sub.tar from equation (5) in FIG. 4B exhibits positive value, the cross-coupled embedding should be capacitive and requires a series capacitor. In addition, to increase the order of freedom on the cross-coupled passive and to track the b.sub.tar across the frequency, a transmission line (TL) is connected in series with the capacitor Co as shown in FIG. 4A, which forms a Y.sub.gd:

[00007]$\begin{array}{cc}{Y}_{\mathrm{gd}}=\frac{1}{2}\left[\begin{array}{cc}j\omega C_{\mathrm{gd}}+\frac{j{Z}_0\tan \left(\beta l_{gd}\right){\omega }^2{C}_{\mathrm{gd}}^2}{1-Z_0\tan \left(\beta l_{gd}\right)\omega c_{gd}}& \frac{{j\mathrm{\omega C}}_{\mathrm{gd}}}{\cos \left(\beta l_{gd}\right)\left(1-Z_0\tan \left(\beta l_{gd}\right){\omega C}_{gd}\right)}\\ \frac{{j\omega C}_{gd}}{\cos \left(\beta l_{gd}\right)\left(1-Z_0\tan \left(\beta l_{gd}\right){\omega C}_{gd}\right)}& \frac{1}{j{Z}_0\tan \left(\beta l_{gd}\right)}+\frac{j}{Z_0\sin \left(\beta l_{gd}\right)\left(1-Z_0\tan \left(\beta l_{gd}\right){\omega C}_{gd}\right)}\end{array}\right],& \left(6\right)\end{array}$

[0090] wherein Z.sub.0 is a characteristic impedance of the transmission line TL, β is a phase constant and l.sub.gd is a length of the transmission line TL.

[0091] Moreover, to satisfy the G.sub.max condition at the center frequency, the C.sub.gd in equation (6) should satisfy the following equation:

[00008]$\begin{array}{cc}{C}_{\mathrm{gd}}=\frac{b_{\mathrm{tar},\mathrm{center}}.Math.\cos \left({\beta }_{\mathrm{center}}{l}_{\mathrm{gd}}\right)}{2\pi f_0\left(0.5+b_{\mathrm{tar},\mathrm{center}}.Math.Z_0\sin \left({\beta }_{\mathrm{center}}{l}_{\mathrm{gd}}\right)\right)},& \left(7\right)\end{array}$

[0092] wherein b.sub.tar,center and β.sub.center stand for b.sub.tar and β at the center frequency f.sub.0.

[0093] The required Z.sub.0 and l.sub.gd for the broadband operation can exemplarily be driven with the help of least squares method:

[00009]$\begin{array}{cc}\underset{Z_0,l_{gd}}{\min }\underset{f_l}{\overset{f_h}{.Math.}}{\left(b_{\mathrm{tar}}-b_{\mathrm{gd},12}\right)}^2,& \left(8\right)\end{array}$

[0094] wherein f.sub.1<f.sub.0<f.sub.h and f.sub.l and f.sub.h are targeted boundaries at the lowest and the highest frequency, respectively.

[0095] Furthermore, the respective trace fitting with equation (8) in FIG. 4B shows that the targeted b.sub.tar can be successfully approximated with appropriate passive models, for example with the aid of the series connection of C.sub.gd and TL, resulting in a near 1 K.sub.f for broad frequency range.

[0096] Moreover, the post-layout simulation results presented by FIG. 5A, FIG. 5B, and FIG. 5C prove that K.sub.f=1 condition is sustained for more than 80 GHz at 144 GHz, while its G.sub.ma tightly follows G.sub.max within 1 dB deviation which is mainly due to the passive losses. The θ deviation in FIG. 5C is less than 30° which has a minor impact on the gain as described in FIG. 3A.

[0097] With respect to FIG. 5A, it is further noted that the depicted “G.sub.max”-curve can be understood as a theoretical target curve, whereas the “Trace Fitting”-curve can be interpreted as a curve with ideal lumped components. Furthermore, the “Implemented”-curve of FIG. 5A can be based on a layout extracted, whereas the “Unilateral”-curve can be seen as a curve based on unilateral gain.

[0098] Furthermore, with respect to FIG. 5B and FIG. 5C, it is noted that these figures show the above-mentioned “Trace Fitting”-curve and “Implemented”-curve in the context of the corresponding stability factor and the above-mentioned θ deviation.

[0099] It can be summarized that the present disclosure allows for achieving enhanced gain (G.sub.max) of the amplifier or transistor, for broad bandwidth. Based on the finding that a stability factor (K.sub.f) deviation around 1 highly degrades a maximum available gain (G.sub.ma) and incurs gain drop around the center frequency, the G.sub.max-core devises embedding passives in differential configuration which can sustain the K.sub.f=1 condition for broad frequency range. The core tracks the theoretical G.sub.max more than 80 GHz at 144 GHz, enabling the usage of the G.sub.max-core in ultra-broadband applications.

[0100] Accordingly, with the aid of the present disclosure, several limitations of conventional gain-boosting cores can be alleviated. For example, such limitations are:

[0101] Some conventional cores are achieved for the single frequency with extremely narrow bandwidth due to its sharp gain peaking nature.

[0102] Some (dual-peaking) conventional cores expand the bandwidth with two gain peaks placed apart while revealing few dBs of gain drop between the gain peaks, still suffering from the gain-bandwidth trade off.

[0103] Most conventional cores are achieved not in a differential configuration but only in a single-ended one.

[0104] For instance, by having overcome the limitations, the disclosure can be utilized in the high frequency front-end where both the high gain and broad bandwidth should be achieved such as PAs and LNAs in transceivers for communications and radars above 100 GHz.

[0105] For example, the disclosure is implemented in 28 nm CMOS technology.

[0106] Finally, FIG. 6 shows a flow chart of a method for enhancing gain (G.sub.max) of a differential amplifier. In a first step 100, a gate terminal of a first transistor, such as the above-mentioned transistors 11 and M.sub.1, of the differential amplifier is connected to a drain terminal of a second transistor, such as the above-mentioned transistors 12 and M.sub.2, of the differential amplifier via a first transmission line, such as the above-mentioned transmission lines 13 and TL.

[0107] Then, in a second step 101, a gate terminal of the second transistor of the differential amplifier is connected to a drain terminal of the first transistor of the differential amplifier via a second transmission line, such as the above-mentioned transmission lines 14 and TL.

[0108] For example, the method further comprises the step of inserting a first capacitance, such as the above-mentioned capacitance C.sub.gd, a first capacitor, between the gate terminal of the first transistor and the first transmission line in a serial manner. In addition to this or as an alternative, the method may comprise the step of inserting a second capacitance, such as C.sub.gd mentioned above, a second capacitor, between the gate terminal of the second transistor and the second transmission line in a serial manner.

[0109] Furthermore, the length of the first transmission line may be between a twentieth and a tenth, for example between a sixteenth and a fourteenth, of the corresponding signal wavelength with respect to the differential amplifier. Additionally or alternatively, the length of the second transmission line may be between a twentieth and a tenth, for example between a sixteenth and a fourteenth, of the corresponding signal wavelength with respect to the differential amplifier.

[0110] It is further noted that the length of the first transmission line may be at least 50 μm, for example at least 100 μm. Additionally or alternatively, the length of the second transmission line may be at least 50 μm, for example at least 100 μm.

[0111] For example, the value of the first capacitance is between one and three times, for example between 1.5 and 2.5 times, the value of the respective parasitic gate capacitance of the first transistor of the differential amplifier.

[0112] For example, the value of the second capacitance is between one and three times, for example between 1.5 and 2.5 times, the value of the respective parasitic gate capacitance of the second transistor of the differential amplifier.

[0113] Furthermore, the value of the first capacitance may be between 50 fF and 200 fF, for example between 100 fF and 150 fF, per millimeter of the length of the first transmission line. Additionally or alternatively, the value of the second capacitance may be between 50 fF and 200 fF, for example between 100 fF and 150 fF, per millimeter of the length of the second transmission line.

[0114] For example, the method further comprises the step of tracking the corresponding stability factor (K.sub.f) with respect to the differential amplifier.

[0115] Moreover, the method may further comprise the step of configuring the corresponding coupling between the gate terminal of the first transistor of the differential amplifier and the drain terminal of the second transistor of the differential amplifier such that the corresponding stability factor (K.sub.f) with respect to the differential amplifier is constantly nearly one, constantly one, more constantly nearly one over a desired frequency range, most constantly one over a desired frequency range, for example, in the case of tracking the corresponding stability factor (K.sub.f), on the basis of the tracked stability factor.

[0116] In addition to this or as an alternative, the method may comprise the step of configuring the corresponding coupling between the gate terminal of the second transistor of the differential amplifier and the drain terminal of the first transistor of the differential amplifier such that the corresponding stability factor (K.sub.f) with respect to the differential amplifier is constantly nearly one, constantly one, more constantly nearly one over a desired frequency range, most constantly one over a desired frequency range, for example, in the case of tracking the corresponding stability factor (K.sub.f), on the basis of the tracked stability factor.

[0117] While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present disclosure should not be limited by any of the above described embodiments. Rather, the scope of the disclosure should be defined in accordance with the following claims and their equivalents.

[0118] Although the disclosure has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.

[0119] While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.