COPPER/CERAMIC ASSEMBLY AND INSULATING CIRCUIT SUBSTRATE

Abstract

This copper/ceramic assembly includes: a copper member consisting of copper or a copper alloy; and a ceramic member consisting of silicon nitride, wherein the copper member and the ceramic member are bonded. At a bonded interface between the ceramic member and the copper member, an active metal nitride layer is formed on a side of the ceramic member. In a region extending by 10 ?m from the active metal nitride layer toward a side of the copper member, an area rate of an active metal compound containing Si and an active metal is 10% or less. A ratio P.sub.A/P.sub.B of an area rate P.sub.A of the active metal compound in a peripheral part region of the copper member to an area rate P.sub.B of the active metal compound in a central part region of the copper member is in a range of 0.7 or more and 1.4 or less.

Claims

1. A copper/ceramic assembly obtained by bonding a copper member consisting of copper or a copper alloy and a ceramic member consisting of silicon nitride, wherein at a bonded interface between the ceramic member and the copper member, an active metal nitride layer is formed on a side of the ceramic member, in a region extending by 10 ?m from the active metal nitride layer toward a side of the copper member, an area rate of an active metal compound containing Si and an active metal is 10% or less, and a ratio P.sub.A/P.sub.B of an area rate P.sub.A of the active metal compound in a peripheral part region of the copper member to an area rate P.sub.B of the active metal compound in a central part region of the copper member is in a range of 0.7 or more and 1.4 or less.

2. The copper/ceramic assembly according to claim 1, wherein a thickness t1.sub.A of the active metal nitride layer formed in the peripheral part region of the copper member and a thickness t1.sub.B of the active metal nitride layer formed in the central part region of the copper member are in a range of 0.05 ?m or more and 0.8 ?m or less, and a thickness ratio t1.sub.A/t1.sub.B is in a range of 0.7 or more and 1.4 or less.

3. The copper/ceramic assembly according to claim 1, wherein at the bonded interface between the ceramic member and the copper member, an AgCu alloy layer is formed on the side of the copper member, and a thickness t2.sub.A of the AgCu alloy layer formed in the peripheral part region of the copper member and a thickness t2.sub.B of the AgCu alloy layer formed in the central part region of the copper member are in a range of 1 ?m or more and 30 ?m or less, and a thickness ratio t2.sub.A/t2.sub.B is in a range of 0.7 or more and 1.4 or less.

4. An insulating circuit substrate obtained by bonding a copper sheet consisting of copper or a copper alloy to a surface of a ceramic substrate consisting of silicon nitride, wherein at a bonded interface between the ceramic substrate and the copper sheet, an active metal nitride layer is formed on a side of the ceramic substrate, in a region extending by 10 ?m from the active metal nitride layer toward a side of the copper sheet, an area rate of an active metal compound containing Si and an active metal is 10% or less, and a ratio P.sub.A/P.sub.B of an area rate P.sub.A of the active metal compound in a peripheral part region of the copper sheet to an area rate P.sub.B of the active metal compound in a central part region of the copper sheet is in a range of 0.7 or more and 1.4 or less.

5. The insulating circuit substrate according to claim 4, wherein a thickness t1.sub.A of the active metal nitride layer formed in the peripheral part region of the copper sheet and a thickness t1.sub.B of the active metal nitride layer formed in the central part region of the copper sheet are in a range of 0.05 ?m or more and 0.8 ?m or less, and a thickness ratio t1.sub.A/t1.sub.B is in a range of 0.7 or more and 1.4 or less.

6. The insulating circuit substrate according to claim 4, wherein at the bonded interface between the ceramic substrate and the copper sheet, an AgCu alloy layer is formed on the side of the copper sheet, and a thickness t2.sub.A of the AgCu alloy layer formed in the peripheral part region of the copper sheet and a thickness t2.sub.B of the AgCu alloy layer formed in the central part region of the copper sheet are in a range of 1 ?m or more and 30 ?m or less, and a thickness ratio t2.sub.A/t2.sub.B is in a range of 0.7 or more and 1.4 or less.

7. The copper/ceramic assembly according to claim 2, wherein at the bonded interface between the ceramic member and the copper member, an AgCu alloy layer is formed on the side of the copper member, and a thickness t2.sub.A of the AgCu alloy layer formed in the peripheral part region of the copper member and a thickness t2.sub.B of the AgCu alloy layer formed in the central part region of the copper member are in a range of 1 ?m or more and 30 ?m or less, and a thickness ratio t2.sub.A/t2.sub.B is in a range of 0.7 or more and 1.4 or less.

8. The insulating circuit substrate according to claim 5, wherein at the bonded interface between the ceramic substrate and the copper sheet, an AgCu alloy layer is formed on the side of the copper sheet, and a thickness t2.sub.A of the AgCu alloy layer formed in the peripheral part region of the copper sheet and a thickness t2.sub.B of the AgCu alloy layer formed in the central part region of the copper sheet are in a range of 1 ?m or more and 30 ?m or less, and a thickness ratio t2.sub.A/t2.sub.B is in a range of 0.7 or more and 1.4 or less.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0037] FIG. 1 is a schematic explanatory view of a power module using an insulating circuit substrate according to the embodiment of the present invention.

[0038] FIG. 2 is an enlarged explanatory view of a bonded interface between a circuit layer (a metal layer) and a ceramic substrate of the insulating circuit substrate according to the embodiment of the present invention. (a) is an explanatory view of the peripheral part region and the central part region of the circuit layer and the metal layer, (b) is an explanatory view of the peripheral part region, and (c) is an explanatory view of the central part region.

[0039] FIG. 3 is a flow chart of a method for producing the insulating circuit substrate according to the embodiment of the present invention.

[0040] FIG. 4 is a schematic explanatory view of the method for producing the insulating circuit substrate according to the embodiment of the present invention.

[0041] FIG. 5 is an explanatory view of a bonding material arranging step in the method for producing the insulating circuit substrate according to the embodiment of the present invention.

[0042] FIG. 6 is an explanatory view showing a method for calculating an area rate of an active metal compound in Examples of the present invention.

DESCRIPTION OF EMBODIMENTS

[0043] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0044] The copper/ceramic assembly according to the present embodiment is an insulating circuit substrate 10 obtained by bonding a copper sheet 42 (a circuit layer 12) and a copper sheet 43 (a metal layer 13) as copper members consisting of copper or a copper alloy to a ceramic substrate 11 as a ceramic member consisting of ceramics. FIG. 1 shows a power module 1 including the insulating circuit substrate 10 according to the present embodiment.

[0045] The power module 1 includes: the insulating circuit substrate 10 in which each of the circuit layer 12 and the metal layer 13 is arranged; a semiconductor element 3 bonded to one surface (the upper surface in FIG. 1) of the circuit layer 12 by interposing a bonding layer 2; and a heat sink 5 disposed on the other surface (the lower surface in FIG. 1) of the metal layer 13.

[0046] The semiconductor element 3 includes a semiconductor material such as Si. The semiconductor element 3 and the circuit layer 12 are bonded with the bonding layer 2 being interposed therebetween.

[0047] The bonding layer 2 is composed of, for example, an SnAg-based solder material, an SnIn-based solder material, or an SnAgCu-based solder material.

[0048] The heat sink 5 is a heat sink for dissipating heat from the insulating circuit substrate 10 described above. The heat sink 5 is composed of copper or a copper alloy, and in the present embodiment, it is composed of phosphorus deoxidized copper. The heat sink 5 includes a passage for allowing a cooling fluid to flow.

[0049] It is noted that in the present embodiment, the heat sink 5 is bonded to the metal layer 13 by a solder layer 7 which consists of a solder material. The solder layer 7 is composed of, for example, an SnAg-based solder material, an SnIn-based solder material, or an SnAgCu-based solder material.

[0050] In addition, the insulating circuit substrate 10 which is the present embodiment includes, as shown in FIG. 1, the ceramic substrate 11, the circuit layer 12 arranged on one surface of the ceramic substrate 11 (the upper surface in FIG. 1), and the metal layer 13 arranged on the other surface of the ceramic substrate 11 (the lower surface in FIG. 1).

[0051] The ceramic substrate 11 is composed of silicon nitride (Si.sub.3N.sub.4, which has excellent insulating properties and heat radiation. The thickness of the ceramic substrate 11 is set to be, for example, in a range of 0.2 mm or more and 1.5 mm or less, and the thickness thereof is 0.32 mm in the present embodiment.

[0052] As shown in FIG. 4, the circuit layer 12 is formed by bonding the copper sheet 42 consisting of copper or a copper alloy to one surface (the upper surface in FIG. 4) of the ceramic substrate 11.

[0053] In the present embodiment, the circuit layer 12 is formed by bonding a rolled sheet of oxygen-free copper to the ceramic substrate 11.

[0054] It is noted that the thickness of the copper sheet 42 which is to be the circuit layer 12 is set to be in a range of 0.1 mm or more and 2.0 mm or less, and the thickness is 0.6 mm in the present embodiment.

[0055] As shown in FIG. 4, the metal layer 13 is formed by bonding the copper sheet 43 consisting of copper or a copper alloy to the other surface (the lower surface in FIG. 4) of the ceramic substrate 11.

[0056] In the present embodiment, the metal layer 13 is formed by bonding a rolled sheet of oxygen-free copper to the ceramic substrate 11.

[0057] It is noted that the thickness of the copper sheet 43 which is to be the metal layer 13 is set to be in a range of 0.1 mm or more and 2.0 mm or less, and the thickness is 0.6 mm in the present embodiment.

[0058] At the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13, as shown in FIG. 2, an active metal nitride layer 21 and an AgCu alloy layer 22 are formed in this order from the side of the ceramic substrate 11.

[0059] It can also be said that the active metal nitride layer 21 is a part of the ceramic substrate 11. It can also be said that the AgCu alloy layer 22 is a part of each of the circuit layer 12 and the metal layer 13. For this reason, the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13 (the copper sheets 42 and 43) is an interface between the active metal nitride layer 21 and the AgCu alloy layer 22. In a case where the AgCu alloy layer 22 is not provided, the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13 (the copper sheets 42 and 43) is an interface between the active metal nitride layer 21 and each of the circuit layer 12 and the metal layer 13 (the copper sheets 42 and 43).

[0060] In addition, in the insulating circuit substrate 10 which is the present embodiment, as shown in FIG. 2(a), an interface structure in a peripheral part region A and a central part region B of each of the circuit layer 12 and the metal layer 13 is defined as follows.

[0061] It is noted that in the present embodiment, the peripheral part region A of each of the circuit layer 12 and the metal layer 13 is, as shown in FIG. 2(a), a region starting from a position at 20 ?m inward from an end portion of each of the circuit layer 12 and the metal layer 13 in a width direction to a position at 200 ?m inward in the width direction therefrom in a cross section along the lamination direction in which each of the circuit layer 12 and the metal layer 13 is laminated with the ceramic substrate 11.

[0062] In addition, as shown in FIG. 2(a), the central part region B of each of the circuit layer 12 and the metal layer 13 is a region of 200 ?m in the width direction, which includes the center of each of the circuit layer 12 and the metal layer 13 in the width direction in a cross section along the lamination direction in which each of the circuit layer 12 and the metal layer 13 is laminated with the ceramic substrate 11.

[0063] As shown in FIG. 2(b), in the peripheral part region A of the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13, an area rate P.sub.A of an active metal compound containing Si and an active metal (Ti in the present embodiment) is 10% or less in a region E.sub.A of 10 ?m from the interface of the active metal nitride layer 21 on the circuit layer 12 (metal layer 13) side (the interface between the active metal nitride layer 21 and the AgCu alloy layer 22) to the circuit layer 12 (metal layer 13) side.

[0064] In addition, as shown in FIG. 2(c), in the central part region B of the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13, an area rate P.sub.B of an active metal compound containing Si and an active metal (Ti in the present embodiment) is 10% or less in a region E.sub.B of 10 ?m from the interface of the active metal nitride layer 21 on the circuit layer 12 (metal layer 13) side (the interface between the active metal nitride layer 21 and the AgCu alloy layer 22) to the circuit layer 12 (metal layer 13) side.

[0065] In addition, in the present embodiment, a ratio P.sub.A/P.sub.B of an area rate P.sub.A of the active metal compound in the peripheral part region A of the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13 to an area rate P.sub.B of the active metal compound in the central part region B of the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13 is in a range of 0.7 or more and 1.4 or less.

[0066] It is noted that examples of the intermetallic compound (an active metal compound) containing Si and an active metal (Ti) include TiSi.sub.2, TiSi, Ti.sub.5Si.sub.4, Ti.sub.5Si.sub.3, and Ti.sub.5Si, and in the present embodiment, Ti.sub.5Si.sub.3 is adopted.

[0067] In addition, in the present embodiment, a thickness t1.sub.A of an active metal nitride layer 21A formed in the peripheral part region A of the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13, and a thickness t1.sub.B of an active metal nitride layer 21B formed in the central part region B of the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13 are in a range of 0.05 ?m or more and 0.8 ?m or less, and it is preferable that a thickness ratio t1.sub.A/t1.sub.B thereof is in a range of 0.7 or more and 1.4 or less. The active metal nitride layer 21 (21A and 21B) is formed by aggregating active metal nitride particles. The average particle size of these particles is 10 nm or more and 100 nm or less.

[0068] It is noted that in the present embodiment, since a bonding material 45 contains Ti as an active metal and the ceramic substrate 11 is composed of silicon nitride, the active metal nitride layer 21 (21A and 21B) is composed of titanium nitride (TiN). That is, the active metal nitride layer 21 (21A and 21B) is formed by aggregating particles of titanium nitride (TiN) having an average particle size of 10 nm or more and 100 nm or less.

[0069] Further, in the present embodiment, it is preferable that a ratio t2.sub.A/t2.sub.B of a thickness t2.sub.A of an AgCu alloy layer 22A formed in the peripheral part region A of the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13, to a thickness t2.sub.B of an AgCu alloy layer 22B formed in the central part region B of the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13 is in a range of 0.7 or more and 1.4 or less.

[0070] In addition, the thickness of the AgCu alloy layer 22 (22A and 22B) is preferably 1 ?m or more and 30 ?m or less.

[0071] Hereinafter, a method for producing the insulating circuit substrate 10 according to the present embodiment will be described with reference to FIG. 3 and FIG. 4.

(Bonding Material Arranging Step S01)

[0072] The copper sheet 42 which is to be the circuit layer 12 and the copper sheet 43 which is to be the metal layer 13 are prepared.

[0073] Then, the bonding material 45 is applied and dried on the bonding surface of the copper sheet 42 which is to be the circuit layer 12 and the bonding surface of the copper sheet 43 which is to be the metal layer 13. The coating thickness of the paste-like bonding material 45 is preferably in a range of 10 ?m or more and 50 ?m or less after drying.

[0074] In the present embodiment, the paste-like bonding material 45 is applied by screen printing.

[0075] The bonding material 45 is a bonding material containing Ag and an active metal (one or more selected from Ti, Zr, Nb, or Hf). In the present embodiment, an AgTi-based brazing material (an AgCuTi-based brazing material) is used as the bonding material 45. As the AgTi-based brazing material (the AgCuTi-based brazing material), it is preferable to use, for example, a brazing material which contains: Cu in an amount of 0% by mass or more and 45% by mass or less; and Ti which is an active metal in an amount of 0.5% by mass or more and 20% by mass or less, with a balance of Ag and inevitable impurities.

[0076] The specific surface area of the Ag powder contained in the bonding material 45 is preferably 0.15 m.sup.2/g or more, more preferably 0.25 m.sup.2/g or more, and still more preferably 0.40 m.sup.2/g or more. On the other hand, the specific surface area of the Ag powder contained in the bonding material 45 is preferably 1.40 m.sup.2/g or less, more preferably 1.00 m.sup.2/g or less, and still more preferably 0.75 m.sup.2/g or less.

[0077] Regarding the particle diameter of the Ag powder contained in the paste-like bonding material 45, it is preferable that D10 is in a range of 0.7 ?m or more and 3.5 ?m or less and D100 is 4.5 ?m or more and 23 ?m or less. D10 is a particle diameter at which the cumulative frequency is 10% on a volume basis in a particle size distribution measured according to a laser diffraction scattering type particle size distribution measuring method, and D100 is a particle diameter at which the cumulative frequency is 100% on a volume basis.

[0078] In a pressurizing and heating step S03 described later, a generated liquid phase is excluded from the central part of the copper sheets 42 and 43 to the peripheral part side by applying a pressure in the lamination direction; and thereby, a relatively large amount of the active metal component is present in the peripheral part of each of the copper sheets 42 and 43.

[0079] Therefore, in the present embodiment, as shown in FIG. 5, the bonding material 45 is applied so that a coating thickness of a bonding material 45A on the peripheral part of each of the copper sheet 42 which is to be the circuit layer 12 and the copper sheet 43 which is to be the metal layer 13 is thinner than a coating thickness of a bonding material 45A on the central part of each of the copper sheet 42 which is to be the circuit layer 12 and the copper sheet 43 which is to be the metal layer 13.

[0080] It is noted that a difference between the coating thickness of a bonding material 45A on the peripheral part of each of the copper sheet 42 which is to be the circuit layer 12 and the copper sheet 43 which is to be the metal layer 13, and the coating thickness of the bonding material 45B in the central part is preferably in a range of 5 ?m or more and 15 ?m or less.

[0081] The peripheral part onto which the bonding material 45A is applied is a peripheral portion which includes a peripheral part region and has an area of 1.5% to 10% of the surface area of each of the copper sheets 42 and 43, where the line width of the peripheral part is at most 1 mm. The central part onto which the bonding material 45B is applied is a central portion which includes a central part region and has an area of 90% to 98.5% of the surface area of each of the copper sheets 42 and 43.

(Laminating Step S02)

[0082] Next, the copper sheet 42 which is to be the circuit layer 12 is laminated on one surface (the upper surface in FIG. 4) of the ceramic substrate 11 while interposing the bonding material 45 therebetween, and concurrently, the copper sheet 43 which is to be the metal layer 13 is laminated on the other surface (the lower surface in FIG. 4) of the ceramic substrate 11 while interposing the bonding material 45 therebetween.

(Pressurizing and Heating Step S03)

[0083] Next, the copper sheet 42, the ceramic substrate 11, and the copper sheet 43 are heated in a pressurized state in a heating furnace in a vacuum atmosphere, and the bonding material 45 is melted.

[0084] The heating temperature in the pressurizing and heating step S03 is preferably set to be in a range of 800? C. or higher and 850? C. or lower. It is preferable that the total of the temperature integral values in the temperature raising step from 780? C. to the heating temperature and the holding step at the heating temperature is set to be in a range of 7? C..Math.h or more and 120? C..Math.h or less.

[0085] In addition, the pressurization load in the pressurizing and heating step S03 is preferably set to be in a range of 0.029 MPa or more and 2.94 MPa or less.

[0086] Further, the degree of vacuum in the pressurizing and heating step S03 is preferably set to be in a range of 1?10.sup.?6 Pa or more and 5?10.sup.?2 Pa or less.

(Cooling Step S04)

[0087] Then, after the pressurizing and heating step S03, cooling is carried out to solidify the molten bonding material 45; and thereby, the copper sheet 42 which is to be the circuit layer 12 is bonded to the ceramic substrate 11, and the copper sheet 43 which is to be the metal layer 13 is bonded to the ceramic substrate 11.

[0088] It is noted that the cooling rate in the cooling step S04 is preferably set to be in a range of 2? C./min or more and 20? C./min or less. It is noted that the cooling rate is a cooling rate from the heating temperature to 780? C., which is an AgCu eutectic temperature.

[0089] As described above, the insulating circuit substrate 10 which is the present embodiment is produced by the bonding material arranging step S01, the laminating step S02, the pressurizing and heating step S03, and the cooling step S04.

(Heat Sink Bonding Step S05)

[0090] Next, the heat sink 5 is bonded to the other surface side of the metal layer 13 of the insulating circuit substrate 10.

[0091] The insulating circuit substrate 10 and the heat sink 5 are laminated with a solder material being interposed therebetween and charged into a heating furnace, and the insulating circuit substrate 10 and the heat sink 5 are subjected to solder bonding with the solder layer 7 being interposed therebetween.

(Semiconductor Element-Bonding Step S06)

[0092] Next, the semiconductor element 3 is bonded by soldering to one surface of the circuit layer 12 of the insulating circuit substrate 10.

[0093] The power module 1 shown in FIG. 1 is produced by the above-described steps.

[0094] According to the insulating circuit substrate 10 (copper/ceramic assembly) according to the present embodiment which has the above-described configuration, in the peripheral part region A of the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13, an area rate P.sub.A of an active metal compound containing Si and an active metal (Ti in the present embodiment) is 10% or less in a region E.sub.A extending by 10 ?m from the interface of the active metal nitride layer 21 on the circuit layer 12 (metal layer 13) side (the interface between the active metal nitride layer 21 and the AgCu alloy layer 22) toward the circuit layer 12 (metal layer 13) side, and concurrently, in the central part region B of the bonded interface between the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13, an area rate P.sub.B of an active metal compound containing Si and an active metal (Ti in the present embodiment) is 10% or less in a region E.sub.B extending by 10 ?m from the interface of the active metal nitride layer 21 on the circuit layer 12 (metal layer 13) side (the interface between the active metal nitride layer 21 and the AgCu alloy layer 22) toward the circuit layer 12 (metal layer 13) side. Thereby, the unnecessary hardening of the bonded interface between the ceramic substrate 11 and the circuit layer 12 and the bonded interface between the ceramic substrate and the metal layer 13 is prevented.

[0095] It is noted that in order to further suppress the unnecessary hardening of the bonded interface between the ceramic substrate 11 and the circuit layer 12 and the bonded interface between the ceramic substrate 11 and the metal layer 13, the above-described area rates P.sub.A and P.sub.B of the active metal compound are preferably 8% or less, more preferably 7% or less, and still more preferably 5% or less. In addition, the area rates P.sub.A and P.sub.B of the active metal compound are preferably 1.5% or more, more preferably 2% or more, and still more preferably 3% or more.

[0096] In addition, a ratio P.sub.A/P.sub.B of an area rate P.sub.A of the active metal compound in a peripheral part region A of each of the circuit layer 12 and the metal layer 13 to an area rate P.sub.B of the active metal compound in a central part region B of each of the circuit layer 12 and the metal layer 13 is in a range of 0.7 or more and 1.4 or less. Thereby, there is no significant difference in hardness between the peripheral part region A of each of the circuit layer 12 and the metal layer 13, and the central part region B of each of the circuit layer 12 and the metal layer 13, it is possible to suppress the occurrence of breaking in the ceramic substrate 11 during loading of a thermal cycle, and the thermal cycle reliability is excellent.

[0097] It is noted that in order to further improve the thermal cycle reliability, a ratio P.sub.A/P.sub.B of an area rate P.sub.A of the active metal compound in a peripheral part region A of each of the circuit layer 12 and the metal layer 13 to an area rate P.sub.B of the active metal compound in a central part region B of each of the circuit layer 12 and the metal layer 13 is preferably in a range of 0.8 or more and 1.2 or less and more preferably in a range of 0.9 or more and 1.1 or less.

[0098] In addition, in the present embodiment, in a case where a thickness t1.sub.A of an active metal nitride layer 21A formed in the peripheral part region A of each of the circuit layer 12 and the metal layer 13, and a thickness t1.sub.B of an active metal nitride layer 21B formed in the central part region B of each of the circuit layer 12 and the metal layer 13 are in a range of 0.05 ?m or more and 0.8 ?m or less, each of the circuit layer 12 and the metal layer 13 is bonded to the ceramic substrate 11 by the active metal reliably and firmly, and concurrently, the hardening of the bonded interface is further suppressed.

[0099] It is noted that in order to more firmly bond the circuit layer 12 and the metal layer 13 to the ceramic substrate 11, a thickness t1.sub.A of an active metal nitride layer 21A formed in the peripheral part region A of each of the circuit layer 12 and the metal layer 13, and a thickness t1.sub.B of an active metal nitride layer 21B formed in the central part region B of each of the circuit layer 12 and the metal layer 13 are preferably 0.08 ?m or more and more preferably 0.15 ?m or more.

[0100] In addition, in order to further suppress the unnecessary hardening of the bonded interface, a thickness t1.sub.A of an active metal nitride layer 21A formed in the peripheral part region A of each of the circuit layer 12 and the metal layer 13, and a thickness t1.sub.B of an active metal nitride layer 21B formed in the central part region B of each of the circuit layer 12 and the metal layer 13 are preferably 0.6 am or less and more preferably 0.4 m or less.

[0101] Further, in the present embodiment, in a case where a ratio t1.sub.A/t1.sub.B of a thickness t1.sub.A of an active metal nitride layer 21A formed in the peripheral part region A of each of the circuit layer 12 and the metal layer 13, to a thickness t1.sub.B of an active metal nitride layer 21B formed in the central part region B of each of the circuit layer 12 and the metal layer 13 is in a range of 0.7 or more and 1.4 or less, there is no significant difference in the hardness of the bonded interface in the peripheral part region A and the central part region B of each of the circuit layer 12 and the metal layer 13, and it is possible to further suppress the occurrence of breaking in the ceramic substrate 11 during loading of a thermal cycle.

[0102] It is noted that in order to further suppress the occurrence of breaking in the ceramic substrate 11 during loading of a thermal cycle, a ratio t1.sub.A/t1.sub.B of a thickness t1.sub.A of an active metal nitride layer 21A formed in the peripheral part region A of each of the circuit layer 12 and the metal layer 13, to a thickness t1.sub.B of an active metal nitride layer 21B formed in the central part region B of each of the circuit layer 12 and the metal layer 13 is preferably in a range of 0.8 or more and 1.2 or less and more preferably in a range of 0.9 or more and 1.1 or less.

[0103] In addition, in the present embodiment, in a case where the thickness t2.sub.A of the AgCu alloy layer 22A formed in the peripheral part region A of each of the circuit layer 12 and the metal layer 13, and the thickness t2.sub.B of the AgCu alloy layer 22B formed in the central part region B of each of the circuit layer 12 and the metal layer 13 are in a range of 1 ?m or more and 30 ?m or less, Ag of the bonding material 45 described later is sufficiently reacted with each of the circuit layer 12 and the metal layer 13, the ceramic substrate 11 and each of the circuit layer 12 and the metal layer 13 are reliably and firmly bonded to each other, and concurrently, the hardening of the bonded interface is suppressed.

[0104] It is noted that in order to more firmly bond the circuit layer 12 and the metal layer 13 to the ceramic substrate 11, the thickness t2.sub.A of the AgCu alloy layer 22A formed in the peripheral part region A of each of the circuit layer 12 and the metal layer 13, and the thickness t2.sub.B of the AgCu alloy layer 22B formed in the central part region B of each of the circuit layer 12 and the metal layer 13 are preferably 3 ?m or more and more preferably 5 ?m or more.

[0105] In addition, in order to further suppress the unnecessary hardening of the bonded interface, the thickness t2.sub.A of the AgCu alloy layer 22A formed in the peripheral part region A of each of the circuit layer 12 and the metal layer 13, and the thickness t2.sub.B of the AgCu alloy layer 22B formed in the central part region B of each of the circuit layer 12 and the metal layer 13 are preferably 25 Lm or less and more preferably 15 ?m or less.

[0106] Further, in the present embodiment, in a case where the ratio t2.sub.A/t2.sub.B of the thickness t2.sub.A of the AgCu alloy layer 22A formed in the peripheral part region A of each of the circuit layer 12 and the metal layer 13, to the thickness t2.sub.B of the AgCu alloy layer 22B formed in the central part region B of each of the circuit layer 12 and the metal layer 13 is in a range of 0.7 or more and 1.4 or less, there is no significant difference in the hardness of the bonded interface in the peripheral part region A and the central part region B of each of the circuit layer 12 and the metal layer 13, and it is possible to further suppress the occurrence of breaking in the ceramic substrate during loading of a thermal cycle.

[0107] It is noted that in order to further suppress the occurrence of breaking in the ceramic substrate 11 during loading of a thermal cycle, the ratio t2.sub.A/t2.sub.B of the thickness t2.sub.A of the AgCu alloy layer 22A formed in the peripheral part region A of each of the circuit layer 12 and the metal layer 13, to the thickness t2n of the AgCu alloy layer 22B formed in the central part region B of each of the circuit layer 12 and the metal layer 13 is preferably in a range of 0.8 or more and 1.2 or less and more preferably in a range of 0.9 or more and 1.1 or less.

[0108] Although the embodiments of the present invention were described above, the present invention is not limited thereto, and appropriate modification is possible in a range not departing from the technical features of the invention.

[0109] For example, the present embodiment has been described such that a semiconductor element is mounted on an insulating circuit substrate to constitute a power module; however, the present embodiment is not limited thereto. For example, an LED element may be mounted on a circuit layer of an insulating circuit substrate to constitute an LED module, or a thermoelectric element may be mounted on a circuit layer of an insulating circuit substrate to constitute a thermoelectric module.

[0110] Further, in the present embodiment, the description has been made using Ti as an example of the active metal contained in the bonding material. However, the present embodiment is not limited thereto, and any one or two or more active metals selected from Ti, Zr, Hf, and Nb may be contained. It is noted that these active metals may be contained as hydrides.

[0111] In addition, in the present embodiment, the description has been made such that the area rate P.sub.A of the active metal compound in the peripheral part region of each of the circuit layer and the metal layer and the area rate P.sub.B of the active metal compound in the central part region of each of the circuit layer and the metal layer are controlled by adjusting the coating thickness of the bonding material in each of the peripheral part and the central part of the copper sheet. However, the present invention is not limited thereto, and the area rate P.sub.A of the active metal compound in the peripheral part region of each of the circuit layer and the metal layer and the area rate P.sub.B of the active metal compound in the central part region of each of the circuit layer and the metal layer may be controlled by using a different bonding material to be applied onto each of the peripheral part and the central part of the copper sheet.

[0112] For example, it is possible to control the above-described area rates P.sub.A and P.sub.B of the active metal compound by adjusting the specific surface area (BET value) of the Ag powder contained in the bonding material. That is, in a case where the specific surface area of the Ag powder is small, the sinterability of the paste-like bonding material increases, a liquid phase is easily generated in the pressurizing and heating step, the diffusion of the active metal is accelerated, and the area rate of the active metal compound described above becomes high. On the other hand, in a case where the specific surface area of the Ag powder is large, the sinterability of the paste-like bonding material decreases, a liquid phase is difficult to be generated in the pressurizing and heating step, the diffusion of the active metal is suppressed, and the area rate of the active metal compound described above becomes low.

[0113] In addition, bonding materials containing active metals of which kinds or amounts are different from each other may be used to be separately coated on the peripheral part and the central part of the copper sheet.

[0114] Further, in the present embodiment, the description has been made such that the circuit layer is formed by bonding a rolled sheet of oxygen-free copper to the ceramic substrate. However, the present invention is not limited thereto, and the circuit layer may be formed by bonding copper pieces which are obtained by punching a copper sheet to the ceramic substrate in a state where the copper pieces are disposed in a circuit pattern. In this case, it is sufficient that each of the copper pieces has such an interface structure as described above between the copper piece and the ceramic substrate.

[0115] In addition, in the present embodiment, the description has been made such that the bonding material is arranged on the bonding surface of the copper sheet. However, the present invention is not limited thereto, and it is sufficient that the bonding material is arranged between the ceramic substrate and the copper sheet, and the bonding material may be arranged on the bonding surface of the ceramic substrate.

Examples

[0116] Hereinafter, a description will be given for the results of confirmatory experiments carried out to confirm the effectiveness of the present invention.

[0117] First, a ceramic substrate (40 mm?40 mm, thickness: 0.32 mm) consisting of silicon nitride (Si.sub.3N.sub.4) was prepared.

[0118] In addition, as the copper sheet which was to be a circuit layer, a copper sheet consisting of oxygen-free copper and having a size of 37 mm?37 mm and a thickness of 0.8 mm were prepared. Further, as the copper sheet which was to be a metal layer, a copper sheet consisting of oxygen-free copper and having a size of 37 mm?37 mm and a thickness of 0.8 mm was prepared.

[0119] A bonding material containing an Ag powder having a BET value shown in Table 1 was applied onto the peripheral part of the copper sheet which was to be each of a circuit layer and a metal layer so that the target thickness after drying was the value shown in Table 1.

[0120] In addition, a bonding material containing an Ag powder having a BET value shown in Table 1 was applied onto the central part of the copper sheet which was to be each of a circuit layer and a metal layer so that the target thickness after drying was the value shown in Table 1.

[0121] It is noted that a paste material was used as the bonding material, and the amounts of Ag, Cu, and the active metal were as shown in Table 1.

[0122] In addition, vacuum degassing was carried out as a pretreatment by heating at 150? C. for 30 minutes, and the BET value (specific surface area) of the Ag powder was measured using AUTOSORB-1 manufactured by QUANTACHROME Corporation by a BET multipoint method under the conditions of N.sub.2 adsorption and liquid nitrogen of 77 K.

[0123] A copper sheet which was to be a circuit layer was laminated on one surface of the ceramic substrate. In addition, a copper sheet which was to be a metal layer was laminated on the other surface of the ceramic substrate.

[0124] This laminate was heated in a state of being pressurized in the lamination direction to generate an AgCu liquid phase. In this case, the pressurization load was set to 0.294 MPa, and the temperature integral value was as shown in Table 2.

[0125] Then, the heated laminate was cooled to bond the copper sheet which was to be the circuit layer, the ceramic substrate, and the metal sheet which was to be the metal layer to each other; and thereby, an insulating circuit substrate (copper/ceramic assembly) was obtained.

[0126] Regarding the obtained insulating circuit substrate (copper/ceramic assembly), the area rate of the active metal compound, the active metal nitride layer, the AgCu alloy layer, and the thermal cycle reliability were evaluated as follows.

(Area Rate of Active Metal Compound)

[0127] A cross section of the bonded interface between the ceramic substrate and each of the circuit layer and the metal layer was observed with an EPMA device, and an element map (width 50 ?m?height 30 ?m) of the active metal and Si in the peripheral part region and the central part region of each of the circuit layer and the metal layer was acquired for five visual fields.

[0128] Then, as shown in FIG. 6, in a region from the active metal nitride layer to 10 ?m toward the circuit layer (metal layer) surface, a portion where Si and the active metal overlapped was regarded as an area of the active metal compound containing Si and the active metal, and the area rate of the active metal compound was calculated. The area rate was a value in a case where an area of 50 km?10 ?m was set to 100%. It is noted that Table 2 shows the average values from both the five visual fields, that is, a total of ten visual fields.

(Active Metal Nitride Layer)

[0129] A cross section of the bonded interface between the ceramic substrate and each of the circuit layer and the metal layer was subjected to measurement at a magnification of 30000 times using an electron scanning microscope (ULTRA55 manufactured by Carl Zeiss NTS, LLC, acceleration voltage: 1.8 kV), and element mapping of N and the active metal element was carried out to acquire the element maps thereof for both the five visual fields according to the energy dispersive X-ray analysis method. It was determined that the active metal nitride layer was present in a case where the active metal element and N were present in the same region.

[0130] The observation was carried out in both the five visual fields, that is, a total of ten visual fields, and the average value obtained by dividing the area in which the active metal element and N were present in the same region by the measured width was defined as the thickness of the active metal nitride layer.

(AgCu Alloy Layer)

[0131] In cross sections of the bonded interface between the circuit layer and the ceramic substrate and the bonded interface between the ceramic substrate and the metal layer, element mapping of Ag, Cu, and the active metal was carried out to acquire the element maps thereof by using an EPMA device. Element mapping was carried out to acquire the element map of each element in both the five visual fields.

[0132] Then, a region in which the Ag concentration was 15% by mass or more was defined as the AgCu alloy layer in a case where Ag+Cu+active metal was set to 100% by mass, and an area thereof was measured to determine a value obtained by dividing the area by a width of the measurement region (area/width of measurement region). The average of the values is shown in Table 2 as the thickness of the AgCu alloy layer.

(Thermal Cycle Reliability) The above-described insulating circuit substrate was loaded with a thermal cycle of 40? C.?5 min< >150? C.?5 min, an SAT examination (ultrasonic examination) was carried out every 100 cycles up to 2000 cycles to check the presence or absence of ceramic breaking, and the number of cycles leading to ceramic breaking was evaluated. The evaluation results are shown in Table 2.

TABLE-US-00001 TABLE 1 Bonding material in Bonding material in peripheral part of copper sheet central part of copper sheet BET Coat- BET Coat- Active value ing Active value ing Cu element of Ag thick- Cu element of Ag thick- mass mass powder ness mass mass powder ness Ag % Element % m.sup.2/g ?m Ag % Element % m.sup.2/g ?m Invention 1 Balance Ti 2.1 0.56 35 Balance 24.5 Ti 3.5 1.03 45 Example 2 Balance 42.7 Ti 0.8 0.16 10 Balance Ti 8.3 15.00 25 3 Balance Ti 2.3 1.03 20 Balance Zr 5.7 0.56 30 4 Balance Zr 1.5 0.16 10 Balance Zr 5.7 1.03 15 5 Balance 29.0 Nb 1.0 0.22 15 Balance Ti 4.5 0.56 30 6 Balance Hf 4.5 1.38 10 Balance Hf 4.5 1.38 25 7 Balance Zr 2.6 0.56 10 Balance 26.5 Zr 2.5 0.22 30 8 Balance 34.5 Ti 0.5 0.22 15 Balance 26.5 Ti 1.5 0.22 35 Comparative 1 Balance Zr 5.7 0.44 35 Balance Zr 5.7 0.16 45 Example 2 Balance Zr 3.3 0.16 15 Balance Zr 5.7 1.38 45 3 Balance 34.5 Ti 2.5 0.56 40 Balance Ti 4.5 1.03 35

TABLE-US-00002 TABLE 2 Pressurizing Active Active Thermal and heating metal compound metal nitride layer AgCu alloy layer cycle step Area rate (%) Thickness (?m) Thickness (?m) reliability Temperature Peripheral Central Peripheral Central Peripheral Central Breaking integral part part part part part part occurrence value region region P.sub.A/ region region t1.sub.A/ region region t2.sub.A/ (number ? C. .Math. h P.sub.A P.sub.B P.sub.B t1.sub.A t1.sub.B t1.sub.B t2.sub.A t2.sub.B t2.sub.B of cycles) Invention 1 119.4 10 8 1.3 0.79 0.67 1.18 28 22 1.27 1600th Example 2 21.5 2 3 0.7 0.13 0.17 0.76 8 10 0.80 1600th 3 96.0 8 6 1.4 0.62 0.45 1.38 18 13 1.38 1500th 4 7.5 2 2 0.9 0.07 0.09 0.75 3 4 0.75 1800th 5 98.7 8 6 1.2 0.44 0.41 1.08 11 9 1.22 1900th 6 32.5 4 3 1.1 0.30 0.29 1.03 13 12 1.08 >2000th 7 61.2 6 6 0.9 0.39 0.43 0.91 5 7 0.71 2000th 8 18.4 3 3 1.1 0.25 0.23 1.09 17 16 1.06 >2000th Comparative 1 148.2 15 13 1.1 1.19 1.16 1.02 24 20 1.20 1100th Example 2 59.7 6 9 0.6 0.47 0.59 0.79 14 18 0.78 1300th 3 51.4 8 5 1.5 0.53 0.34 1.53 21 13 1.62 1200th

[0133] In Comparative Example 1, in a region extending by 10 ?m from the active metal nitride layer toward a side of the copper sheet, an area rate of an active metal compound containing Si and an active metal was more than 10%, and in the thermal cycle test, the number of cycles leading to breaking occurrence was 1100 cycles.

[0134] In Comparative Example 2, a ratio P.sub.A/P.sub.B of an area rate P.sub.A of the active metal compound in a peripheral part region of the copper sheet to an area rate P.sub.B of the active metal compound in a central part region of the copper sheet was 0.6, and in the thermal cycle test, the number of cycles leading to breaking occurrence was 1300 cycles.

[0135] In Comparative Example 3, a ratio P.sub.A/P.sub.B of an area rate P.sub.A of the active metal compound in a peripheral part region of the copper sheet to an area rate P.sub.B of the active metal compound in a central part region of the copper sheet was 1.5, and in the thermal cycle test, the number of cycles leading to breaking occurrence was 1200 cycles.

[0136] On the other hand, in Invention Examples 1 to 8, in a region extending by 10 ?m from the active metal nitride layer toward a side of the copper sheet, an area rate of an active metal compound containing Si and an active metal was 10% or less, and concurrently, a ratio P.sub.A/P.sub.B of an area rate P.sub.A of the active metal compound in a peripheral part region of the copper sheet to an area rate P.sub.B of the active metal compound in a central part region of the copper sheet was 0.7 or more and 1.4 or less, and in the thermal cycle test, the number of cycles leading to breaking occurrence was 1500 to more than 2000 cycles, and the thermal cycle reliability was excellent.

[0137] From the results of the above-described checking experiments, according to Invention Examples, it has been confirmed that it is possible to provide an insulating circuit substrate (a copper/ceramic assembly) having an excellent thermal cycle reliability, which can suppress the occurrence of breaking in a ceramic member even in a case where a severe thermal cycle is loaded.

INDUSTRIAL APPLICABILITY

[0138] The copper/ceramic assembly and the insulating circuit substrate according to the present embodiment are suitably applied to power modules, LED modules, and thermoelectric modules.

REFERENCE SIGNS LIST

[0139] 10: Insulating circuit substrate (copper/ceramic assembly) [0140] 11: Ceramic substrate (ceramic member) [0141] 12: Circuit layer (copper member) [0142] 13: Metal layer (copper member) [0143] 21 (21A, 21B): Active metal nitride layer [0144] 22 (22A, 22B): AgCu alloy layer