WINDOW-BASED ENVELOPE TRACKING IN A MULTI-ANTENNA TRANSMISSION CIRCUIT

Abstract

Window-based envelope tracking in a multi-antenna transmission circuit is provided. The multi-antenna transmission circuit includes a power amplifier circuit that amplifies multiple radio frequency (RF) signals concurrently based on a modulated voltage, an envelope tracking integrated circuit (ETIC) that generates the modulated voltage based on a modulated target voltage, and a transceiver circuit that generates the RF signals and the modulated target voltage. The RF signals may be modulated across a wide modulation bandwidth, but the ETIC may have a lower bandwidth limit. Such bandwidth disparity can cause a ripple(s) in the modulated voltage and, consequently, lead to distortions in the RF signals. Herein, the transceiver circuit is configured to perform window-based envelope tracking to thereby determine and add a compensation term(s) in the modulated target voltage. As a result, it is possible to suppress the ripple(s) and prevent distortions in the RF signals across the wide modulation bandwidth.

Claims

1. A multi-antenna transmission circuit comprising: a power amplifier circuit configured to amplify a plurality of radio frequency (RF) signals each having a respective one of a plurality of time-variant power envelopes based on a modulated voltage; an envelope tracking integrated circuit (ETIC) configured to generate the modulated voltage based on a modulated target voltage; and a transceiver circuit comprising: a signal processing circuit configured to generate the plurality of RF signals from a time-variant digital input vector; an envelope detector circuit configured to generate a plurality of time-variant amplitude envelopes based on the time-variant digital input vector to each correspond to a respective one of the plurality of time-variant power envelopes; and a target voltage circuit configured to generate the modulated target voltage based on a selected time-variant amplitude envelope among the plurality of time-variant amplitude envelopes.

2. The multi-antenna transmission circuit of claim 1, further comprising an antenna circuit configured to emit the plurality of RF signals simultaneously to thereby form an RF beam.

3. The multi-antenna transmission circuit of claim 1, wherein the envelope detector circuit comprises: an amplitude detector circuit configured to detect a time-variant amplitude of the time-variant digital input vector; and a plurality of scaler circuits each configured to scale the detected time-variant amplitude based on a respective one of a plurality of scaling factors to generate a respective one of the plurality of time-variant amplitude envelopes.

4. The multi-antenna transmission circuit of claim 1, wherein the target voltage circuit comprises: a voltage processing circuit configured to generate a digital target voltage based on the selected time-variant amplitude envelope among the plurality of time-variant amplitude envelopes; a current processing circuit configured to generate a digital compensation term based on the plurality of time-variant amplitude envelopes; a combiner circuit configured to add the digital compensation term into the digital target voltage; and a digital-to-analog converter (DAC) configured to convert the digital target voltage into the modulated target voltage.

5. The multi-antenna transmission circuit of claim 4, wherein the voltage processing circuit comprises: a multiplexer configured to output a maximum one of the plurality of time-variant amplitude envelopes as the selected time-variant amplitude envelope; a windowed peak detector circuit configured to detect a set of peak amplitudes of the selected time-variant amplitude envelope; a lookup table (LUT) circuit configured to generate the digital target voltage based on the set of peak amplitudes; a current estimator configured to estimate a load current in the power amplifier circuit that is a function of the modulated voltage; an equalizer configured to generate a load current compensation term to suppress a ripple in the modulated voltage that is caused by the estimated load current; and a combiner configured to add the load current compensation term to the digital target voltage.

6. The multi-antenna transmission circuit of claim 5, wherein the windowed peak detector circuit is further configured to: take one or more highest amplitude samples in each of a plurality of sampling windows based on a modulation bandwidth of the plurality of RF signals and a defined threshold; and generate the set of peak amplitudes comprising the one or more highest amplitude samples taken in each of the plurality of sampling windows.

7. The multi-antenna transmission circuit of claim 6, wherein the windowed peak detector circuit is further configured to: take a peak amplitude sample in each of the plurality of sampling windows when the modulation bandwidth is below the defined threshold; and generate the set of peak amplitudes comprising the peak amplitude sample taken in each of the plurality of sampling windows.

8. The multi-antenna transmission circuit of claim 6, wherein the windowed peak detector circuit is further configured to: take a plurality of highest amplitude samples in each of the plurality of sampling windows when the modulation bandwidth is above or equal to the defined threshold; and generate the set of peak amplitudes comprising the plurality of highest amplitude samples taken in each of the plurality of sampling windows.

9. The multi-antenna transmission circuit of claim 4, wherein the current processing circuit comprises: a plurality of current lookup table (LUT) circuits configured to generate a plurality of digital current terms each corresponding to a respective one of the plurality of time-variant amplitude envelopes; a summing circuit configured to sum up the plurality of digital current terms to generate a time-variant digital current term; and a filter circuit configured to generate the digital compensation term based on the time-variant digital current term to compensate for a ripple in the modulated voltage that is a function of a total inductive impedance presented at the power amplifier circuit.

10. The multi-antenna transmission circuit of claim 1, wherein the signal processing circuit comprises: a modulator circuit configured to generate a modulated RF signal from the time-variant digital input vector; and a beamformer circuit configured to preprocess the modulated RF signal based on a beamforming codeword to generate the plurality of RF signals.

11. The multi-antenna transmission circuit of claim 1, wherein the target voltage circuit comprises: a plurality of digital-to-analog converters (DACs) each configured to convert a respective one of the plurality of time-variant amplitude envelopes into a respective one of a plurality of analog amplitude envelopes; a voltage processing circuit configured to generate an analog target voltage based on the plurality of analog amplitude envelopes; a current processing circuit configured to generate an analog compensation term based on the plurality of analog amplitude envelopes; and a combiner circuit configured to add the analog compensation term into the analog target voltage.

12. A wireless device comprising: a multi-antenna transmission circuit comprising: a power amplifier circuit configured to amplify a plurality of radio frequency (RF) signals each having a respective one of a plurality of time-variant power envelopes based on a modulated voltage; an envelope tracking integrated circuit (ETIC) configured to generate the modulated voltage based on a modulated target voltage; and a transceiver circuit comprising: a signal processing circuit configured to generate the plurality of RF signals from a time-variant digital input vector; an envelope detector circuit configured to generate a plurality of time-variant amplitude envelopes based on the time-variant digital input vector to each correspond to a respective one of the plurality of time-variant power envelopes; and a target voltage circuit configured to generate the modulated target voltage based on a selected time-variant amplitude envelope among the plurality of time-variant amplitude envelopes.

13. The wireless device of claim 12, wherein the envelope detector circuit comprises: an amplitude detector circuit configured to detect a time-variant amplitude of the time-variant digital input vector; and a plurality of scaler circuits each configured to scale the detected time-variant amplitude based on a respective one of a plurality of scaling factors to generate a respective one of the plurality of time-variant amplitude envelopes.

14. The wireless device of claim 12, wherein the target voltage circuit comprises: a voltage processing circuit configured to generate a digital target voltage based on the selected time-variant amplitude envelope among the plurality of time-variant amplitude envelopes; a current processing circuit configured to generate a digital compensation term based on the plurality of time-variant amplitude envelopes; a combiner circuit configured to add the digital compensation term into the digital target voltage; and a digital-to-analog converter (DAC) configured to convert the digital target voltage into the modulated target voltage.

15. The wireless device of claim 14, wherein the voltage processing circuit comprises: a multiplexer configured to output a maximum one of the plurality of time-variant amplitude envelopes as the selected time-variant amplitude envelope; a windowed peak detector circuit configured to detect a set of peak amplitudes of the selected time-variant amplitude envelope; a lookup table (LUT) circuit configured to generate the digital target voltage based on the set of peak amplitudes; a current estimator configured to estimate a load current in the power amplifier circuit that is a function of the modulated voltage; an equalizer configured to generate a load current compensation term to suppress a ripple in the modulated voltage that is caused by the estimated load current; and a combiner configured to add the load current compensation term to the digital target voltage.

16. The wireless device of claim 15, wherein the windowed peak detector circuit is further configured to: take one or more highest amplitude samples in each of a plurality of sampling windows based on a modulation bandwidth of the plurality of RF signals and a defined threshold; and generate the set of peak amplitudes comprising the one or more highest amplitude samples taken in each of the plurality of sampling windows.

17. The wireless device of claim 16, wherein the windowed peak detector circuit is further configured to: take a peak amplitude sample in each of the plurality of sampling windows when the modulation bandwidth is below the defined threshold; and generate the set of peak amplitudes comprising the peak amplitude sample taken in each of the plurality of sampling windows.

18. The wireless device of claim 16, wherein the windowed peak detector circuit is further configured to: take a plurality of highest amplitude samples in each of the plurality of sampling windows when the modulation bandwidth is above or equal to the defined threshold; and generate the set of peak amplitudes comprising the plurality of highest amplitude samples taken in each of the plurality of sampling windows.

19. The wireless device of claim 14, wherein the current processing circuit comprises: a plurality of current lookup table (LUT) circuits configured to generate a plurality of digital current terms each corresponding to a respective one of the plurality of time-variant amplitude envelopes; a summing circuit configured to sum up the plurality of digital current terms to generate a time-variant digital current term; and a filter circuit configured to generate the digital compensation term based on the time-variant digital current term to compensate for a ripple in the modulated voltage that is a function of a total inductive impedance presented at the power amplifier circuit.

20. The wireless device of claim 12, wherein the target voltage circuit comprises: a plurality of digital-to-analog converters (DACs) each configured to convert a respective one of the plurality of time-variant amplitude envelopes into a respective one of a plurality of analog amplitude envelopes; a voltage processing circuit configured to generate an analog target voltage based on the plurality of analog amplitude envelopes; a current processing circuit configured to generate an analog compensation term based on the plurality of analog amplitude envelopes; and a combiner circuit configured to add the analog compensation term into the analog target voltage.

21. A method for performing window-based envelope tracking in a multi-antenna transmission circuit comprising: amplifying a plurality of radio frequency (RF) signals each having a respective one of a plurality of time-variant power envelopes based on a modulated voltage; generating the modulated voltage based on a modulated target voltage; generating the plurality of RF signals from a time-variant digital input vector; generating a plurality of time-variant amplitude envelopes based on the time-variant digital input vector to each correspond to a respective one of the plurality of time-variant power envelopes; and generating the modulated target voltage based on a selected time-variant amplitude envelope among the plurality of time-variant amplitude envelopes.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0011] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] FIG. 1 is a schematic diagram of an exemplary multi-antenna transmission circuit wherein a transceiver circuit is configured according to embodiments of the present disclosure to perform window-based envelope tracking to suppress a ripple(s) in a modulated voltage received by a power amplifier circuit;

[0013] FIG. 2 is a schematic diagram providing an exemplary illustration of an output stage of a power amplifier in the power amplifier circuit in FIG. 1;

[0014] FIG. 3 is a schematic diagram of an exemplary signal processing circuit in the transceiver circuit in FIG. 1;

[0015] FIG. 4 is a schematic diagram of an exemplary envelope detector circuit in the transceiver circuit in FIG. 1;

[0016] FIG. 5 is a schematic diagram of an exemplary voltage processing circuit in the transceiver circuit in FIG. 1;

[0017] FIGS. 6A and 6B are graphic diagrams providing exemplary illustrations of the window-based envelope tracking as performed by the transceiver circuit in FIG. 1;

[0018] FIG. 7 is a schematic diagram of an exemplary current processing circuit in the transceiver circuit in FIG. 1;

[0019] FIG. 8 is a schematic diagram of an exemplary multi-antenna transmission circuit configured according to an alternative embodiment of the present disclosure;

[0020] FIG. 9 is a schematic diagram of an exemplary user element wherein the multi-antenna transmission circuits of FIGS. 1 and 8 can be provided; and

[0021] FIG. 10 is a flowchart of an exemplary process for performing window-based envelope tracking in the multi-antenna transmission circuit of FIG. 1 and the multi-antenna transmission circuit of FIG. 8.

DETAILED DESCRIPTION

[0022] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0023] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

[0024] It will be understood that when an element such as a layer, region, or substrate is referred to as being on or extending onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or extending directly onto another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being over or extending over another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over or extending directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.

[0025] Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0028] Embodiments of the disclosure relate to window-based envelope tracking in a multi-antenna transmission circuit. The multi-antenna transmission circuit includes a power amplifier circuit that amplifies multiple radio frequency (RF) signals concurrently based on a modulated voltage, an envelope tracking integrated circuit (ETIC) that generates the modulated voltage based on a modulated target voltage, and a transceiver circuit that generates the RF signals and the modulated target voltage. In a non-limiting example, the RF signals can be preprocessed based on a codeword and emitted simultaneously from multiple antennas to form an RF beam. The RF signals may be modulated across a wide modulation bandwidth (e.g., >200 MHz). However, the ETIC may have a bandwidth limit lower than the modulation bandwidth of the RF signals. Such bandwidth disparity can cause a ripple(s) in the modulated voltage and, consequently, lead to distortions in the RF signals. Herein, the transceiver circuit is configured to perform window-based envelope tracking on the RF signals to thereby determine and add a compensation term(s) (digital or analog) in the modulated target voltage. As a result, it is possible to suppress the ripple(s) and prevent distortions in the RF signals across the wide modulation bandwidth.

[0029] FIG. 1 is a schematic diagram of an exemplary multi-antenna transmission circuit 10 wherein a transceiver circuit 12 is configured according to embodiments of the present disclosure to perform window-based envelope tracking to suppress a ripple(s) in a modulated voltage V.sub.CC received by a power amplifier circuit 14. Herein, the multi-antenna transmission circuit 10 also includes an ETIC 16 and an antenna circuit 18.

[0030] The power amplifier circuit 14 includes multiple power amplifiers 20(1)-20(X) and the antenna circuit 18 includes multiple antennas 22(1)-22(X). Each of the power amplifiers 20(1)-20(X) is configured to amplify a respective one of multiple RF signals 24(1)-24(X), each of which is associated with a respective one of multiple time-variant power envelopes P.sub.IN-1-P.sub.IN-X, based on the modulated voltage V.sub.CC and provide the respective one of the RF signals 24(1)-24(X) to a respective one of the antennas 22(1)-22(X). The antennas 22(1)-22(X) are configured to simultaneously radiate the amplified RF signals 24(1)-24(X) in one or more polarizations (e.g., horizontal and/or vertical). In context of the present disclosure, the RF signals 24(1)-24(X) are preprocessed based on a beamforming codeword(s) to ensure that the antennas 22(1)-22(X) can radiate the RF signals 24(1)-24(X) in an RF beam.

[0031] The ETIC 16 is coupled to the power amplifier circuit 14 via a conductive path 26 and configured to generate the modulated voltage V.sub.CC based on a modulated target voltage V.sub.TGT. The transceiver circuit 12 is configured to generate the modulated target voltage V.sub.TGT and provide the modulated target voltage V.sub.TGT to the ETIC 16.

[0032] Notably, the ETIC 16 can be associated with an inductive ETIC impedance L.sub.ETIC and the conductive path 26 can be associated with an inductive trace impedance L.sub.TRACE. As such, the ETIC 16 and the conductive path 26 can collectively present a total inductive impedance (L.sub.ETIC+L.sub.TRACE) to the power amplifier circuit 14. The power amplifier circuit 14 and the antenna circuit 18, on the other hand, can collectively present a total load impedance R.sub.LOAD, which is primarily a resistance, to the ETIC 16. The total load impedance R.sub.LOAD may interact with the modulate voltage V.sub.CC to cause a load current I.sub.LOAD.

[0033] Specifically, the ETIC 16 is configured to provide the modulated voltage Von to an output stage in each of the power amplifiers 20(1)-20(X). In this regard, FIG. 2 is a schematic diagram providing an exemplary illustration of an output stage 28 in each of the power amplifiers 20(1)-20(X) of the power amplifier circuit 14 in FIG. 1. Common elements between FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described herein.

[0034] The output stage 28 can include at least one transistor 30, such as a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor. Taking the BJT as an example, the transistor 30 can include a base electrode B, a collector electrode C, and an emitter electrode E. The base electrode B is configured to receive a bias voltage VBIAS, and the collector electrode C is coupled to the conductive path 26 to receive the modulated voltage V.sub.CC and output a respective one of the amplified RF signals 24(1)-24(X) to a respective one of the antennas 22(1)-22(X).

[0035] The modulated voltage V.sub.CC can cause a respective one of multiple modulated currents I.sub.CC-1-I.sub.CC-X in the output stage 28. Each of the modulated currents I.sub.CC-1-I.sub.CC-X is a function of a respective one of the time-variant power envelopes P.sub.IN-1-P.sub.IN-X. In this regard, the amplified RF signals 24(1)-24(X) will each be associated with a respective one of multiple time-variant output power envelopes P.sub.OUT-1-P.sub.OUT-X that is a function of the modulated voltage V.sub.CC and the respective one of the modulated currents I.sub.CC-1-I.sub.CC-X.

[0036] With reference back to FIG. 1, the total inductive impedance (L.sub.ETIC+L.sub.TRACE) may exhibit a memory effect that can cause degraded RF performance in the multi-antenna transmission circuit 10. Moreover, the total inductive impedance (L.sub.ETIC+L.sub.TRACE) can interact with each of the modulated currents I.sub.CC-1-I.sub.CC-X to create a ripple in the modulated voltage V.sub.CC at the collector electrode C of the transistor 30 in each of the power amplifiers 20(1)-20(X). In this regard, it is desirable to suppress the ripple in the modulated voltage V.sub.CC to help improve RF performance of the multi-antenna transmission circuit 10.

[0037] In this regard, as described in detail below, the transceiver circuit 12 is configured to perform window-based envelope tracking to determine at least one voltage compensation V.sub.TERM that can suppress the ripple in the modulated voltage V.sub.CC. Accordingly, the transceiver circuit 12 can add the determined voltage compensation V.sub.TERM in the modulated target voltage V.sub.TGT to thereby suppress the ripple in the modulated voltage V.sub.CC and improve the RF performance of the multi-antenna transmission circuit 10.

[0038] According to an embodiment of the present disclosure, the transceiver circuit 12 includes a signal processing circuit 32, an envelope detector circuit 34, and a target voltage circuit 36. Specifically, the signal processing circuit 32 is configured to generate the RF signals 24(1)-24(X) from a time-variant digital input vector b.sub.MOD.sup..fwdarw..

[0039] The envelope detector circuit 34 is configured to generate multiple time-variant amplitude envelopes A.sub.IN-1-A.sub.IN-X, each of which is in a digital format and corresponds to a respective one of the time-variant power envelopes P.sub.IN-1-P.sub.IN-X, based on the time-variant digital input vector b.sub.MOD.sup..fwdarw.. Accordingly, the target voltage circuit 36 can be configured to generate a combination of the voltage compensation V.sub.TERM and the modulated target voltage V.sub.TGT based on the time-variant amplitude envelopes A.sub.IN-1-A.sub.IN-X.

[0040] Specific embodiments of the signal processing circuit 32, the envelope detector circuit 34, and the target voltage circuit 36 are now described. FIG. 3 is a schematic diagram of the signal processing circuit 32 in the transceiver circuit 12 in FIG. 1. Common elements between FIGS. 1 and 3 are shown therein with common element numbers and will not be re-described herein.

[0041] According to an embodiment, the signal processing circuit 32 includes a modulator circuit 38 and a beamformer circuit 40. The modulator circuit 38 is configured to generate a modulated RF signal 42 from the time-variant digital input vector b.sub.MOD.sup..fwdarw.. In a non-limiting example, the modulated RF signal 42 is modulated to a carrier frequency, such as a millimeter wave (mmWave) frequency, for transmission via the antenna circuit 18. The beamformer circuit 40, on the other hand, is configured to preprocess the modulated RF signal 42 based on a beamforming codeword to generate the RF signals 24(1)-24(X). The beamforming codeword is a set of complex coefficients that collectively cause the antennas 22(1)-22(X) to simultaneously radiate the RF signals 24(1)-24(X) in the RF beam.

[0042] FIG. 4 is a schematic diagram of the envelope detector circuit 34 in the transceiver circuit 12 in FIG. 1. Common elements between FIGS. 1 and 4 are shown therein with common element numbers and will not be re-described herein.

[0043] In an embodiment, the digital input vector b.sub.MOD.sup..fwdarw. may be so generated to include an in-phase (I) component and a quadrature (Q) component. In this regard, the digital input vector b.sub.MOD.sup..fwdarw. will be associated with a time-variant amplitude ?{square root over (I.sup.2+Q.sup.2)}. Thus, the envelope detector circuit 34 is configured to include an amplitude detector circuit 44 that can detect the time-variant amplitude ?{square root over (I.sup.2+Q.sup.2)} of the time-variant digital input vector b.sub.MOD.sup..fwdarw.. The envelope detector circuit 34 further includes multiple scaler circuits 46(1)-46(X). Each scaler circuit 46(1)-46(X) is configured to scale the detected time-variant amplitude ?{square root over (I.sup.2+Q.sup.2)} based on a respective one of multiple scaling factors ?.sub.1-?.sub.X to thereby generate a respective one of the time-variant amplitude envelopes A.sub.IN-1-A.sub.IN-X.

[0044] Notably, the envelope detector circuit 34 may not have any knowledge about the time-variant power envelopes P.sub.IN-1-P.sub.IN-X. As such, the scaling factors ?.sub.1-?.sub.X need to be so determined to correlate the amplitude envelopes A.sub.IN-1-A.sub.IN-X with the time-variant power envelopes P.sub.IN-1-P.sub.IN-X, respectively. In one embodiment, the scaling factors ?.sub.1-?.sub.X may be predetermined and stored in the envelope detector circuit 34. In another embodiment, the scaling factors ?.sub.1-?.sub.X may be dynamically determined and provided to the envelope detector circuit 34.

[0045] With reference back to FIG. 1, according to an embodiment of the present disclosure, the target voltage circuit 36 includes a voltage processing circuit 48, a current processing circuit 50, a combiner circuit 52, and a digital-to-analog converter (DAC) 54. Specifically, the voltage processing circuit 48 is configured to generate a digital target voltage V.sub.DTGT based on a selected time-variant amplitude envelope among the time-variant amplitude envelopes A.sub.IN-1-A.sub.IN-X. The current processing circuit 50 is configured to generate the compensation term V.sub.TERM, which is a digital compensation term, based on all the time-variant amplitude envelopes A.sub.IN-1-A.sub.IN-X. The combiner circuit 52 is configured to add the compensation term V.sub.TERM into the digital target voltage V.sub.DTGT and the DAC 54 is configured to convert the digital target voltage V.sub.DTGT into the modulated target voltage V.sub.TGT.

[0046] FIG. 5 is a schematic diagram of the voltage processing circuit 48 in the transceiver circuit 12 in FIG. 1. Common elements between FIGS. 1 and 5 are shown therein with common element numbers and will not be re-described herein.

[0047] According to an embodiment of the present disclosure, the voltage processing circuit 48 includes a multiplexer 56, a windowed peak detector circuit 58, a lookup table (LUT) circuit 60, a current estimator 62, an equalizer 64, and a combiner 66. The multiplexer 56 is configured to output the selected time-variant amplitude envelope among the time-variant amplitude envelopes A.sub.IN-1-A.sub.IN-X. In an embodiment, the selected time-variant amplitude envelope is a maximum time-variant amplitude envelope PIN-MAX (PIN-MAX E (P.sub.IN-1-P.sub.IN-X)) of the time-variant amplitude envelopes A.sub.IN-1-A.sub.IN-X.

[0048] The windowed peak detector circuit 58 is configured to detect a set of peak amplitudes A.sub.PK-1-A.sub.PK-Y (Y<X) of the selected time-variant amplitude envelope (a.k.a. PIN-MAX) by performing window-based envelope tracking. FIGS. 6A and 6B are graphic diagrams providing exemplary illustrations of the window-based envelope tracking as performed by the transceiver circuit 12 in FIG. 1.

[0049] In a nutshell, the window-based envelope tracking involves taking one or more amplitude samples of the selected time-variant amplitude envelope (a.k.a. P.sub.IN-MAX) in each of multiple sampling windows W1-WN and select one or more highest ones of the amplitude samples taken in each of the multiple sampling windows W.sub.1-W.sub.N to thereby generate the set of peak amplitudes A.sub.PK-1-A.sub.PK-Y. Herein, an exact number of the amplitude samples that are sampled in each of the multiple sampling windows W.sub.1-W.sub.N is denoted by a grouping factor K (K?1).

[0050] In a non-limiting example, the grouping factor K can be determined based on a modulation bandwidth of the RF signals 24(1)-24(X). Herein, the grouping factor K is equal to one (K=1) if the modulation bandwidth is below a defined threshold (e.g., 200 MHz). In this regard, the windowed peak detector circuit 58 will take one amplitude sample of the selected time-variant amplitude envelope (a.k.a. P.sub.IN-MAX) in each of the multiple sampling windows W.sub.1-W.sub.N. As such, the set of peak amplitudes A.sub.PK-1-A.sub.PK-Y will be the same as the amplitude samples taken in the sampling windows W.sub.1-W.sub.N.

[0051] In contrast, the grouping factor K will be greater than one (e.g., K>1) if the modulation bandwidth is above or equal to the defined threshold. As an example, if the grouping factor K is set to be equal to two (K=2), the windowed peak detector circuit 58 will take two amplitude samples of the selected time-variant amplitude envelope (a.k.a. P.sub.IN-MAX) in each of the multiple sampling windows W.sub.1-W.sub.N. Accordingly, the set of peak amplitudes A.sub.PK-1-A.sub.PK-Y will include one-half (?) of the amplitude samples taken in the sampling windows W.sub.1-W.sub.N.

[0052] In an embodiment, the windowed peak detector circuit 58 may receive a bandwidth indication 68, for example from a digital baseband circuit (not shown) that generates the digital input vector b.sub.MOD.sup..fwdarw., that indicates the modulation bandwidth and determines the grouping factor K accordingly.

[0053] FIG. 6A provides an exemplary illustration of the windowed peak detector circuit 58 in FIG. 5 configured to take two amplitude samples 70 (K=2) in each of the multiple sampling windows W.sub.1-W.sub.N. FIG. 6B provides an exemplary illustration of the windowed peak detector circuit 58 in FIG. 5 configured to select a peak amplitude 72 from the amplitude samples 70 taken in each of the multiple sampling windows W.sub.1-W.sub.N to thereby generate the set of peak amplitude samples A.sub.PK-1-A.sub.PK-Y.

[0054] With reference back to FIG. 5, the LUT circuit 60 is configured to generate the digital target voltage V.sub.DTGT based on the set of peak amplitudes A.sub.PK-1-A.sub.PK-Y detected in the sampling windows W.sub.1-W.sub.N. The current estimator 62 is configured to estimate the load current I.sub.LOAD in the power amplifier circuit 14, which is a function of the modulated voltage V.sub.CC and the total load impedance R.sub.LOAD (I.sub.LOAD=V.sub.CC/R.sub.LOAD). The equalizer 64 is configured to generate a load current compensation term V.sub.TERM-LOAD to suppress the ripple in the modulated voltage V.sub.CC that is caused by the estimated load current I.sub.LOAD. The combiner 66 is configured to add the load current compensation term V.sub.TERM-LOAD to the digital target voltage V.sub.DTGT.

[0055] FIG. 7 is a schematic diagram of the current processing circuit 50 in the transceiver circuit 12 in FIG. 1. Common elements between FIGS. 1 and 7 are shown therein with common element numbers and will not be re-described herein.

[0056] Herein, the current processing circuit 50 includes multiple current LUT circuits 74(1)-74(X), a summing circuit 76, and a filter circuit 78. The current LUT circuits 74(1)-74(X) are each configured to generate a respective one of multiple digital current terms I.sub.TERM-1-I.sub.TERM-X that correspond to a respective one of the time-variant amplitude envelopes A.sub.IN-1-A.sub.IN-X. The summing circuit 76 is configured to sum up the digital current terms I.sub.TERM-1-I.sub.TERM-X to generate a time-variant digital current term I.sub.TERM. The filter circuit 78 is configured to generate the compensation term V.sub.TERM based on the time-variant digital current term I.sub.TERM to compensate for the ripple in the modulated voltage V.sub.CC that is a function of the total inductive impedance (L.sub.ETIC+L.sub.TRACE) presented at the power amplifier circuit 14.

[0057] The current processing circuit 50 may also include an adjustable delay circuit 80. The adjustable delay circuit 80 may be coupled between the summing circuit 76 and the filter circuit 78. The adjustable delay circuit 80 may be configured to introduce an adjustable delay term ?.sub.1 into the time-variant digital current term I.sub.TERM. The adjustable delay term ?.sub.1 may be determined (e.g., via experiment) to cause the modulated currents I.sub.CC-1-I.sub.CC-X to each be time aligned with the modulated voltage V.sub.CC at the power amplifier circuit 14.

[0058] With reference back to FIG. 5, the voltage processing circuit 48 may include a second delay circuit 82. The second delay circuit 82 may introduce a second adjustable delay term ?.sub.2 into the modulated digital target voltage V.sub.DTGT.

[0059] With reference back to FIG. 3, the signal processing circuit 32 may include a third delay circuit 84. The third delay circuit 84 may be configured to introduce a third adjustable delay term ?.sub.3 into the digital input vector b.sub.MOD.sup..fwdarw.. In this regard, the adjustable delay term ?.sub.1, the second adjustable delay term ?.sub.2, and/or the third adjustable delay term ?.sub.3 may be adjusted to ensure proper alignment among the modulated voltage V.sub.CC, the modulated currents I.sub.CC-1-I.sub.CC-X, and the time-variant power envelope P.sub.IN-1-P.sub.IN-X at the power amplifier circuit 14.

[0060] In an embodiment, the signal processing circuit 32 may also include a windowing buffer 86. The windowing buffer 86 may be configured to temporally buffer the digital input vector b.sub.MOD.sup..fwdarw. based on the grouping factor K. The signal processing circuit 32 may further include a memory digital predistortion (mDPD) circuit 88. The mDPD circuit 88 can be configured to digitally pre-distort the digital input vector b.sub.MOD.sup..fwdarw. before the modulator circuit 38 generates the modulated RF signal 42.

[0061] FIG. 8 is a schematic diagram of an exemplary multi-antenna transmission circuit 90 configured according to an alternative embodiment of the present disclosure. Common elements between FIGS. 1 and 8 are shown therein with common element numbers and will not be re-described herein.

[0062] The multi-antenna transmission circuit 90 includes a target voltage circuit 91, which further includes a voltage processing circuit 92, a current processing circuit 94, an analog combiner 96, and multiple DACs 98(1)-98(X). The DACs 98(1)-98(X) are configured to convert the amplitude envelopes A.sub.IN-1-A.sub.IN-X into analog amplitude envelopes. The voltage processing circuit 92 is configured to generate the modulated target voltage V.sub.TGT, which is an analog target voltage, based on the analog amplitude envelopes. The current processing circuit 94 is configured to generate the compensation term V.sub.TERM, which is an analog compensation term, based on the analog amplitude envelopes. The analog combiner 96 is configured to add the compensation term V.sub.TERM into the modulated target voltage V.sub.TGT.

[0063] The multi-antenna transmission circuit 10 of FIG. 1 and the multi-antenna transmission circuit 90 of FIG. 8 can be provided in a user element (e.g., a wireless device) to enable memory distortion neutralization according to embodiments described above. In this regard, FIG. 9 is a schematic diagram of an exemplary user element 100 wherein the multi-antenna transmission circuit 10 of FIG. 1 and the multi-antenna transmission circuit 90 of FIG. 8 can be provided.

[0064] Herein, the user element 100 can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0065] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0066] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 110. The multiple antennas 112 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0067] In an embodiment, it is possible to perform window-based envelope tracking in the multi-antenna transmission circuit 10 of FIG. 1 and the multi-antenna transmission circuit 90 of FIG. 8 based on a process. In this regard, FIG. 10 is a flowchart of an exemplary process 200 for performing window-based envelope tracking in the multi-antenna transmission circuit 10 of FIG. 1 and the multi-antenna transmission circuit 90 of FIG. 8.

[0068] Herein, the process 200 includes amplifying the RF signals 24(1)-24(X), each of which has a respective one of the time-variant power envelopes P.sub.IN-1-P.sub.IN-X, based on the modulated voltage V.sub.CC (step 202). The process 200 also includes generating the modulated voltage V.sub.CC based on the modulated target voltage V.sub.TGT (step 204). The process 200 also includes generating the plurality of RF signals 24(1)-24(X) from the time-variant digital input vector b.sub.MOD.sup..fwdarw. (step 206). The process 200 also includes generating the time-variant amplitude envelopes A.sub.IN-1-A.sub.IN-X based on the time-variant digital input vector b.sub.MOD.sup..fwdarw. to each correspond to a respective one of the time-variant power envelopes P.sub.IN-1-P.sub.IN-X (step 208). The process 200 also includes generating the modulated target voltage V.sub.TGT based on a selected time-variant amplitude envelope among the time-variant amplitude envelopes A.sub.IN-1-A.sub.IN-X (step 210).

[0069] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.