METHOD FOR MANUFACTURING METAL GATE

Abstract

The present application provides a method for manufacturing a metal gate, comprising: step 1: forming a polysilicon dummy gate on a semiconductor substrate; step 2: forming low dielectric constant sidewalls, comprising: step 21: forming a first protective layer; step 22: forming a second low dielectric constant layer; step 23: forming a third protective layer; and step 24: performing blank etching, and forming the low dielectric constant sidewalls by stacking the first protective layer, the second low dielectric constant layer, and the third protective layer on the side surfaces of the polysilicon dummy gate; step 3: forming a zeroth interlayer film; and step 4: performing gate replacement, comprising: step 41: removing the polysilicon dummy gate, and forming a gate trench; and step 42: forming a metal gate in the gate trench.

Claims

1. A method for manufacturing a metal gate of a semiconductor device, comprising following steps: step 1: providing a semiconductor substrate, forming a polysilicon dummy on the semiconductor substrate, wherein a spacer region is configured to be around the polysilicon dummy gate, and forming a first gate dielectric layer between the polysilicon dummy gate and a surface of the semiconductor substrate; step 2: forming low dielectric constant sidewalls on side surfaces of the polysilicon dummy gate, wherein the step 2 comprises following sub-steps: step 21: forming a first protective layer, wherein the first protective layer is disposed on the side surfaces and a top surface of the polysilicon dummy gate, and wherein the first protective layer is also disposed on a portion of the surface of the semiconductor substrate not under the polysilicon dummy gate; step 22: forming a second low dielectric constant layer on a surface of the first protective layer, wherein the first protective layer has a higher thermal stability and a higher etching resistance than a thermal stability and an etching resistance of the second low dielectric constant layer; step 23: forming a third protective layer on a surface of the second low dielectric constant layer, wherein a thermal stability and an etching resistance of the third protective layer are higher than the thermal stability and etching resistance of the second low dielectric constant layer, wherein low dielectric constant sidewalls are formed comprising the first, the second and the third low dielectric constant layers in the spacer region at sides of the polysilicon dummy gate; and step 24: removing by etching the low dielectric constant sidewalls in the spacer region from the top surface of the polysilicon dummy gate, and from a portion of the surface of the semiconductor substrate not under the low dielectric constant sidewalls; and step 3: forming a zeroth interlayer film on sides of the remaining low dielectric constant sidewalls in the spacer region; and step 4: performing gate replacement, wherein the step 4 comprises following sub-steps: step 41: removing the polysilicon dummy gate, and forming a gate trench from where the polysilicon dummy gate is removed; and step 42: forming a metal gate in the gate trench.

2. The method for manufacturing the metal gate according to claim 1, wherein a material of the second low dielectric constant layer is SiOCN.

3. The method for manufacturing the metal gate according to claim 2, wherein a material of the first protective layer is SiCN.

4. The method for manufacturing the metal gate according to claim 3, wherein a material of the third protective layer is SiCN.

5. The method for manufacturing the metal gate according to claim 4, wherein the second low dielectric constant layer is grown by means of an ALD process in step 22.

6. The method for manufacturing the metal gate according to claim 5, wherein the first protective layer is grown by means of the ALD process in step 21; wherein the third protective layer is grown by means of the ALD process in step 23; and Wherein a continuous growth in a same ALD process chamber is implemented in step 21, step 22, and step 23.

7. The method for manufacturing the metal gate according to claim 1, wherein the semiconductor substrate comprises a silicon substrate.

8. The method for manufacturing the metal gate according to claim 7, further comprising a step of forming a source region and a drain region on both sides of the polysilicon dummy gate after step 2 and before step 3.

9. The method for manufacturing the metal gate according to claim 8, wherein the semiconductor device is a FinFET; wherein a fin is formed on the semiconductor substrate in step 1, wherein the fin is formed by etching the semiconductor substrate; and wherein the polysilicon dummy gate is disposed on a top surface and side surfaces of the fin.

10. The method for manufacturing the metal gate according to claim 1, wherein a hard mask layer is further formed on the top surface of the polysilicon dummy gate in step 1; and wherein the first protective layer is further disposed on a surface of the hard mask layer in step 21.

11. The method for manufacturing the metal gate according to claim 1, further comprising a following step before forming the zeroth interlayer film in step 3: forming a contact etch stop layer, wherein the contact etch stop layer is disposed on the side surfaces of the low dielectric constant sidewalls, the top surface of the polysilicon dummy gate, and a portion of the the surface of the semiconductor substrate not under the polysilicon dummy gate.

12. The method for manufacturing the metal gate according to claim 11, wherein the step of forming the zeroth interlayer film in step 3 further comprises: performing a process of depositing the zeroth interlayer film to fill the spacer region and to extend to the top surface of the polysilicon dummy gate outside the spacer region; and performing a chemical mechanical polishing process to remove the contact etch stop layer and the zeroth interlayer film from the top surface of the polysilicon dummy gate, wherein a top surface of the zeroth interlayer film in the spacer region is flush with the top surface of the polysilicon dummy gate.

13. The method for manufacturing the metal gate according to claim 1, wherein the first gate dielectric layer comprises a high dielectric constant layer, wherein step 41 does not remove the first gate dielectric layer, and wherein step 42 forms a gate structure by stacking the first gate dielectric layer and the metal gate; or wherein step 41 removes the first gate dielectric layer, wherein the method further comprises a step of forming a second gate dielectric layer before forming the metal gate, wherein the second gate dielectric layer comprises a high dielectric constant layer, and wherein step 42 forms a gate structure by stacking the second gate dielectric layer and the metal gate.

14. The method for manufacturing the metal gate according to claim 13, wherein the process of forming the metal gate in step 42 further comprises: forming a metal work function layer; and forming a metal conductive material layer.

15. The method for manufacturing the metal gate according to claim 14, wherein a material of the metal conductive material layer comprises tungsten; wherein a material of the metal work function layer of an NMOS device comprises TiAl; and wherein a material of the metal work function layer of a PMOS device comprises TiN.

16. The method for manufacturing the metal gate according to claim 8, further comprising a step of forming contacts on top surfaces of the metal gate, the source region, and the drain region after step 4.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The present application is further described in detail below with reference to the drawings and specific embodiments:

[0064] FIG. 1A to FIG. 1G are cross sectional views of device structures in steps of manufacturing a metal gate with the existing method

[0065] FIG. 2 is a flowchart of a method for manufacturing a metal gate according to an embodiment of the present application.

[0066] FIG. 3A to FIG. 3H are cross sectional views of device structures in steps of manufacturing a metal gate with the method according to an embodiment of the present application.

DETAILED DESCRIPTION

[0067] FIG. 2 is a flowchart of the method for manufacturing a metal gate according to an embodiment of the present application. FIG. 3A to FIG. 3H are cross sectional views of device structures in steps of manufacturing a metal gate according to an embodiment of the present application. The method for manufacturing a metal gate with the method according to the embodiment of the present application includes the following steps:

[0068] Step 1. Referring to FIG. 3A, a semiconductor substrate 201 is provided, and a plurality of polysilicon dummy gates 202 are formed on the semiconductor substrate 201, wherein there is a spacer region between the polysilicon dummy gates 202, and a first gate dielectric layer is formed between the polysilicon dummy gate 202 and the semiconductor substrate 201.

[0069] In the embodiment of the present application, the semiconductor substrate 201 includes a silicon substrate.

[0070] A hard mask layer 203 is formed on top of the polysilicon dummy gate 202. The hard mask layer 203 is formed by stacking a first hard mask layer 203a and a second hard mask layer 203b. The material of the first hard mask layer 203a includes silicon oxide, and the material of the second hard mask layer 203b includes silicon nitride. In the process of patterning the polysilicon dummy gate 202, the hard mask layer 203 is etched first, and then polysilicon is etched using the hard mask layer 203 as a mask to form the polysilicon dummy gate 202.

[0071] Step 2. The low dielectric constant sidewalls 204 are formed on the side surfaces of the polysilicon dummy gate 202, including the following sub-steps:

[0072] Step 21. Referring to FIG. 3B, a first protective layer 204a is formed, wherein the first protective layer 204a covers the side surfaces and top surface of the polysilicon dummy gate 202 and the surface of the semiconductor substrate 201 outside the polysilicon dummy gate 202, and the thermal stability and etching resistance of the first protective layer 204a are higher than the thermal stability and etching resistance of a second low dielectric constant layer 204b formed subsequently.

[0073] Since the hard mask layer 203 is formed on the top surface of the polysilicon dummy gate 202, the first protective layer 204a also covers the side surfaces and top surface of the hard mask layer 203.

[0074] Step 22. Referring to FIG. 3B, the second low dielectric constant layer 204b is formed, wherein the second low dielectric constant layer 204b is formed on the surface of the first protective layer 204a.

[0075] Step 23. Referring to FIG. 3B, a third protective layer 204c is formed, wherein the third protective layer 204c is formed on the surface of the second low dielectric constant layer 204b, and the thermal stability and etching resistance of the third protective layer 204c are higher than the thermal stability and etching resistance of the second low dielectric constant layer 204b.

[0076] In the embodiment of the present application, the material of the second low dielectric constant layer 204b is SiOCN.

[0077] The material of the first protective layer 204a is SiCN.

[0078] The material of the third protective layer 204c is also SiCN.

[0079] The second low dielectric constant layer 204b is grown by means of an ALD process in step 22.

[0080] The first protective layer 204a is grown by means of the ALD process in step 21; and the first protective layer 204a is grown by means of the ALD process in step 23.

[0081] Continuous growth in the same ALD process chamber is implemented in step 21, step 22, and step 23. The first protective layer 204a, the second low dielectric constant layer 204b, and the third protective layer 204c can be realized by means of gradient film growth, i.e., realized by designing three process sequences in similar ALD growth process.

[0082] Step 24. Referring to FIG. 3C, a stack layer combining the first protective layer 204a, the second low dielectric constant layer 204b, and the third protective layer 204c are fully etched, and the low dielectric constant sidewalls 204 are formed by stacking the first protective layer 204a, the second low dielectric constant layer 204b, and the third protective layer 204c on the side surfaces of the polysilicon dummy gate 202, wherein the first protective layer 204a, the second low dielectric constant layer 204b, and the third protective layer 204c on the top surface of the polysilicon dummy gate 202 and on the surface of the semiconductor substrate 201 outside the low dielectric constant sidewalls 204 are all removed.

[0083] Referring to FIG. 3C, the method further includes a step of forming a source region 205a and a drain region 205b of a semiconductor device in the semiconductor substrate 201 on both sides of the polysilicon dummy gate 202.

[0084] As the process node progresses, for example, when the process node reaches to and beyond 14 nm, FinFETs are replacing the semiconductor devices; in FinFETS, fins are formed by etching on the semiconductor substrate 201 in step 1, and the polysilicon dummy gate 202 are made the top surface and the side surfaces of the fin.

[0085] Step 3. Referring to FIG. 3D, a zeroth interlayer film 207 is formed in the spacer region.

[0086] In the embodiment of the present application, the method further includes the following step before forming the zeroth interlayer film 207:

[0087] A contact etch stop layer 206 is formed, wherein the contact etch stop layer 206 covers the side surfaces of the low dielectric constant sidewalls 204, the top surface of the polysilicon dummy gate 202, and the surface of the semiconductor substrate 201 outside the polysilicon dummy gate 202.

[0088] The step of forming the zeroth interlayer film 207 includes the following processes:

[0089] A process of depositing the zeroth interlayer film 207 is performed, wherein the deposited zeroth interlayer film 207 fills the spacer region and extends to the top of the polysilicon dummy gate 202 outside the spacer region.

[0090] Referring to FIG. 3E, a chemical mechanical polishing process is performed to remove the contact etch stop layer 206 and the zeroth interlayer film 207 on top of the polysilicon dummy gate 202 and to make the top surface of the zeroth interlayer film 207 in the spacer region flush with the top surface of the polysilicon dummy gate 202.

[0091] Step 4. Gate replacement is performed, including the following sub-steps:

[0092] Step 41. Referring to FIG. 3F, the polysilicon dummy gate 202 is removed, and a gate trench 208 in a region from which the polysilicon dummy gate 202 is removed is formed. In the process of removing the polysilicon dummy gate 202, the first protective layer 204a prevents the second low dielectric constant layer 204b from being etched.

[0093] In the embodiment of the present application, the first gate dielectric layer includes a high dielectric constant layer, the first gate dielectric layer is remained in step 41, and a gate structure is formed by stacking the first gate dielectric layer and the metal gate after step 42 is completed. In other embodiments, the first gate dielectric layer is removed in step 41, the method further includes a step of forming a second gate dielectric layer before forming the metal gate, the second gate dielectric layer includes a high dielectric constant layer, and a gate structure is formed by stacking the second gate dielectric layer and the metal gate after step 42 is completed.

[0094] Step 42. A metal gate is formed in the gate trench 208.

[0095] The process of forming the metal gate includes the following sub-steps:

[0096] A metal work function layer 209 is formed.

[0097] A metal conductive material layer is formed.

[0098] The material of the metal conductive material layer 210 includes tungsten.

[0099] The material of the metal work function layer 209 of an NMOS device includes TiAl.

[0100] The material of the metal work function layer 209 of a PMOS device includes TiN.

[0101] The method further includes a step of forming contacts on the tops of the metal gate, the source region 205a, and the drain region 205b after step 4.

[0102] Step 2 of the embodiment of the present application is implemented by means of the gradient film growth. The three sequences are designed in the ALD process. First, in the first sequence, a SiCN film, i.e., the first protective layer 204a, is grown on the sidewalls close to the polysilicon dummy gate 202, and since SiCN has an ultra-low etching rate, it can be ensured that the SiCN film is not etched away during the process of removing the polysilicon dummy gate 202. In the second sequence, a SiOCN film, i.e., the second low dielectric constant layer 204b, is grown on the basis of the SiCN film in the first sequence, to ensure the low-k characteristic of the sidewalls. In the third sequence, on the basis of the above two sequences, a SiCN film, i.e., the third protective layer 204c, is grown on the outermost layer of the sidewalls of the polysilicon dummy gate 202, wherein the good thermal stability and etching resistance of SiCN ensure that, during the process of manufacturing the metal gate after the sidewalls are grown, there is no loss of the sidewalls resulting from the factors such as pickling, etching, and thermal oxidation. For example, in the etching process of step 24 and the process steps of forming the contact etching stop layer 206 and the zeroth interlayer film 207 in step 3, conventional process steps such as pickling, etching, and thermal oxidation are usually adopted. In these steps, since the third protective layer 204c covers the outer surface of the second low dielectric constant layer 204b, a loss on the outside of the second low dielectric constant layer 204b resulting from these processes can be avoided. The thickness of the gradient film growth mode is controllable, thus ensuring the low-k characteristic of the sidewalls while avoiding gate enlargement due to the loss of the sidewalls, and thereby avoiding the short circuit between the source/drain contact and the gate caused by the gate enlargement.

[0103] In the embodiment of the present application, during the process of forming the low dielectric constant sidewalls 204, the low dielectric constant sidewalls 204 are not formed by directly depositing a low dielectric constant layer and then performing blank etching, but is formed by sequentially forming the first protective layer 204a, the second low dielectric constant layer 204b, and the third protective layer 204c and then performing blank etching, so that the first protective layer 204a and the third protective layer 204c respectively protect the inner side and the outer side of the second low dielectric constant layer 204b, in which case the sidewalls have the properties of a low dielectric constant, antioxidation, and anti-etching. The third protective layer 204c can fill the spacer region before the gate replacement process, avoiding a loss on the outside of the second low dielectric constant layer 204b resulting from the factors such as pickling, etching, or thermal oxidation. The first protective layer 204a can prevent the second low dielectric constant layer 204b from being etched from the inside during the process of removing the polysilicon dummy gate 202. Therefore, the embodiment of the present application can achieve the low dielectric constant sidewalls 204, thus reducing the parasitic capacitance between the source/drain contact 211 and the gate, while avoiding a loss of the low dielectric constant sidewalls 204 in the process, thereby avoiding gate enlargement and avoiding the short circuit between the source/drain contact 211 and the gate.

[0104] The present application is described above in detail via specific embodiments, but these embodiments do not intended to limit the present application. Without departing from the principle of the present application, those skilled in the art can make many modifications and improvements, which shall also be regarded as the protection scope of the present application.