ISOLATION COMMUNICATIONS CHANNEL USING DIRECT DEMODULATION AND DATA-EDGE ENCODING

Abstract

An apparatus for communicating across an isolation barrier includes a differential pair of input terminals. The apparatus includes a bandpass filter circuit configured to receive a received signal on the differential pair of input terminals and to provide a received differential signal on a differential pair of nodes. The apparatus includes a demodulator directly coupled to the bandpass filter circuit and configured to directly demodulate the received differential signal on the differential pair of nodes to provide a demodulated received signal.

Claims

1. An apparatus for communicating across an isolation barrier, the apparatus comprising: a differential pair of input terminals; a bandpass filter circuit configured to receive a received signal on the differential pair of input terminals and to provide a received differential signal on a differential pair of nodes; and a demodulator directly coupled to the bandpass filter circuit and configured to directly demodulate the received differential signal on the differential pair of nodes to provide a demodulated received signal.

2. The apparatus, as recited in claim 1, further comprising: a transmitter path comprising an oscillator circuit configured to provide an oscillating signal to a differential pair of output terminals in response to a control signal, wherein the bandpass filter circuit includes a first inductor and a first capacitor matched to a second inductor and a second capacitor of the oscillator circuit.

3. The apparatus, as recited in claim 1, wherein the bandpass filter circuit is configured to amplify a first frequency band of the received signal and to attenuate a second frequency band of the received signal, a carrier signal of the received signal being in the first frequency band and common-mode transient interference of the received signal being in the second frequency band.

4. The apparatus, as recited in claim 1, wherein the demodulator comprises: a differential pair of transistors, each transistor of the differential pair of transistors having a corresponding source terminal coupled to a corresponding node of the differential pair of nodes.

5. The apparatus, as recited in claim 4, wherein the demodulator further comprises: a reference transistor having a first size greater than a sum of second sizes of transistors of the differential pair of transistors.

6. The apparatus, as recited in claim 5, wherein an offset threshold of the demodulator is determined by a ratio of the first size of the reference transistor and a second size of each transistor of the differential pair of transistors.

7. The apparatus, as recited in claim 5, wherein the demodulator further comprises: a first resistor coupled between a common node coupled to a first source terminal of the reference transistor and a second source terminal of a first transistor of the differential pair of transistors; and a second resistor coupled between the common node and a third source terminal of a second transistor of the differential pair of transistors, the first resistor and the second resistor having the same resistance.

8. The apparatus, as recited in claim 5, wherein the demodulator further comprises: a bias transistor having a first gate terminal coupled to second gate terminals of the differential pair of transistors and a third gate terminal of the reference transistor.

9. The apparatus, as recited in claim 1, further comprising: a digital circuit configured to provide a received digital signal based on the demodulated received signal, wherein the digital circuit is configured to toggle the received digital signal to a first logic value in response to a pulse of the demodulated received signal having a first width and configured to toggle the received digital signal to a second logic value in response to a second pulse of the demodulated received signal having a second width.

10. The apparatus, as recited in claim 1, further comprising: an oscillator circuit coupled to a differential pair of output terminals and configured to transmit a signal using the differential pair of output terminals according to a transmit data signal received on a center tap of an inductor of the oscillator circuit; and a control circuit configured to generate the transmit data signal having a first modulated pulse with a first pulse width in response to a first transition of an input data signal and to generate a second modulated pulse having a second pulse width in response to a second transition of the input data signal, the first pulse width being greater than the second pulse width.

11. A method for communicating across an isolation barrier, the method comprising: bandpass filtering a received signal on a differential pair of input terminals to provide a received differential signal on a differential pair of nodes; and directly demodulating the received differential signal on the differential pair of nodes to provide a demodulated received signal.

12. The method, as recited in claim 11, wherein directly demodulating comprises: biasing a differential pair of transistors; receiving the received differential signal on first source terminals of the differential pair of transistors; and generating an indication of a difference between a first voltage on drain terminals of the differential pair of transistors to a second voltage on a drain of a reference transistor.

13. The method, as recited in claim 11, further comprising: decoding a first value of a digital signal based on first pulse having a first pulse width; and decoding a second value of the digital signal based on a second pulse having a second pulse width smaller than the first pulse width.

14. The method, as recited in claim 11, wherein the bandpass filtering amplifies a first frequency band of the received signal and attenuates a second frequency band of the received signal, a carrier signal of the received signal being in the first frequency band and common-mode transient interference of the received signal being in the second frequency band.

15. The method, as recited in claim 11, further comprising: selectively configuring a first instantiation of an LC circuit on a first integrated circuit die as an LC oscillator circuit; and selectively configuring a second instantiation of the LC circuit on a second integrated circuit die as a bandpass filter circuit.

16. The method, as recited in claim 11, further comprising: transmitting across the isolation barrier, a first modulated pulse in response to a first transition of a data signal and a second modulated pulse in response to a next transition of the data signal, wherein the first modulated pulse has a first pulse width and the second modulated pulse has a second pulse width different from the first pulse width.

17. A method for communicating across an isolation barrier, the method comprising: generating data-edge-encoded signal based on a data signal using an LC oscillator circuit; and transmitting the data-edge-encoded signal across the isolation barrier.

18. The method, as recited in claim 17, wherein generating the data-edge-encoded signal comprises: generating a first modulated pulse in response to a first transition of the data signal; and generating a second modulated pulse in response to a next transition of the data signal, wherein the first modulated pulse has a first pulse width and the second modulated pulse has a second pulse width different from the first pulse width.

19. The method, as recited in claim 18, wherein generating the data-edge-encoded signal further comprises: modulating a first pulse and a second pulse with a carrier signal having a first frequency much greater than a second frequency of common-mode transient noise to generate the first modulated pulse and the second modulated pulse.

20. The method, as recited in claim 17, further comprising: directly demodulating a received version of the data-edge-encoded signal received across the isolation barrier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0015] FIG. 1 illustrates a functional block diagram of an exemplary isolator system.

[0016] FIG. 2 illustrates a functional block diagram of an exemplary isolation communications system.

[0017] FIG. 3 illustrates waveforms for the isolator communications system of FIG. 2.

[0018] FIG. 4 illustrates a functional block diagram of an exemplary low-jitter isolator system.

[0019] FIG. 5 illustrates a circuit diagram of an exemplary oscillator of the low-jitter isolator system of FIG. 4.

[0020] FIG. 6 illustrates waveforms for the low-jitter isolator system of FIG. 4.

[0021] FIG. 7 illustrates a functional block diagram of an exemplary isolation communications system consistent with at least one embodiment of the invention.

[0022] FIG. 8 illustrates a functional block diagram of an exemplary transmitter of the isolation communications system of FIG. 7 consistent with at least one embodiment of the invention.

[0023] FIG. 9 illustrates a functional block diagram of an exemplary receiver front-end of the isolation communications system of FIG. 7 consistent with at least one embodiment of the invention.

[0024] FIG. 10 illustrates a circuit diagram of an exemplary demodulator of the isolation communications system of FIG. 7 consistent with at least one embodiment of the invention.

[0025] FIG. 11 illustrates a logic diagram of an exemplary encoding circuit of the isolation communications system of FIG. 7 consistent with at least one embodiment of the invention.

[0026] FIG. 12 illustrates a logic diagram of an exemplary decoding circuit of the isolation communications system of FIG. 7 consistent with at least one embodiment of the invention.

[0027] FIG. 13 illustrates exemplary waveforms for the isolation communications system of FIG. 7 consistent with at least one embodiment of the invention.

[0028] FIG. 14 illustrates a functional block diagram of an exemplary pulse width correction circuit of the receiver of the isolation communications system of FIG. 7 consistent with at least one embodiment of the invention.

[0029] The use of the same reference symbols in different drawings indicates similar or identical items.

DETAILED DESCRIPTION

[0030] An isolation communications system having low power consumption and common-mode transient immunity is described. The isolation communications system uses reliably enables data-edge-encoding and decoding that only enables the transmitter for a limited interval of the duty cycle during input data transition and provides a data-rate scalable ultra-low power channel operation. Referring to FIGS. 7 and 8, in at least one embodiment the isolation communications system includes transmitter 702 on a first integrated circuit die and receiver 704 on a second integrated circuit die that communicate across isolation barrier 725. In at least one embodiment, transmitter 702 includes an embodiment of oscillator 800 that includes passive on-chip inductor 802, capacitance 804, transistor 806, and transistor 808 and is configured to drive an oscillating signal on differential pair of nodes TXO+ and TXO−, which are coupled to isolation capacitors 720 of the isolation barrier. In at least one embodiment of isolation communications system 700, transistor 806 and transistor 808 are cross-coupled and are formed using gate oxide layers that are thicker than gate oxide layers of other transistors of isolation communications system 700 and have different breakdown voltages and speeds of operation than the other transistors that are formed from thinner gate oxide layers.

[0031] Unlike the ring oscillator described above, the oscillation frequency of oscillator 800, which is formed using an inductor and capacitor, is not limited by manufacturing process and easily achieves high frequency oscillation (e.g., a frequency of at least 5 GHz). High frequency oscillation increases the gain of the oscillator (e.g., increases at least ten times, i.e., 20 dB) as compared to using a carrier with a frequency of approximately 500 MHz. In addition, depending on the mode of oscillation (e.g., class-C or class-D operation), the amplitude of an oscillating signal generated by oscillator 800 can exceed VDD, thereby increasing the gain. In at least one embodiment, the oscillation frequency of an LC oscillator varies much less than the oscillation frequency of a CMOS-based oscillator, which may further relax receiver design. In at least one embodiment of transmitter 702, signal DATA and signal DATA_B control oscillator 800 according to an implementation of data-edge-encoded modulation scheme described further below.

[0032] A conventional receiver of an isolation communications channel includes a low input impedance, low pass front-end, followed by high-power gain stages that provide an amplified received signal to a demodulator. In at least one embodiment of isolation communications system 700, receiver 704 includes bandpass receiver front-end 710 that lowers the input impedance for the lower frequency common-mode transient signal to implement a relatively low common-mode transient signal gain (i.e., attenuates common-mode transient signals), and increases the input impedance for a high frequency carrier signal (e.g., 5 GHz) to implement a higher gain for the carrier signal. Accordingly, receiver front end 710 has a signal-to-noise ratio that is improved by Q.sup.2, as compared to a conventional receiver front end, where Q is the quality factor of the inductor of receiver front-end 710. Thus, receiver front end 710 reduces or eliminates common-mode transient interference using a moderate Q inductor and direct demodulation, described further below.

[0033] Referring to FIGS. 7 and 11, in at least one embodiment, digital circuit 708 receives a data signal TX_IN for transmission across isolation barrier 725. Digital circuit 708 generates signal TX_RISE, which includes an active pulse having a first pulse width in response to a rising edge of data signal TX_IN, and signal TX_FALL, which includes an active pulse having a second pulse width in response to a falling edge of data signal TX_IN. In at least one embodiment, circuit DELAY_L1 and circuit DELAY_L2 include paths having different delays, which causes the first pulse width and the second pulse width to be different. Note that digital circuit 708 is exemplary only and pulses of different durations in response to rising edges or falling edges of data signal TX_IN may be generated using different combinations of digital logic.

[0034] Referring to FIGS. 7, and 8, in at least one embodiment, signal DATA controls operation of transmitter front end 706 by selectively providing power to oscillator 800 according to the value of signal DATA. For example, when signal DATA has a first logic level (e.g., DATA=‘1’), then the center tap of inductor 802 is coupled to a power supply voltage (e.g., VDD) causing oscillator 800 to drive a differential oscillating signal on the differential pair of nodes TXO+ and TXO− coupled to isolation capacitors 720. When signal DATA has a second logic level (e.g., DATA=‘0’), then the center tap of inductor 802 is coupled to a second power supply voltage (e.g., ground) causing oscillator 706 to cease oscillation and to discharge the differential pair of nodes TXO+ and TXO−. In at least one embodiment, oscillator 800 is an LC oscillator and may have a class-A, class-B, class-C, or class-D oscillator topology.

[0035] Referring to FIGS. 7 and 9, in at least one embodiment, receiver front end 710 includes isolation capacitors 730 coupled to differential pair of nodes RXI+ and RXI−. In at least one embodiment, filter 900 is a parallel LC filter that amplifies the received carrier signal and attenuates common-mode transient noise. In at least one embodiment, resistors RCM separate differential pair of nodes RXI+ and RXI− and have resistances (e.g., 3 kΩ to 10 kΩ) that are sufficient to provide a bias path to node RX_VCM. In other embodiments, resistors RCM are excluded. Receiver front end 710 presents a high gain at the carrier signal frequency of an exemplary differential signal on differential pair of nodes RXI+ and RXI−. In at least one embodiment, receiver front end 710 has common-mode transient immunity to 200 kV/μs events. In at least one embodiment, differential signal on differential pair of nodes RXI+ and RXI− is relatively small (e.g., 10 mV). Referring to FIGS. 8 and 9, in at least one embodiment, oscillator 800 and filter 900 include matched LC components, e.g., inductor 802 and inductor 902 have the same inductance and capacitor 804 and capacitor 904 have the same capacitance.

[0036] Referring to FIGS. 7 and 10, in at least one embodiment of receiver 704, demodulator 712 is an offset-bias-free, low power, high-frequency differential signal demodulator circuit. Demodulator 712 has a threshold voltage determined by a ratio of transistor sizes of reference transistor 1008 and the combined size of transistor 1004 and transistor 1006. Demodulator 712 directly demodulates an AC signal received from receiver front-end 710 (i.e., demodulates the differential signal on differential nodes of the LC filter without additional amplification) to a demodulated received signal with relatively small delay (e.g., a delay of less than 20 ns). To enable data-rate scalability and an ultra-low power channel (e.g., current of less than 10 μA), isolation communications system 700 implements a data-edge decoding scheme to decode information received across the isolation barrier using a carrier signal, as discussed further below.

[0037] In at least one embodiment, receiver front end 710 is directly coupled to demodulator 712, i.e., no gain stages are coupled between filter 900 of receiver front end 710 and demodulator 712. The absence of gain stages between receiver front end 710 and demodulator 712 reduces power consumption of receiver 704 as compared to a conventional demodulator circuit. Differential pair of nodes RXI+ and RXI− are directly coupled to source terminals of a differential pair of transistors in demodulator 712. Demodulator 712 has a DC bias point at ground of receiver front end 710. Receiver front end 710 provides a filtered received signal to demodulator 712. In at least one embodiment, unlike the conventional demodulator topology that requires an offset voltage to make the signal positive, demodulator 712 does not generate an offset voltage for low input voltage biasing. The common mode voltage of the input signals and the DC bias point of demodulator 712 are approximately at ground of the LC network.

[0038] In at least one embodiment, demodulator 712 is an extremum detector (e.g., a peak detector or a valley detector). Transistors 1004 and transistor 1006 of the differential pair of transistors are the same size (e.g., one unit) and reference transistor 1008 has a size of 2.x times the size of transistor 1004 or transistor 1006 (e.g., 2.x units, where 0<x<10) to provide a relatively small bias signal and no other bias or offset voltage generation is used. Reference transistor 1008 sets a threshold voltage for the output level of demodulator 712. Bias transistor 1002 is configured to generate a bias voltage provided to the gate terminals of transistor 1004, transistor 1006, and reference transistor 1008. In at least one embodiment, resistors RCM between the source of reference transistor 1008 and the differential pair of nodes RXI+ and RXI− have resistances (e.g., 3 kΩ to 10 kΩ) that are sufficient to provide a bias path to node RX_VCM. In other embodiments, resistors RCM are excluded. The output on node 1007 has the carrier signal removed and is representative of the signal on differential pair of nodes RXI+ and RXI−. A current mirror formed by transistor 1012 and transistor 1014 sets the voltage on the drain of reference transistor 1008 and the gate of output transistor 1010.

[0039] In normal operation, demodulator 712 removes the carrier signal from a received differential pair of signals on differential pair of nodes RXI+ and RXI− and compares the demodulated signal to a reference signal to generate a logic ‘0’ signal or a logic ‘1’ signal based on the comparison. In at least one embodiment, demodulator 712 detects the lesser signal of the differential pair of signals. In at least one embodiment, demodulator 712 includes a minimum selector (or a maximum selector) that identifies which signal has the minimum (or the maximum, as the case may be) of greater magnitude. Demodulator 712 generates an indication of a difference between the voltage on node 1007 (e.g., generated by the current through node 1007, which is the sum of the currents through transistors 1004 and 1006) to the voltage on the drain terminal of transistor 1008 (e.g., generated by the current through the drain terminal of transistor 1008). If the signal on differential pair of nodes RXI+ and RXI− causes the current through node 1007 to be less than the current through transistor 1008, then the voltage on node 1007 is greater than the voltage on the drain of transistor 1008. If the voltage on node 1007 causes the gate-to-source voltage of output transistor 1010 to exceed the threshold voltage of transistor 1010, then transistor 1010 turns on, charges node 1011 and causes signal RX_OUT to have a low logic level. If the signal on differential pair of nodes RXI+ and RXI− causes the current through node 1007 to be greater than the current through transistor 1008, then the voltage on node 1007 is less than the voltage on the drain of transistor 1008. If the output of the differential node causes the gate-to-source voltage of output transistor 1010 to be below the threshold voltage of transistor 1010, then transistor 1010 is disabled, node 1011 discharges, causing signal RX_OUT to have a high logic level.

[0040] Referring to FIGS. 7 and 12, in at least one embodiment, demodulator 712 provides signal RX_OUT to digital circuit 714. Digital circuit 714 decodes a data edge pulse width of signal RX_OUT. For example, digital circuit 714 uses signal RX_OUT as a clock control signal that triggers storage of a value of intermediate signal RX_DATA in storage element 1112 on the falling edge of clock signal RX_CLK (e.g., RX_OUT). Intermediate signal RX_DATA includes a pulse indicating detection of a pulse having a first pulse width (e.g., a 40 ns pulse width) and in an embodiment is generated by introducing a minimum delay and an extended delay using circuit DELAY MIN and circuit DELAY_L2, logic device 1110, and buffer 1106, respectively. Digital circuit 714 sets the decoded received signal B_OUT in response to detecting the pulse having a first pulse width. Intermediate signal RX_DATA is reset (e.g., ‘0’) in response to detecting a second pulse having a second pulse width (e.g., a 20 ns pulse width) that is different from the first pulse width (e.g., a smaller pulse width), causing digital circuit 714 to reset the decoded received signal B_OUT in response to detecting the pulse having the second pulse width. Note that digital circuit 714 is exemplary only and other logic circuits may be used to generate decoded received signal B_OUT based on signal RX_OUT.

[0041] Referring to FIGS. 7 and 13, an exemplary embodiment of isolation communications system 700 implements a data-edge-triggered pulse-width encoding scheme that transmits a carrier signal for a first interval (i.e., transmits a modulated pulse) having a first width in response to a first transition of a data signal (e.g., a rising transition) and transmits the carrier signal for a second interval (i.e., transmits a modulated pulse) having a second width in response to a second transition of the data signal (e.g., a falling transition). For example, when data signal TX_IN transitions high, digital circuit 708 generates a pulse of signal TX_RISE and creates a corresponding pulse of signal DATA, which causes transmitter front end 706 to provide a modulated pulse of the carrier signal on TXO+ and TXO− for a first interval corresponding to a first pulse width, as illustrated by signal TX_OUT. In response, receiver 704 generates a pulse of signal RX_OUT having the first width and digital circuit 714 generates a pulse of the first width on signal RX_CLK used to capture the pulse of signal RX_DATA, thereby causing the digital signal B_OUT to transition high after time t.sub.1 from the rising edge of data signal TX_IN.

[0042] When data signal TX_IN transitions low, digital circuit 708 generates a pulse of signal TX_FALL having a second width and creates a corresponding pulse of signal DATA, which causes transmitter front end 706 to provide the carrier signal on TXO+ and TXO− for a second interval corresponding to a second pulse width, as illustrated by signal TX_OUT. In response, receiver 704 generates a pulse of signal RX_OUT having the second width and digital circuit 714 generates a pulse of the second width on signal RX_CLK used to capture a low level of signal RX_DATA, thereby causing the digital signal B_OUT to transition low after time t.sub.2 from the rising edge of data signal TX_IN.

[0043] In at least one embodiment, transmission of data using the data-edge encoding scheme can introduce a pulse width error into digital signal B_OUT. For example, the delay between a rising edge of data signal TX_IN to a corresponding rising edge of B_OUT includes the delay through the isolation communications channel (DELAY_CH) and the delay to the falling edge of the corresponding pulse on RX_OUT (DELAY_L1), i.e., t.sub.1=DELAY_CH+DELAY_L1 (e.g., approximately 30 ns+20 ns=50 ns). However, the delay between a falling edge of data signal TX_IN to a corresponding falling edge of digital signal B_OUT includes the delay through the isolation communications channel (e.g., DELAY_CH) and the delay to the falling edge of the corresponding pulse on RX_OUT (e.g., DELAY_S1), i.e., t.sub.2=DELAY_CH+DELAY_S1 (e.g., approximately 30 ns). Since the first pulse width is different from the second pulse width and DELAY_L1>DELAY_L2>DELAY_S1>DELAY_MIN2, digital signal B_OUT is high for a shorter interval than TX_IN is high. In at least one embodiment, pulse-width correction circuit 1400 adjusts the delay of the decoded signal to account for a pulse width error. For example, if DELAY_L1 is 40 ns, DELAY_L2 is 30 ns, DELAY_S1 is 20 ns, and DELAY_MIN2 is 5 ns, pulse width correction circuit 1400 delays the falling edge of B_OUT by an amount equal to DELAY_L1−DELAY_S1 (e.g., 40 ns−20 ns=20 ns).

[0044] In at least one embodiment of isolation communications system 700, an alternative to data-edge encoding and pulse width correction, isolation communications system 700 synchronizes the input and output process using a timer and generates a pulse of a predetermined width in response to a rising edge of data signal TX_IN, generates a pulse of the predetermined width in response to a falling edge of the data signal, and no pulse width distortion occurs. Such embodiments toggle digital signal B_OUT in response to detecting a pulse and no pulse width correction is needed.

[0045] In at least one embodiment of isolation communications system 700, an integrated circuit die including an integrated circuit inductor and capacitor and both receiver circuitry and transmitter circuitry can be digitally configured as a transmitter or a receiver of isolation communications system 700 by selectively coupling the integrated circuit inductor and capacitor using integrated circuit switches as part of oscillator 800 of FIG. 8 or as part of filter 900 of FIG. 9. Accordingly, the inductors and capacitors in embodiments of transmitter 702 and receiver 704 are matched because they are manufactured using the same manufacturing technology, are surrounded by the same integrated circuit devices, and are subject to the same process variations.

[0046] Thus, an isolation communications channel that directly demodulates an encoded signal received has common-mode transient immunity uses data-edge encoding scheme has been disclosed. The isolation communications channel consumes less power than conventional isolation communications channels and the power consumption is data rate dependent. The parallel LC filter used in the receiver front end increases signal gain while attenuating common-mode transient noise and improves the signal-to-noise ratio of the receiver by Q.sup.2, where Q is the quality factor of the inductor. Direct demodulation of the signal received across the isolation barrier reduces current consumption to less than 10 μA for a target manufacturing technology as compared to milli-Amps of current in conventional isolators.

[0047] The pulse-width data-edge encoding and decoding scheme and associated oscillator are enabled according to the data, thereby reducing power consumption as compared to other encoding and decoding schemes having an oscillator always enabled. During normal operation, sensing a single pulse's rising edge and toggling the output at the receiver and using direct demodulation reduces power, especially in applications using a substantial number of isolators or in applications having a relatively low data rate. However, common-mode transient immunity and the reduction in power consumption trades off potentially increased electromagnetic interference due to use of a higher carrier frequency. Use of the data-edge encoding and decoding scheme reduces the duty cycle, and thus reduces electromagnetic interference as compared to encoding schemes that have the oscillator enabled longer. In at least one embodiment, a conventional frequency spreading techniques can be employed to further reduce electromagnetic interference.

[0048] The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. For example, while the invention has been described in an embodiment in which an LC oscillator is used at the transmitter and a LC bandpass filter is used in the receiver, one of skill in the art will appreciate that the teachings herein can be utilized with other types of oscillators at the transmitter or other types of bandpass filters at the receiver. The terms “first,” “second,” “third,” and so forth, as used in the claims, unless otherwise clear by context, is to distinguish between different items in the claims and does not otherwise indicate or imply any order in time, location or quality. For example, “a first received signal,” “a second received signal,” does not indicate or imply that the first received network signal occurs in time before the second received network signal. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.